Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875300
Daniel Oliveira, P. Navaux, P. Rech
Selective hardening is a promising solution to efficiently improve the reliability of high performance and safety-critical real-time applications. One of the most significant challenges of selective hardening is to choose how many resources or code portions to protect to avoid unnecessary system performances degradation (at least 2x overhead for the naive duplication). In this paper, we propose a selective hardening strategy for parallel algorithms. We first identify through extensive fault-injection campaigns the code portions whose protection significantly increases the algorithm reliability. Then, we select the code portions that, once protected, maximize the reliability/overhead ratio. We can achieve fault coverage as high as 60% with a 3% overhead. We show that the hardening efficiency can be higher than 90% when compared to naive full duplication.
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Pub Date : 2019-09-01DOI: 10.1109/DFT.2019.8875379
M. Jenihhin, M. Reorda, A. Balakrishnan, D. Alexandrescu
The gigantic complexity and heterogeneity of today's advanced cyber-physical systems and systems of systems is multiplied by the use of avant-garde computing architectures to employ artificial intelligence based autonomy in the system. Here, the overall system's reliability comes along with requirements for fail-safe, fail-operational modes specific to the target applications of the autonomous system and adopted HW architectures. The paper makes an overview of reliability challenges for intelligence implementation in autonomous systems enabled by HW backbones such as neuromorphic architectures, approximate computing architectures, GPUs, tensor processing units (TPUs) and SoC FPGAs.
{"title":"Challenges of Reliability Assessment and Enhancement in Autonomous Systems","authors":"M. Jenihhin, M. Reorda, A. Balakrishnan, D. Alexandrescu","doi":"10.1109/DFT.2019.8875379","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875379","url":null,"abstract":"The gigantic complexity and heterogeneity of today's advanced cyber-physical systems and systems of systems is multiplied by the use of avant-garde computing architectures to employ artificial intelligence based autonomy in the system. Here, the overall system's reliability comes along with requirements for fail-safe, fail-operational modes specific to the target applications of the autonomous system and adopted HW architectures. The paper makes an overview of reliability challenges for intelligence implementation in autonomous systems enabled by HW backbones such as neuromorphic architectures, approximate computing architectures, GPUs, tensor processing units (TPUs) and SoC FPGAs.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114328937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-22DOI: 10.1109/DFT.2019.8875468
N. Foutris, Christos Kotselidis, M. Luján
As the silicon industry moves into deep nanoscale technologies, preserving Mean Time to Failure at acceptable levels becomes a first-order challenge. The operational stress, along with the inefficient power dissipation and the unsustainable thermal thresholds increase the wear-induced failures. As a result, faster wear-out leads to earlier performance degradation with eventual device breakdown. Furthermore, the proliferation of asymmetric multicores is tightly coupled with an increasing susceptibility to variable wear-out rate within the components of processors. This paper investigates the reliability boundaries of asymmetric multicores, which span from embedded systems to high performance computing domains, by performing a continuous-operation reliability assessment. As our experimental analysis illustrates, the variation between the least and the most aged hardware resource equals to 2.6 years. Motivated by this finding, we show that an MTTF-aware, asymmetric configuration prolongs its lifetime by 21%.
{"title":"Simulating Wear-out Effects of Asymmetric Multicores at the Architecture Level","authors":"N. Foutris, Christos Kotselidis, M. Luján","doi":"10.1109/DFT.2019.8875468","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875468","url":null,"abstract":"As the silicon industry moves into deep nanoscale technologies, preserving Mean Time to Failure at acceptable levels becomes a first-order challenge. The operational stress, along with the inefficient power dissipation and the unsustainable thermal thresholds increase the wear-induced failures. As a result, faster wear-out leads to earlier performance degradation with eventual device breakdown. Furthermore, the proliferation of asymmetric multicores is tightly coupled with an increasing susceptibility to variable wear-out rate within the components of processors. This paper investigates the reliability boundaries of asymmetric multicores, which span from embedded systems to high performance computing domains, by performing a continuous-operation reliability assessment. As our experimental analysis illustrates, the variation between the least and the most aged hardware resource equals to 2.6 years. Motivated by this finding, we show that an MTTF-aware, asymmetric configuration prolongs its lifetime by 21%.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"438 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116705485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-12DOI: 10.1109/DFT.2019.8875478
Viola Rieger, A. Zeh
We propose two parity-based concurrent error detection schemes for the Quarterround of the ChaCha stream cipher to protect from transient and permanent faults. They offer a trade-off between implementation overhead and error coverage. The second approach can detect any odd-weight error on the in-/output and intermediate signals of a Quarterround, while the first one requires less logic.
{"title":"Parity-Based Concurrent Error Detection Schemes for the ChaCha Stream Cipher","authors":"Viola Rieger, A. Zeh","doi":"10.1109/DFT.2019.8875478","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875478","url":null,"abstract":"We propose two parity-based concurrent error detection schemes for the Quarterround of the ChaCha stream cipher to protect from transient and permanent faults. They offer a trade-off between implementation overhead and error coverage. The second approach can detect any odd-weight error on the in-/output and intermediate signals of a Quarterround, while the first one requires less logic.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126525215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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