Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875328
Donald Kline, Stephen Longofono, R. Melhem, A. Jones
The ability to leverage commodity memory in harsh environments due to radiation has the potential advance computing capability for aerospace and nuclear applications, among others. In this work, we provide the first demonstration of the existence of a small number of weak cells to single event effects for DDR3 memory when exposed to radiation. Thus, a high proportion of single event faults are actually not entirely random and can be predicted with high accuracy. We also demonstrate a classification of single event effects into predictable single cell, unpredictable single cell, and correlated multi-cell persistent faults, the latter due to latch-up effects. We further show that through classification, we can partition faults, which allows the development of a holistic framework to provide enhanced protection of the DRAM memory. This framework leverages a fault map with bit sparing to protect against faults from weak cells in conjunction with Chipkill ECC to effectively correct chip-level and random errors. This protection provides a potential path to the use of commodity DRAM memory in high radiation environments with extremely low fault rates. Our results, based on data from a multi-day radiation beam experiment, indicate a reduction in uncorrectable bit error rate for rows containing a weak cell by a factor of $geq 10^{7}$ compared to Chipkill alone.
{"title":"Predicting Single Event Effects in DRAM","authors":"Donald Kline, Stephen Longofono, R. Melhem, A. Jones","doi":"10.1109/DFT.2019.8875328","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875328","url":null,"abstract":"The ability to leverage commodity memory in harsh environments due to radiation has the potential advance computing capability for aerospace and nuclear applications, among others. In this work, we provide the first demonstration of the existence of a small number of weak cells to single event effects for DDR3 memory when exposed to radiation. Thus, a high proportion of single event faults are actually not entirely random and can be predicted with high accuracy. We also demonstrate a classification of single event effects into predictable single cell, unpredictable single cell, and correlated multi-cell persistent faults, the latter due to latch-up effects. We further show that through classification, we can partition faults, which allows the development of a holistic framework to provide enhanced protection of the DRAM memory. This framework leverages a fault map with bit sparing to protect against faults from weak cells in conjunction with Chipkill ECC to effectively correct chip-level and random errors. This protection provides a potential path to the use of commodity DRAM memory in high radiation environments with extremely low fault rates. Our results, based on data from a multi-day radiation beam experiment, indicate a reduction in uncorrectable bit error rate for rows containing a weak cell by a factor of $geq 10^{7}$ compared to Chipkill alone.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132115641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875372
J. Pathrose, L. V. D. Logt, H. Kerkhoff
Embedded instruments have become ubiquitous in modern day System-on-Chips for test and monitoring purposes. IEEE 1687 or IJTAG addresses the standardization of access and operation of these embedded instruments. Recently, there has been a lot of interest in employing embedded instruments for dependability purposes. Many of these embedded instruments are required to monitor physical quantities which are analog in nature. A cost-effective architecture to integrate these analog instruments into the IEEE 1687 infrastructure is a bottleneck and has not yet been standardized. This paper presents a time and area efficient architecture to interface analog embedded instruments onto the IEEE 1687 network especially for dependability applications. The architecture mitigates the drawbacks associated with utilizing an analog test bus and enables periodic sampling with minimal hardware overhead. The simulations to illustrate the concept have been conducted with TSMC 40nm CMOS technology.
{"title":"Analog Test Interface for IEEE 1687 Employing Split SAR Architecture to Support Embedded Instrument Dependability Applications","authors":"J. Pathrose, L. V. D. Logt, H. Kerkhoff","doi":"10.1109/DFT.2019.8875372","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875372","url":null,"abstract":"Embedded instruments have become ubiquitous in modern day System-on-Chips for test and monitoring purposes. IEEE 1687 or IJTAG addresses the standardization of access and operation of these embedded instruments. Recently, there has been a lot of interest in employing embedded instruments for dependability purposes. Many of these embedded instruments are required to monitor physical quantities which are analog in nature. A cost-effective architecture to integrate these analog instruments into the IEEE 1687 infrastructure is a bottleneck and has not yet been standardized. This paper presents a time and area efficient architecture to interface analog embedded instruments onto the IEEE 1687 network especially for dependability applications. The architecture mitigates the drawbacks associated with utilizing an analog test bus and enables periodic sampling with minimal hardware overhead. The simulations to illustrate the concept have been conducted with TSMC 40nm CMOS technology.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134604390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, it is indispensable to test in transition fault model due to timing defects increase along with complication and high speed of VLSI. However, the transition fault coverage tends to be lower than the stuck-at fault coverage due to untestable faults caused by the circuit structure. Low transition fault coverage may not be able to detect potential timing defects. Therefore, it is important to design-for-testability (DFT) to improve transition fault coverage. In this paper, we show that transition fault coverages depend on state assignment to a controller in RTL netlists. We propose a QDT value which is an evaluation index on transition fault coverage for state assignment. Experimental results show that state assignment with high evaluation index has high transition fault coverages.
{"title":"A State Assignment Method to Improve Transition Fault Coverage for Controllers","authors":"Masayoshi Yoshimura, Yukihiko Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa","doi":"10.1109/DFT.2019.8875322","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875322","url":null,"abstract":"Recently, it is indispensable to test in transition fault model due to timing defects increase along with complication and high speed of VLSI. However, the transition fault coverage tends to be lower than the stuck-at fault coverage due to untestable faults caused by the circuit structure. Low transition fault coverage may not be able to detect potential timing defects. Therefore, it is important to design-for-testability (DFT) to improve transition fault coverage. In this paper, we show that transition fault coverages depend on state assignment to a controller in RTL netlists. We propose a QDT value which is an evaluation index on transition fault coverage for state assignment. Experimental results show that state assignment with high evaluation index has high transition fault coverages.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124640427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875314
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, M. Kumm, P. Zipf, K. Vissers
Neural Networks are currently one of the most widely deployed machine learning algorithms. In particular, Convolutional Neural Networks (CNNs), are gaining popularity and are evaluated for deployment in safety critical applications such as self driving vehicles. Modern CNNs feature enormous memory bandwidth and high computational needs, challenging existing hardware platforms to meet throughput, latency and power requirements. Functional safety and error tolerance need to be considered as additional requirement in safety critical systems. In general, fault tolerant operation can be achieved by adding redundancy to the system, which is further exacerbating the computational demands. Furthermore, the question arises whether pruning and quantization methods for performance scaling turn out to be counterproductive with regards to fail safety requirements. In this work we present a methodology to evaluate the impact of permanent faults affecting Quantized Neural Networks (QNNs) and how to effectively decrease their effects in hardware accelerators. We use FPGA-based hardware accelerated error injection, in order to enable the fast evaluation. A detailed analysis is presented showing that QNNs containing convolutional layers are by far not as robust to faults as commonly believed and can lead to accuracy drops of up to 10%. To circumvent that, we propose two different methods to increase their robustness: 1) selective channel replication which adds significantly less redundancy than used by the common triple modular redundancy and 2) a fault-aware scheduling of processing elements for folded implementations.
{"title":"Efficient Error-Tolerant Quantized Neural Network Accelerators","authors":"Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, M. Kumm, P. Zipf, K. Vissers","doi":"10.1109/DFT.2019.8875314","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875314","url":null,"abstract":"Neural Networks are currently one of the most widely deployed machine learning algorithms. In particular, Convolutional Neural Networks (CNNs), are gaining popularity and are evaluated for deployment in safety critical applications such as self driving vehicles. Modern CNNs feature enormous memory bandwidth and high computational needs, challenging existing hardware platforms to meet throughput, latency and power requirements. Functional safety and error tolerance need to be considered as additional requirement in safety critical systems. In general, fault tolerant operation can be achieved by adding redundancy to the system, which is further exacerbating the computational demands. Furthermore, the question arises whether pruning and quantization methods for performance scaling turn out to be counterproductive with regards to fail safety requirements. In this work we present a methodology to evaluate the impact of permanent faults affecting Quantized Neural Networks (QNNs) and how to effectively decrease their effects in hardware accelerators. We use FPGA-based hardware accelerated error injection, in order to enable the fast evaluation. A detailed analysis is presented showing that QNNs containing convolutional layers are by far not as robust to faults as commonly believed and can lead to accuracy drops of up to 10%. To circumvent that, we propose two different methods to increase their robustness: 1) selective channel replication which adds significantly less redundancy than used by the common triple modular redundancy and 2) a fault-aware scheduling of processing elements for folded implementations.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875417
C. Fuchs, Pai H. Chou, X. Wen, N. Murillo, G. Furano, S. Holst, A. Tavoularis, Shyue-Kung Lu, A. Plaat, K. Marinis
We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 $W$ of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.
{"title":"A Fault-Tolerant MPSoC For CubeSats","authors":"C. Fuchs, Pai H. Chou, X. Wen, N. Murillo, G. Furano, S. Holst, A. Tavoularis, Shyue-Kung Lu, A. Plaat, K. Marinis","doi":"10.1109/DFT.2019.8875417","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875417","url":null,"abstract":"We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 $W$ of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125160081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875316
Zhen Gao, Jinhua Zhu, Lina Yan, Tong Yan, P. Reviriego
Decimation is widely used in digital communication systems to reduce the oversampling rate of the base band signal. The structure of Poly Phase Filters (PPFs) provides an efficient implementation of the decimator. This paper studies the effects of Single Event Upsets (SEUs) on PPFs based decimators implemented on SRAM-FPGAs. Fault injection experiments are performed to evaluate the reliability of the decimator to SEUs on filter coefficients and on the configuration memory. For the first part, experiment results show that only SEUs on the two most significant bits would cause non negligible SNR loss in the output. For SEUs on the essential bits in the configuration memory, about 20% of them would affect the results, among which 70% of the SEUs would cause negligible SNR loss. The percentage of SEUs that cause a SNR loss larger than 5dB are 7%, 13% and 16% for decimation rates of 16, 8 and 4, respectively. This can be explained as the decimator is composed of a number of parallel filters that is equal to the decimation rate, and each filter contributes a fraction of the final output. Therefore, a SEU on one filter would not cause large degradation to the decimated signal, and the larger the decimation rate is, the smaller the degradation of decimated signal introduced by the SEU.
{"title":"Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs","authors":"Zhen Gao, Jinhua Zhu, Lina Yan, Tong Yan, P. Reviriego","doi":"10.1109/DFT.2019.8875316","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875316","url":null,"abstract":"Decimation is widely used in digital communication systems to reduce the oversampling rate of the base band signal. The structure of Poly Phase Filters (PPFs) provides an efficient implementation of the decimator. This paper studies the effects of Single Event Upsets (SEUs) on PPFs based decimators implemented on SRAM-FPGAs. Fault injection experiments are performed to evaluate the reliability of the decimator to SEUs on filter coefficients and on the configuration memory. For the first part, experiment results show that only SEUs on the two most significant bits would cause non negligible SNR loss in the output. For SEUs on the essential bits in the configuration memory, about 20% of them would affect the results, among which 70% of the SEUs would cause negligible SNR loss. The percentage of SEUs that cause a SNR loss larger than 5dB are 7%, 13% and 16% for decimation rates of 16, 8 and 4, respectively. This can be explained as the decimator is composed of a number of parallel filters that is equal to the decimation rate, and each filter contributes a fraction of the final output. Therefore, a SEU on one filter would not cause large degradation to the decimated signal, and the larger the decimation rate is, the smaller the degradation of decimated signal introduced by the SEU.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127079873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875320
Ana Lasheras, R. Canal, Eva Rodríguez, Luca Cassano
Hardware accelerators for cryptographic algorithms are ubiquitously deployed in nowadays consumer and industrial products. Unfortunately, the HW implementations of such algorithms often suffer from vulnerabilities that expose systems to a number of attacks, among which differential fault analysis (DFA). It is therefore crucial to protect cryptographic circuits against such attacks in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting circuits implementing the RSA algorithm against DFA. The proposed solution borrows residue checking from the traditional fault tolerance and applies it to RSA circuits in order to first detect the occurrence a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the proposed solution detects the 100% of the possible fault attacks while leading to a 2.85% area overhead, a 16.67% power consumption increase and with no operating frequency decrease.
{"title":"Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking","authors":"Ana Lasheras, R. Canal, Eva Rodríguez, Luca Cassano","doi":"10.1109/DFT.2019.8875320","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875320","url":null,"abstract":"Hardware accelerators for cryptographic algorithms are ubiquitously deployed in nowadays consumer and industrial products. Unfortunately, the HW implementations of such algorithms often suffer from vulnerabilities that expose systems to a number of attacks, among which differential fault analysis (DFA). It is therefore crucial to protect cryptographic circuits against such attacks in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting circuits implementing the RSA algorithm against DFA. The proposed solution borrows residue checking from the traditional fault tolerance and applies it to RSA circuits in order to first detect the occurrence a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the proposed solution detects the 100% of the possible fault attacks while leading to a 2.85% area overhead, a 16.67% power consumption increase and with no operating frequency decrease.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"405 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133153389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875490
F. Merchant, Anandraj Devarajan, A. Basu, David Ashen, Brandon Yelton, Prashant D. Joshi
As process technology dimensions shrink, manufacturing defect density is increasing, adversely impacting product yield. Products have typically built redundancy and repair features in SRAM. Register File arrays (RFs) can also benefit from redundancy and repair. There are various types of repair techniques used in SRAMs today which can also be employed on RFs. However all known techniques (column, row, 1-bit, multi-bit) incur a performance loss of at least two gate delays due to the addition of logic either on the memory address path or on the read output path. This paper describes a row repair scheme that incurs virtually no performance penalty. In simulations conducted in recent process nodes, we noted a performance impact of less than half a gate delay
{"title":"High Performance Memory Repair","authors":"F. Merchant, Anandraj Devarajan, A. Basu, David Ashen, Brandon Yelton, Prashant D. Joshi","doi":"10.1109/DFT.2019.8875490","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875490","url":null,"abstract":"As process technology dimensions shrink, manufacturing defect density is increasing, adversely impacting product yield. Products have typically built redundancy and repair features in SRAM. Register File arrays (RFs) can also benefit from redundancy and repair. There are various types of repair techniques used in SRAMs today which can also be employed on RFs. However all known techniques (column, row, 1-bit, multi-bit) incur a performance loss of at least two gate delays due to the addition of logic either on the memory address path or on the read output path. This paper describes a row repair scheme that incurs virtually no performance penalty. In simulations conducted in recent process nodes, we noted a performance impact of less than half a gate delay","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875272
Dipojjwal Ray, Siddharth Singh, Sk Subidh Ali, S. Biswas
The chiller system in a building accounts for the main part of the building's total energy consumption, so it is critical to optimize the operation of chiller system for the purpose of saving energy. A chiller system generally consists of evaporation side and condensing side. The condensing side includes chillers, cooling water pumps and cooling towers, which form a subsystem of cooling water. It is a typical optimization problem to minimize the total energy consumption of cooling water subsystem. This paper discusses how to solve the optimization problem of the cooling water subsystem and proposes a simple optimal control rule for field operation based on the optimization results.
{"title":"Co-relation Scan Attack Analysis (COSAA) on AES: A Comprehensive Approach","authors":"Dipojjwal Ray, Siddharth Singh, Sk Subidh Ali, S. Biswas","doi":"10.1109/DFT.2019.8875272","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875272","url":null,"abstract":"The chiller system in a building accounts for the main part of the building's total energy consumption, so it is critical to optimize the operation of chiller system for the purpose of saving energy. A chiller system generally consists of evaporation side and condensing side. The condensing side includes chillers, cooling water pumps and cooling towers, which form a subsystem of cooling water. It is a typical optimization problem to minimize the total energy consumption of cooling water subsystem. This paper discusses how to solve the optimization problem of the cooling water subsystem and proposes a simple optimal control rule for field operation based on the optimization results.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129301218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875362
B. Du, S. Azimi, C. D. Sio, Ludovica Bozzoli, L. Sterpone
In recent years, topics around machine learning and artificial intelligence (AI) have (re-)gained a lot of interest due to high demand in industrial automation applications in various areas such as medical, automotive and space and the increasing computational power offered by technology advancements. One common task for these applications is object recognition/classification whose input is usually an image taken from camera and output is whether an object is present and the class of the object. In industrial pipeline, this task could be used to identify possible defects in products; in automotive application, such task could be deployed to detect pedestrians for Advanced Driver-Assistance Systems (ADAS). When the task is safety-critical as in automotive application, the reliability of the task implementation is crucial and has to be evaluated before final deployment. On the other hand, Field Programmable Gate Array (FPGA) devices are gaining increasing attention in the hardware acceleration part for machine learning applications due to their high flexibility and increasing computational power. When the SRAM-based FPGA is considered, Single Event Upset (SEU) in configuration memory induced by radiation particle is one of the major concerns even at sea level. In this paper, we present the fault injection results on a Convolutional Neural Network (CNN) implementation on Xilinx SRAM-based FPGA which demonstrate that though there exists built-in redundancy in CNN implementation one SEU in configuration memory can still impact the task execution results while the possibility of Single Event Multiple Upsets (SEMU) must also be taken into consideration.
{"title":"On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA","authors":"B. Du, S. Azimi, C. D. Sio, Ludovica Bozzoli, L. Sterpone","doi":"10.1109/DFT.2019.8875362","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875362","url":null,"abstract":"In recent years, topics around machine learning and artificial intelligence (AI) have (re-)gained a lot of interest due to high demand in industrial automation applications in various areas such as medical, automotive and space and the increasing computational power offered by technology advancements. One common task for these applications is object recognition/classification whose input is usually an image taken from camera and output is whether an object is present and the class of the object. In industrial pipeline, this task could be used to identify possible defects in products; in automotive application, such task could be deployed to detect pedestrians for Advanced Driver-Assistance Systems (ADAS). When the task is safety-critical as in automotive application, the reliability of the task implementation is crucial and has to be evaluated before final deployment. On the other hand, Field Programmable Gate Array (FPGA) devices are gaining increasing attention in the hardware acceleration part for machine learning applications due to their high flexibility and increasing computational power. When the SRAM-based FPGA is considered, Single Event Upset (SEU) in configuration memory induced by radiation particle is one of the major concerns even at sea level. In this paper, we present the fault injection results on a Convolutional Neural Network (CNN) implementation on Xilinx SRAM-based FPGA which demonstrate that though there exists built-in redundancy in CNN implementation one SEU in configuration memory can still impact the task execution results while the possibility of Single Event Multiple Upsets (SEMU) must also be taken into consideration.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129880402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：