Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875433
Markus Ulbricht, R. Syed, M. Krstic
The ambitious goals for implementing autonomous systems in nearly all industry sectors create big challenges for the designers of such devices. Especially sensors, key factors for enabling autonomy, must fulfil greatest demands. The challenge is to build highly reliable sensory systems, preferably based on commercial off-the-shelf components, with short design cycles, high robustness against faults and minimal power consumption. In this paper, we present an approach for designing such a sensory system that targets automated driving. Designed as a configurable software-implemented TMR system, we based it on three Tensilica Fusion G3 cores with negligible additional hardware to each core. We are able to show that this system can be controlled to support low power, fail safe, fail operational and distributed execution of different tasks, all while keeping the strict timing and safety constraints that are crucial in the automotive area.
{"title":"Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor Processing","authors":"Markus Ulbricht, R. Syed, M. Krstic","doi":"10.1109/DFT.2019.8875433","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875433","url":null,"abstract":"The ambitious goals for implementing autonomous systems in nearly all industry sectors create big challenges for the designers of such devices. Especially sensors, key factors for enabling autonomy, must fulfil greatest demands. The challenge is to build highly reliable sensory systems, preferably based on commercial off-the-shelf components, with short design cycles, high robustness against faults and minimal power consumption. In this paper, we present an approach for designing such a sensory system that targets automated driving. Designed as a configurable software-implemented TMR system, we based it on three Tensilica Fusion G3 cores with negligible additional hardware to each core. We are able to show that this system can be controlled to support low power, fail safe, fail operational and distributed execution of different tasks, all while keeping the strict timing and safety constraints that are crucial in the automotive area.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122858172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875281
Antonio J. Sánchez, Y. Barrios, Lucana Santos, R. Sarmiento
This work analyses the results of applying Triple Modular Redundancy (TMR) to the SHyLoC CCSDS-121 IP, a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 121.0-B-2 lossless compression standard, a universal compressor specifically thought for space applications. The results obtained in a radiation experiment performed at the North Area new facilities at CERN are presented. The objective is to evaluate the robustness applying TMR to the design, by comparing to the unhardened implementation of the SHyLoC CCSDS-121 IP, when it is working under Ultra High Energy radiation. Both TMR and unhardened implementations of the SHyLoC CCSDS-121 IP were implemented in a Xilinx Zynq XC7Z020 System-on-Chip and radiated with Pb ions. Compression results were compared against a golden reference, obtaining a Mean Time To Failure (MTTF) a 40% higher for the TMR design than for the unhardened one.
{"title":"Evaluation of TMR effectiveness for soft error mitigation in SHyLoC compression IP core implemented on Zynq SoC under heavy ion radiation","authors":"Antonio J. Sánchez, Y. Barrios, Lucana Santos, R. Sarmiento","doi":"10.1109/DFT.2019.8875281","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875281","url":null,"abstract":"This work analyses the results of applying Triple Modular Redundancy (TMR) to the SHyLoC CCSDS-121 IP, a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 121.0-B-2 lossless compression standard, a universal compressor specifically thought for space applications. The results obtained in a radiation experiment performed at the North Area new facilities at CERN are presented. The objective is to evaluate the robustness applying TMR to the design, by comparing to the unhardened implementation of the SHyLoC CCSDS-121 IP, when it is working under Ultra High Energy radiation. Both TMR and unhardened implementations of the SHyLoC CCSDS-121 IP were implemented in a Xilinx Zynq XC7Z020 System-on-Chip and radiated with Pb ions. Compression results were compared against a golden reference, obtaining a Mean Time To Failure (MTTF) a 40% higher for the TMR design than for the unhardened one.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133649289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875355
Satyadev Ahlawat, Jaynarayan T. Tudu, M. Gaur, M. Fujita, Virendra Singh
The strategies for breaking a cipher has been shifting towards side channel attacks which exploit the run-time physical attributes of cryptographic chips. Among the many such attacks, the scan-based attack has become a convenient approach for attackers to extract the secret information. As reported in academic research, the scan-based side-channel attacks have been successfully mounted on Advanced Encryption Standard (AES) crypto chips. On the other hand, the scan design-for-test (DfT) has become a mandatory practice for almost all the modern designs for the test, debug, and diagnosis. Therefore, the development of a secure scan test technique is very much needed, which can effectively countermeasure the scan attacks on cryptographic chips. In this paper, we propose a new countermeasure against scan attacks on AES crypto chips. The proposed countermeasure is based on the principle of test response encryption. The scan chain content can be scanned out only in encrypted form and hence cannot be analysed by an unauthorised user. The proposed countermeasure thwarts all the known scan attacks on scan design without compromising on its test capabilities. Moreover, the extra circuitry used for test response encryption is used during mission mode to achieve 2X throughput compared with the conventional iterative AES architecture.
{"title":"Preventing Scan Attack through Test Response Encryption","authors":"Satyadev Ahlawat, Jaynarayan T. Tudu, M. Gaur, M. Fujita, Virendra Singh","doi":"10.1109/DFT.2019.8875355","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875355","url":null,"abstract":"The strategies for breaking a cipher has been shifting towards side channel attacks which exploit the run-time physical attributes of cryptographic chips. Among the many such attacks, the scan-based attack has become a convenient approach for attackers to extract the secret information. As reported in academic research, the scan-based side-channel attacks have been successfully mounted on Advanced Encryption Standard (AES) crypto chips. On the other hand, the scan design-for-test (DfT) has become a mandatory practice for almost all the modern designs for the test, debug, and diagnosis. Therefore, the development of a secure scan test technique is very much needed, which can effectively countermeasure the scan attacks on cryptographic chips. In this paper, we propose a new countermeasure against scan attacks on AES crypto chips. The proposed countermeasure is based on the principle of test response encryption. The scan chain content can be scanned out only in encrypted form and hence cannot be analysed by an unauthorised user. The proposed countermeasure thwarts all the known scan attacks on scan design without compromising on its test capabilities. Moreover, the extra circuitry used for test response encryption is used during mission mode to achieve 2X throughput compared with the conventional iterative AES architecture.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116525208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875345
A. Ruospo, R. Cantoro, E. Sánchez, Pasquale Davide Schiavone, Angelo Garofalo, L. Benini
In the last decade, a growing number of electronic devices have been designed to be deployed in safety-critical autonomous systems. Many application domains, such as autonomous vehicles, robots, nano-drones, are exploring artificial intelligence solutions to handle the increasing computation requirements. Besides, due to their safety-critical application scenarios, they are demanding for even more reliable and advanced systems. These requirements clearly entail a growing complexity in modern processors and System-on-a-Chip design, leading to new efforts in verification and testing phases. These new devices must be also compliant with emerging functional safety standards that regulate their usage during the entire lifetime. The main intent of this work is to improve the reliability of autonomous systems, providing a strategy to link the verification methodology with the testing one. Starting from an almost exhaustive verification set, it is possible to derive a different set of patterns intended for on-line testing. This achievement is gained by taking into account the constraints due to the final system application and the common requirements of the embedded devices used in autonomous systems. Experimental results are provided on an open-source RISC-V processor assembled on an autonomous nano-drone.
{"title":"On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification","authors":"A. Ruospo, R. Cantoro, E. Sánchez, Pasquale Davide Schiavone, Angelo Garofalo, L. Benini","doi":"10.1109/DFT.2019.8875345","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875345","url":null,"abstract":"In the last decade, a growing number of electronic devices have been designed to be deployed in safety-critical autonomous systems. Many application domains, such as autonomous vehicles, robots, nano-drones, are exploring artificial intelligence solutions to handle the increasing computation requirements. Besides, due to their safety-critical application scenarios, they are demanding for even more reliable and advanced systems. These requirements clearly entail a growing complexity in modern processors and System-on-a-Chip design, leading to new efforts in verification and testing phases. These new devices must be also compliant with emerging functional safety standards that regulate their usage during the entire lifetime. The main intent of this work is to improve the reliability of autonomous systems, providing a strategy to link the verification methodology with the testing one. Starting from an almost exhaustive verification set, it is possible to derive a different set of patterns intended for on-line testing. This achievement is gained by taking into account the constraints due to the final system application and the common requirements of the embedded devices used in autonomous systems. Experimental results are provided on an open-source RISC-V processor assembled on an autonomous nano-drone.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115774317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875489
A. Simevski, Patryk Skoncej, C. Calligaro, M. Krstic
Space applications constantly require integration of more processing capabilities and greater memory capacity, at reduced weight and power consumption. The IHP 130 nm technology is a commercially-qualified and radiation-assessed technology which is sufficiently aggressive for the conservative approach in the space area. In this process node we realize a rad-hard 16Mbit Multi-Chip Module (MCM) SRAM with improved characteristics in comparison to competitor SRAMs. Moreover, the real novelty is the scalable master-slave architecture of the System-in-Package (SiP) with Error Detection and Correction (EDAC), and scrubbing mechanisms which are now at the SiP level. Furthermore, the width of the word size is configurable. On the other side, we conduct a large number of fault injection campaigns in order to early investigate the SiP reliability. High error resilience and significantly reduced number of interrupt requests for error recovery are observed.
{"title":"Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications","authors":"A. Simevski, Patryk Skoncej, C. Calligaro, M. Krstic","doi":"10.1109/DFT.2019.8875489","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875489","url":null,"abstract":"Space applications constantly require integration of more processing capabilities and greater memory capacity, at reduced weight and power consumption. The IHP 130 nm technology is a commercially-qualified and radiation-assessed technology which is sufficiently aggressive for the conservative approach in the space area. In this process node we realize a rad-hard 16Mbit Multi-Chip Module (MCM) SRAM with improved characteristics in comparison to competitor SRAMs. Moreover, the real novelty is the scalable master-slave architecture of the System-in-Package (SiP) with Error Detection and Correction (EDAC), and scrubbing mechanisms which are now at the SiP level. Furthermore, the width of the word size is configurable. On the other side, we conduct a large number of fault injection campaigns in order to early investigate the SiP reliability. High error resilience and significantly reduced number of interrupt requests for error recovery are observed.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875457
A. Choudhury, B. Sikdar
Voltage scaling to reduce power consumption for ensuring longer battery life expedites SRAM cell failures due to process variations. Cache, holding significant chip area, encounters these cell failures exponentially with voltage reduction. Several voltage reduction techniques have been proposed by tolerating faults at the cost of sacrificial cache portions affecting effective cache capacity. On this outset, this work attempts to minimize power below threshold by handling faults without affecting effective cache capacity. Words under priority blocks addressed on faulty cache portions are remapped in non-functional blocks to avoid cache pollution. Blocks are prioritized considering their coherence states and reusability. Non-reusable clean copies are invalidated to ensure adequate space for remapping and maintaining effective cache capacity. This work achieves minimum Vdd 325 mV with 7.77% area overhead with 6.7% leakage power and 0.5% dynamic power overhead in 90nm processor.
{"title":"CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore","authors":"A. Choudhury, B. Sikdar","doi":"10.1109/DFT.2019.8875457","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875457","url":null,"abstract":"Voltage scaling to reduce power consumption for ensuring longer battery life expedites SRAM cell failures due to process variations. Cache, holding significant chip area, encounters these cell failures exponentially with voltage reduction. Several voltage reduction techniques have been proposed by tolerating faults at the cost of sacrificial cache portions affecting effective cache capacity. On this outset, this work attempts to minimize power below threshold by handling faults without affecting effective cache capacity. Words under priority blocks addressed on faulty cache portions are remapped in non-functional blocks to avoid cache pollution. Blocks are prioritized considering their coherence states and reusability. Non-reusable clean copies are invalidated to ensure adequate space for remapping and maintaining effective cache capacity. This work achieves minimum Vdd 325 mV with 7.77% area overhead with 6.7% leakage power and 0.5% dynamic power overhead in 90nm processor.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123619727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875396
Jiaqiang Li, P. Reviriego, Liyi Xiao, A. Klockmann
The increasing importance of Multiple Cell Upsets (MCU) in memories has led to the development of error correction codes that can correct multiple bit errors on nearby bits. In particular, 3-bit burst error correction codes have been recently proposed for memories with data words of up to 64 bits. In some cases, like caches, widths can be much larger than 64 bits and therefore, to protect them 3-bit burst codes with larger block sizes are needed. Most of the 3-bit burst codes presented so far are generated with a computer search program. This approach does not scale well to large word sizes. Recently an algorithmic construction has also been proposed for 3-bit burst codes that supports large word sizes. A decoding algorithm was also proposed but no implementation was provided. This paper studies the implementation of 3-bit burst error correction for large word sizes using the recently proposed algorithmic code construction. To that end, the decoding has been implemented using the algorithm proposed for those codes and a traditional syndrome decoding and both have been compared to a SEC-DED code. The results show that syndrome decoding is more efficient than the ad-hoc algorithm. Compared to a SEC-DED decoder, implementing 3-bit burst correction decoder requires approximately an increase of 2x in area, 3x in power and 20–30% in delay for word sizes of 128, 256 and 512 bits. Therefore, the impact is significant even when using the most efficient decoder implementation.
{"title":"Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction","authors":"Jiaqiang Li, P. Reviriego, Liyi Xiao, A. Klockmann","doi":"10.1109/DFT.2019.8875396","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875396","url":null,"abstract":"The increasing importance of Multiple Cell Upsets (MCU) in memories has led to the development of error correction codes that can correct multiple bit errors on nearby bits. In particular, 3-bit burst error correction codes have been recently proposed for memories with data words of up to 64 bits. In some cases, like caches, widths can be much larger than 64 bits and therefore, to protect them 3-bit burst codes with larger block sizes are needed. Most of the 3-bit burst codes presented so far are generated with a computer search program. This approach does not scale well to large word sizes. Recently an algorithmic construction has also been proposed for 3-bit burst codes that supports large word sizes. A decoding algorithm was also proposed but no implementation was provided. This paper studies the implementation of 3-bit burst error correction for large word sizes using the recently proposed algorithmic code construction. To that end, the decoding has been implemented using the algorithm proposed for those codes and a traditional syndrome decoding and both have been compared to a SEC-DED code. The results show that syndrome decoding is more efficient than the ad-hoc algorithm. Compared to a SEC-DED decoder, implementing 3-bit burst correction decoder requires approximately an increase of 2x in area, 3x in power and 20–30% in delay for word sizes of 128, 256 and 512 bits. Therefore, the impact is significant even when using the most efficient decoder implementation.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127268484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875487
Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.
{"title":"Testing of In-Memory-Computing 8T SRAMs","authors":"Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun","doi":"10.1109/DFT.2019.8875487","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875487","url":null,"abstract":"To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132113283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875467
Luca Gnoli, Giuseppe Carnicelli, A. Parisi, Luca Urbinati, Burim Kabashi, Fabio Michieletti, Sebastian Ignacio Peradotto Ibarra, M. Vacca, M. Graziano, J. Mathew, M. Ottavi
Solar energy is one of the most important sources of renewable energy. Photovoltaic arrays are a widely employed systems used to harvest solar energy. In such systems, the presence of faulty cells negatively affect the energy production of the entire array. The design of fault tolerant solar arrays is therefore attracting a growing interest. In this work, we propose a hardware implementation of a fault-recovery algorithm for solar cell arrays. The proposed system detects cells with degraded performance using a memristor as sensing device. With the aim of improving energy production efficiency, the connections among solar cells are reconfigured according to the array health status. The designed system automatically activates spare cells in the segments of the array to eventually increase energy production. The proposed solution can be adapted to arrays of any size and be applied to different types of solar cells. We show through simulations that the solution here proposed significantly increases the energy production in presence of faults.
{"title":"Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing","authors":"Luca Gnoli, Giuseppe Carnicelli, A. Parisi, Luca Urbinati, Burim Kabashi, Fabio Michieletti, Sebastian Ignacio Peradotto Ibarra, M. Vacca, M. Graziano, J. Mathew, M. Ottavi","doi":"10.1109/DFT.2019.8875467","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875467","url":null,"abstract":"Solar energy is one of the most important sources of renewable energy. Photovoltaic arrays are a widely employed systems used to harvest solar energy. In such systems, the presence of faulty cells negatively affect the energy production of the entire array. The design of fault tolerant solar arrays is therefore attracting a growing interest. In this work, we propose a hardware implementation of a fault-recovery algorithm for solar cell arrays. The proposed system detects cells with degraded performance using a memristor as sensing device. With the aim of improving energy production efficiency, the connections among solar cells are reconfigured according to the array health status. The designed system automatically activates spare cells in the segments of the array to eventually increase energy production. The proposed solution can be adapted to arrays of any size and be applied to different types of solar cells. We show through simulations that the solution here proposed significantly increases the energy production in presence of faults.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/DFT.2019.8875283
Shanshan Liu, P. Reviriego, K. Namba, S. Pontarelli, Liyi Xiao, F. Lombardi
Non-volatile emerging Multilevel Cell (MLC) memories (such as magneto electric, magnetic resistive, memristor-based and phase change memories) are attractive to increase density. A key advantage of these memories is that they can store several bits per cell by using different levels. This however reduces the margins against noise and other effects and can lead to larger error rates. Errors in MLC memories are usually limited to magnitude-2 levels, and thus corrupt one or two bits per cell when using a Gray mapping from levels to bits. This enables the use of codes that can correct those error patterns in a memory cell instead of codes that correct all possible patterns in the cell, thus reducing complexity and cost. In this paper, the case of a 64 data bit memory built using memory cells that can store four bits and suffer up to double bit errors per cell is considered. Several (72, 64) Spotty codes that can correct double bit errors in 4-bit cells are designed and evaluated. The new codes require fewer parity bits than existing Spotty codes or symbol-based codes such as Hong-Patel codes. Therefore, they reduce the size of the memory while having encoding and decoding complexity similar to existing alternative codes.
{"title":"Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells","authors":"Shanshan Liu, P. Reviriego, K. Namba, S. Pontarelli, Liyi Xiao, F. Lombardi","doi":"10.1109/DFT.2019.8875283","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875283","url":null,"abstract":"Non-volatile emerging Multilevel Cell (MLC) memories (such as magneto electric, magnetic resistive, memristor-based and phase change memories) are attractive to increase density. A key advantage of these memories is that they can store several bits per cell by using different levels. This however reduces the margins against noise and other effects and can lead to larger error rates. Errors in MLC memories are usually limited to magnitude-2 levels, and thus corrupt one or two bits per cell when using a Gray mapping from levels to bits. This enables the use of codes that can correct those error patterns in a memory cell instead of codes that correct all possible patterns in the cell, thus reducing complexity and cost. In this paper, the case of a 64 data bit memory built using memory cells that can store four bits and suffer up to double bit errors per cell is considered. Several (72, 64) Spotty codes that can correct double bit errors in 4-bit cells are designed and evaluated. The new codes require fewer parity bits than existing Spotty codes or symbol-based codes such as Hong-Patel codes. Therefore, they reduce the size of the memory while having encoding and decoding complexity similar to existing alternative codes.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127793837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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