D. Morales, A. García, A. Palma, A. Martínez-Olmos
This work focuses on the application of both field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs) as an unique system for implementing IEEE 1451.4 sensor interfaces. The inherent reconfigurability of these two hardware platforms allows increasing the versatility of the overall system, leading to a variety of sensor connectivity and remote measurement and control options.
{"title":"Merging FPGA and FPAA Reconfiguration Capabilities for IEEE 1451.4 Compliant Smart Sensor Applications","authors":"D. Morales, A. García, A. Palma, A. Martínez-Olmos","doi":"10.1109/SPL.2007.371753","DOIUrl":"https://doi.org/10.1109/SPL.2007.371753","url":null,"abstract":"This work focuses on the application of both field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs) as an unique system for implementing IEEE 1451.4 sensor interfaces. The inherent reconfigurability of these two hardware platforms allows increasing the versatility of the overall system, leading to a variety of sensor connectivity and remote measurement and control options.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122630025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M.A. Nuho-Maganda, M. Arias-Estrada, C. Torres-Huitzil
Artificial neural networks (ANNs) are processing models widely explored due to their computational capabilities for solving problems. Recently, spiking neural networks (SNNs) are being studied as more biological plausible models that resemble closer to biological neurons than classical ANNs. In spite of SNNs offer richer dynamics, their full utilization in practical systems is still limited due to high computational demand on microprocessors-based software implementations. In order to overcome this drawback, an efficient scalable parallel hardware architecture for SNNs is proposed to map efficiently area demanding and dense interconnection requirements of neural processing. The SNNs models have the advantage of reducing the bandwidth needed for interchanging information among neurons, making them more suitable for hardware implementation, due to the communication scheme based on digital spikes. The hardware implementation is divided into two main phases: recall and learning. Timing, hardware resources and performance comparison are mainly shown for the recall phase in this paper.
{"title":"An Efficient Scalable Parallel Hardware Architecture for Multilayer Spiking Neural Networks","authors":"M.A. Nuho-Maganda, M. Arias-Estrada, C. Torres-Huitzil","doi":"10.1109/SPL.2007.371742","DOIUrl":"https://doi.org/10.1109/SPL.2007.371742","url":null,"abstract":"Artificial neural networks (ANNs) are processing models widely explored due to their computational capabilities for solving problems. Recently, spiking neural networks (SNNs) are being studied as more biological plausible models that resemble closer to biological neurons than classical ANNs. In spite of SNNs offer richer dynamics, their full utilization in practical systems is still limited due to high computational demand on microprocessors-based software implementations. In order to overcome this drawback, an efficient scalable parallel hardware architecture for SNNs is proposed to map efficiently area demanding and dense interconnection requirements of neural processing. The SNNs models have the advantage of reducing the bandwidth needed for interchanging information among neurons, making them more suitable for hardware implementation, due to the communication scheme based on digital spikes. The hardware implementation is divided into two main phases: recall and learning. Timing, hardware resources and performance comparison are mainly shown for the recall phase in this paper.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128169401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fingerprint is the most widely used and studied biometric technique because of its universality, distinctiveness, and decreasing cost of the sensing devices. Among the fingerprint identification techniques, minutiae-based algorithms are the most mature. However, these methods are computationally expensive, particularly for comparison with large databases. This work is devoted to study the performance gains that can be achieved with the use of FPGAs. To this purpose, two minutia-based fingerprint matching algorithms have been selected and implemented in a FPGA in order to compare the requirements and performance of software and hardware implementations. Experimental results demonstrate the feasibility of implementing fingerprint matching algorithms in current FPGA devices achieving speed-ups of one or two orders of magnitude. Customization of the proposed implementations can lead to several architectures optimized in size, price, speed or accuracy.
{"title":"FPGA-Based Acceleration of Fingerprint Minutiae Matching","authors":"A. Lindoso, L. Entrena, J. Izquierdo","doi":"10.1109/SPL.2007.371728","DOIUrl":"https://doi.org/10.1109/SPL.2007.371728","url":null,"abstract":"Fingerprint is the most widely used and studied biometric technique because of its universality, distinctiveness, and decreasing cost of the sensing devices. Among the fingerprint identification techniques, minutiae-based algorithms are the most mature. However, these methods are computationally expensive, particularly for comparison with large databases. This work is devoted to study the performance gains that can be achieved with the use of FPGAs. To this purpose, two minutia-based fingerprint matching algorithms have been selected and implemented in a FPGA in order to compare the requirements and performance of software and hardware implementations. Experimental results demonstrate the feasibility of implementing fingerprint matching algorithms in current FPGA devices achieving speed-ups of one or two orders of magnitude. Customization of the proposed implementations can lead to several architectures optimized in size, price, speed or accuracy.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130810759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Based on our previous work concerning DSP applications mapping onto ASTRA reconfigurable architecture, this paper describes the microarchitecture in more detail and introduces some significant improvements. The silicon area of the logic tile is reduced by 40%. The area figures of the benchmarks are only factor 10-25 worse than the ASIC implementation - a very competitive ratio for a reconfigurable architecture.
{"title":"A Novel Reconfigurable Architecture for Temporal and Spatial Application Mapping","authors":"A. Danilin, S. Sawitzki","doi":"10.1109/SPL.2007.371726","DOIUrl":"https://doi.org/10.1109/SPL.2007.371726","url":null,"abstract":"This paper introduces a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Based on our previous work concerning DSP applications mapping onto ASTRA reconfigurable architecture, this paper describes the microarchitecture in more detail and introduces some significant improvements. The silicon area of the logic tile is reduced by 40%. The area figures of the benchmarks are only factor 10-25 worse than the ASIC implementation - a very competitive ratio for a reconfigurable architecture.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127922582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Motion estimation constitutes a significant computational part of video compression standards such as MPEG4. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the full search block matching algorithm which is highly computing intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of access to image memory and router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every PE in the array includes a double ALU in order to search multiple macro-blocks in parallel. Results show that a peak performance in the order of 9 GOPS can be achieved.
{"title":"Compact FPGA-Based Systolic Array Architecture for Motion Estimation Using Full Search Block Matching","authors":"G. Saldaha, M. Arias-Estrada","doi":"10.1109/SPL.2007.371756","DOIUrl":"https://doi.org/10.1109/SPL.2007.371756","url":null,"abstract":"Motion estimation constitutes a significant computational part of video compression standards such as MPEG4. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the full search block matching algorithm which is highly computing intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of access to image memory and router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every PE in the array includes a double ALU in order to search multiple macro-blocks in parallel. Results show that a peak performance in the order of 9 GOPS can be achieved.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132213273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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