In this paper we present a hardware architecture for adaptive background modelling. Adaptive background models are used in a variety of computer vision applications, ranging from traffic monitoring to biometric identification. We report (a) a design for an adaptive background modelling algorithm; (b) implementation of the algorithm on an FPGA device; and (c) performance evaluation for our hardware architecture. One of our designs, running on a Xilinx XC2V1000 FPGA at 81 MHz, can process VGA quality 640times480 pixel frames at 132 frames per second using 291 slices and a single memory bank.
{"title":"Hardware Architectures for Adaptive Background Modelling","authors":"M. Juvonen, J. Coutinho, W. Luk","doi":"10.1109/SPL.2007.371739","DOIUrl":"https://doi.org/10.1109/SPL.2007.371739","url":null,"abstract":"In this paper we present a hardware architecture for adaptive background modelling. Adaptive background models are used in a variety of computer vision applications, ranging from traffic monitoring to biometric identification. We report (a) a design for an adaptive background modelling algorithm; (b) implementation of the algorithm on an FPGA device; and (c) performance evaluation for our hardware architecture. One of our designs, running on a Xilinx XC2V1000 FPGA at 81 MHz, can process VGA quality 640times480 pixel frames at 132 frames per second using 291 slices and a single memory bank.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129154057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Benítez, G. Bellanco, C. Amuchastegui, G. Álvarez, I. Laniella, H. Cepeda, N. Ayuso, A. Guerendiain
This article presents a remote automatic meter reading (AMR) system as a result of the Mirakonta project, in which are involved several university investigation groups and a private company. The AMR system is composed by reader devices and a group of elements that allow a wireless connection to a central server. The system is based on taking a picture of the fluid meter digit display, preprocessing and transmitting it to a remote element using a radio frequency ad-hoc protocol. The reader device is implemented on a FPGA based system and the firmware can be updated remotely (remote reconfiguration). In addition, the different parameters of the reader can be configured remotely. To meet the low power requirements a sleep and wake-up technique is applied. All the requirements of the system have been covered, offering a hardware-software product that covers most needs of the end users.
{"title":"Low Power AMR System Based on FPGA","authors":"N. Benítez, G. Bellanco, C. Amuchastegui, G. Álvarez, I. Laniella, H. Cepeda, N. Ayuso, A. Guerendiain","doi":"10.1109/SPL.2007.371744","DOIUrl":"https://doi.org/10.1109/SPL.2007.371744","url":null,"abstract":"This article presents a remote automatic meter reading (AMR) system as a result of the Mirakonta project, in which are involved several university investigation groups and a private company. The AMR system is composed by reader devices and a group of elements that allow a wireless connection to a central server. The system is based on taking a picture of the fluid meter digit display, preprocessing and transmitting it to a remote element using a radio frequency ad-hoc protocol. The reader device is implemented on a FPGA based system and the firmware can be updated remotely (remote reconfiguration). In addition, the different parameters of the reader can be configured remotely. To meet the low power requirements a sleep and wake-up technique is applied. All the requirements of the system have been covered, offering a hardware-software product that covers most needs of the end users.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114306275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Compton cameras acting as electronic collimators, improve the characteristics of nuclear medicine imaging, with an additional computational cost for the readout circuitry and digital control system. This paper presents the use of reconfigurable logic based hardware-software co-design, to deal with such tasks as the ones related to the electronic collimation architecture used on gamma cameras. The readout circuitry has been implemented as dedicated logic and as an embedded system that contains it. Both are studied in terms of scalability in the number of channels and response time. This number of channels and the speed of acquisition of such channels define the overall performance achieved by the technique. A typical scenario of electronic collimation application, using a high purity pixelated CdZnTe crystal as the sensitive material with a pixellated anode design, is the base of this performance study. The results of this study are the exact design parameters of an FPGA based embedded system that performs all tasks associated with the control of an electronic collimator prototype.
{"title":"Viability Study of Soft-Processor Usage for Electronic Collimation Control in Medical Applications","authors":"E. Aguayo, R. Martin, G. Sutter, E. Boemo","doi":"10.1109/SPL.2007.371752","DOIUrl":"https://doi.org/10.1109/SPL.2007.371752","url":null,"abstract":"Compton cameras acting as electronic collimators, improve the characteristics of nuclear medicine imaging, with an additional computational cost for the readout circuitry and digital control system. This paper presents the use of reconfigurable logic based hardware-software co-design, to deal with such tasks as the ones related to the electronic collimation architecture used on gamma cameras. The readout circuitry has been implemented as dedicated logic and as an embedded system that contains it. Both are studied in terms of scalability in the number of channels and response time. This number of channels and the speed of acquisition of such channels define the overall performance achieved by the technique. A typical scenario of electronic collimation application, using a high purity pixelated CdZnTe crystal as the sensitive material with a pixellated anode design, is the base of this performance study. The results of this study are the exact design parameters of an FPGA based embedded system that performs all tasks associated with the control of an electronic collimator prototype.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125678492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Dessbesell, M.A. Pacheco, J.B. dos S. Martins, R.F. Molz
Connected components labeling is a commonly used procedure when performing image analysis and segmentation, as well as pattern recognition processing. The state-of-the-art approach, proposed by (S.-H. Yang et al., 2005), uses a parallel algorithm to achieve high speed operation. Based on it, an area and speed efficient VLSI architecture was designed. However, as the size of the input image increases, the area cost increases as well. This paper proposes an optimization for the method from (S.-H. Yang et al., 2005), achieving considerable area cost reduction, mainly when large images are considered. The area economy is accomplished by processing the input image in partitions of columns. This way, the higher the number of columns of the input image, the greater will be the area cost reduction.
在进行图像分析和分割以及模式识别处理时，连接组件标记是一种常用的程序。最先进的方法，由s.h。Yang et al.， 2005)采用并行算法实现高速运算。在此基础上，设计了一种面积和速度高效的VLSI体系结构。然而，随着输入图像尺寸的增加，面积成本也会增加。本文从(s - h)对该方法进行了优化。Yang et al.， 2005)，实现了相当大的面积成本降低，主要是在考虑大图像时。区域经济是通过对输入图像进行分栏处理来实现的。这样，输入图像的列数越多，减少的面积成本就越大。
{"title":"An Area Cost Optimized Fast Parallel Label Assignment VLSI Architecture","authors":"G. Dessbesell, M.A. Pacheco, J.B. dos S. Martins, R.F. Molz","doi":"10.1109/SPL.2007.371740","DOIUrl":"https://doi.org/10.1109/SPL.2007.371740","url":null,"abstract":"Connected components labeling is a commonly used procedure when performing image analysis and segmentation, as well as pattern recognition processing. The state-of-the-art approach, proposed by (S.-H. Yang et al., 2005), uses a parallel algorithm to achieve high speed operation. Based on it, an area and speed efficient VLSI architecture was designed. However, as the size of the input image increases, the area cost increases as well. This paper proposes an optimization for the method from (S.-H. Yang et al., 2005), achieving considerable area cost reduction, mainly when large images are considered. The area economy is accomplished by processing the input image in partitions of columns. This way, the higher the number of columns of the input image, the greater will be the area cost reduction.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128154332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pulse width modulation (PWM) is a very common technique used in different applications, from the control of motors, switching power converters (power supplies), audio amplifiers or illumination systems. In some of those applications, the pulse frequency has increased so much in the last years that the resolution obtained with classical (counter) techniques is not enough. This paper explains some methods used for increasing the resolution of PWMs and proposes a new method based on the resources available in almost every FPGA nowadays.
{"title":"High Resolution Pulse Width Modulators in FPGA","authors":"Á. de Castro, G. Sutter, S. C. Huerta, J. Cobos","doi":"10.1109/SPL.2007.371737","DOIUrl":"https://doi.org/10.1109/SPL.2007.371737","url":null,"abstract":"Pulse width modulation (PWM) is a very common technique used in different applications, from the control of motors, switching power converters (power supplies), audio amplifiers or illumination systems. In some of those applications, the pulse frequency has increased so much in the last years that the resolution obtained with classical (counter) techniques is not enough. This paper explains some methods used for increasing the resolution of PWMs and proposes a new method based on the resources available in almost every FPGA nowadays.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121929422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a fast text to braille translator based on field programmable gate arrays (FPGAs). Compared with most commercial methods, this translator is able to carry out the translation in hardware instead of using software. To achieve the fast translation, a FPGA with big programmable resource has been utilized, and an algorithm, proposed by Paul Blenkhorn, has been revised to perform the fast translation. The translator has been described using very high speed integrated circuit hardware description language (VHDL). The test results indicate that the hardware-based translator achieves the same results as software-based commercial translators, and moreover, this system achieves superior throughput compared to Blenkhorn's original algorithm.
{"title":"A System for Fast Text-to-Braille Translation Based on FPGAs","authors":"Xuan Zhang, C. Ortega-Sanchez, L. Murray","doi":"10.1109/SPL.2007.371735","DOIUrl":"https://doi.org/10.1109/SPL.2007.371735","url":null,"abstract":"This paper describes a fast text to braille translator based on field programmable gate arrays (FPGAs). Compared with most commercial methods, this translator is able to carry out the translation in hardware instead of using software. To achieve the fast translation, a FPGA with big programmable resource has been utilized, and an algorithm, proposed by Paul Blenkhorn, has been revised to perform the fast translation. The translator has been described using very high speed integrated circuit hardware description language (VHDL). The test results indicate that the hardware-based translator achieves the same results as software-based commercial translators, and moreover, this system achieves superior throughput compared to Blenkhorn's original algorithm.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130135885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. El-Araby, M. Taher, M. Abouellail, T. El-Ghazawi, G. Newby
Most application developers are willing to give up some performance and chip utilization in exchange of productivity. High-level tools for developing reconfigurable computing applications trade performance with ease-of-use. However, it is hard to know in a general sense how much performance and utilization one is giving up and how much ease-of-use he/she is gaining. More importantly, given the lack of standards and the uncertainty generated by sales literature, it is very hard to know the real differences that exist among different high-level programming paradigms. In order to do so, one needs a formal methodology and/or a framework that uses a common set of metrics and common experiments over a number of representative tools. In this work, we consider three representative high-level tools, Impulse-C, Mitrion-C, and DSPLogic in the Cray XD1 environment. These tools were selected to represent imperative programming, functional programming and graphical programming, and thereby demonstrate the applicability of our methodology. It will be shown that in spite of the disparity in concepts behind those tools, our methodology will be able to formally uncover the basic differences among them and analytically assess their comparative performance, utilization, and ease-of-use.
{"title":"Comparative Analysis of High Level Programming for Reconfigurable Computers: Methodology and Empirical Study","authors":"E. El-Araby, M. Taher, M. Abouellail, T. El-Ghazawi, G. Newby","doi":"10.1109/SPL.2007.371731","DOIUrl":"https://doi.org/10.1109/SPL.2007.371731","url":null,"abstract":"Most application developers are willing to give up some performance and chip utilization in exchange of productivity. High-level tools for developing reconfigurable computing applications trade performance with ease-of-use. However, it is hard to know in a general sense how much performance and utilization one is giving up and how much ease-of-use he/she is gaining. More importantly, given the lack of standards and the uncertainty generated by sales literature, it is very hard to know the real differences that exist among different high-level programming paradigms. In order to do so, one needs a formal methodology and/or a framework that uses a common set of metrics and common experiments over a number of representative tools. In this work, we consider three representative high-level tools, Impulse-C, Mitrion-C, and DSPLogic in the Cray XD1 environment. These tools were selected to represent imperative programming, functional programming and graphical programming, and thereby demonstrate the applicability of our methodology. It will be shown that in spite of the disparity in concepts behind those tools, our methodology will be able to formally uncover the basic differences among them and analytically assess their comparative performance, utilization, and ease-of-use.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"509 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116331555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tool path generation is one of the most complex problems in computer aided manufacturing. Although some efficient strategies have been developed, most of them are only useful for standard machining. The algorithm called Virtual Digitizing avoids this problem by its own definition but its computing cost is high and make it difficult for being integrated in standard machining in order to adopt the new ISO standard 14649. Presented in the paper there is a Virtual Digitizing architecture that takes the advantages of reconfigurable computing (using field programmable gate arrays) in order to improve the algorithm efficiency. FPGAs are used as low cost and low frequency coprocessor to accelerate the calculation of tool path, meeting the actual restrictions of the computer numeric controls (CNCs) at the same time. A prototype has been implemented to measure the real impact on the total computing time.
{"title":"Accelerating Tool Path Computing in Turning Lathe Machining","authors":"A. Jimeno, S. Cuenca, A. Martinez, J. Romero","doi":"10.1109/SPL.2007.371727","DOIUrl":"https://doi.org/10.1109/SPL.2007.371727","url":null,"abstract":"Tool path generation is one of the most complex problems in computer aided manufacturing. Although some efficient strategies have been developed, most of them are only useful for standard machining. The algorithm called Virtual Digitizing avoids this problem by its own definition but its computing cost is high and make it difficult for being integrated in standard machining in order to adopt the new ISO standard 14649. Presented in the paper there is a Virtual Digitizing architecture that takes the advantages of reconfigurable computing (using field programmable gate arrays) in order to improve the algorithm efficiency. FPGAs are used as low cost and low frequency coprocessor to accelerate the calculation of tool path, meeting the actual restrictions of the computer numeric controls (CNCs) at the same time. A prototype has been implemented to measure the real impact on the total computing time.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128647765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.
{"title":"Exploring FPGA Capabilities for Building Symmetric Multiprocessor Systems","authors":"P. Huerta, J. Castillo, J.I. Martinez, C. Pedraza","doi":"10.1109/SPL.2007.371733","DOIUrl":"https://doi.org/10.1109/SPL.2007.371733","url":null,"abstract":"Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134378352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Wolf, J. A. Holanda, Vanderlei Bonato, Rafael Peron, E. Marques
Mobile robotics and embedded systems are two research areas that have been receiving a considerable attention in years. Combining these two research topics is a very interesting and promising task. Some of the problems of controlling robots using embedded systems are designing device drivers, provide network communication, and develop complex control algorithms under hardware limitations. Player is one of the most used controllers for mobile robots and sensors. It has been widely used by the robotics community. This paper presents an embedded implementation of Player client mobile robot using the NIOS II softcore. Our client has been experimentally tested on a FPGA board and compared to a standard PC implementation.
{"title":"An FPGA-Based Mobile Robot Controller","authors":"D. Wolf, J. A. Holanda, Vanderlei Bonato, Rafael Peron, E. Marques","doi":"10.1109/SPL.2007.371734","DOIUrl":"https://doi.org/10.1109/SPL.2007.371734","url":null,"abstract":"Mobile robotics and embedded systems are two research areas that have been receiving a considerable attention in years. Combining these two research topics is a very interesting and promising task. Some of the problems of controlling robots using embedded systems are designing device drivers, provide network communication, and develop complex control algorithms under hardware limitations. Player is one of the most used controllers for mobile robots and sensors. It has been widely used by the robotics community. This paper presents an embedded implementation of Player client mobile robot using the NIOS II softcore. Our client has been experimentally tested on a FPGA board and compared to a standard PC implementation.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126015831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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