This paper describes a Braille note taker implemented in hardware. The system is able to perform Braille to text translation as well as note taking. A method is presented on how to achieve Braille note taking using a Braille keyboard. To perform Braille to text translation, a translating system has been built based on previous work. Using very high speed integrated circuit hardware description language (VHDL) and a field programmable gate arrays (FPGAs) development platform, a system that includes the keyboard controller and translator has been hierarchically described and implemented.
{"title":"A Hardware Based Braille Note Taker","authors":"Xuan Zhang, C. Ortega-Sanchez, I. Murray","doi":"10.1109/SPL.2007.371736","DOIUrl":"https://doi.org/10.1109/SPL.2007.371736","url":null,"abstract":"This paper describes a Braille note taker implemented in hardware. The system is able to perform Braille to text translation as well as note taking. A method is presented on how to achieve Braille note taking using a Braille keyboard. To perform Braille to text translation, a translating system has been built based on previous work. Using very high speed integrated circuit hardware description language (VHDL) and a field programmable gate arrays (FPGAs) development platform, a system that includes the keyboard controller and translator has been hierarchically described and implemented.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124557700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Castillo, A. García, L. Parrilla, D. Morales, A. Lloris, U. Meyer-Baese
The intellectual property protection of reusable design modules are becoming a problem with the expansion of this design strategy. This paper propose a new protection method for IP cores to be implemented over FPGAs. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction that allows to detect the ownership right without interfering the normal operation of the system and requiring minimal modifications to the system. The IPP technique has been implemented on programmable devices, with negligible performance penalties.
{"title":"Digital Signature Embedding Technique for IP Core Protection","authors":"E. Castillo, A. García, L. Parrilla, D. Morales, A. Lloris, U. Meyer-Baese","doi":"10.1109/SPL.2007.371738","DOIUrl":"https://doi.org/10.1109/SPL.2007.371738","url":null,"abstract":"The intellectual property protection of reusable design modules are becoming a problem with the expansion of this design strategy. This paper propose a new protection method for IP cores to be implemented over FPGAs. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction that allows to detect the ownership right without interfering the normal operation of the system and requiring minimal modifications to the system. The IPP technique has been implemented on programmable devices, with negligible performance penalties.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131204660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will integrate many processor nodes and memory units. To interconnect these IP nodes, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. One major problem consists in being able to compare choices and strategies in NoC design. To tackle this problem, we propose a complete highly configurable framework called Polymorpher which enables a quantitative comparison of the performance and energy consumption of different NoC communication component architectures. Our models are based on a set of basic VHDL communication components that can be reused for different designs. This common test-bed allows us to fairly and accurately compare different types of communication components in terms of energy consumption, delay and area. In particular, the framework enables easy instantiation and exploration of different types of routers. We have chosen to explore different switching strategies and parameters as an example of the possibilities offered by our tool. Our study compares quantitatively different switching techniques widely used in NoCs (store and forward, virtual cut through, wormhole) in terms of power consumption, area overhead and delay with a post lay-out gate-level simulation.
{"title":"Quantitative Comparison of Switching Strategies for Networks on Chip","authors":"A. Leroy, J. Picalausa, D. Milojevic","doi":"10.1109/SPL.2007.371724","DOIUrl":"https://doi.org/10.1109/SPL.2007.371724","url":null,"abstract":"To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will integrate many processor nodes and memory units. To interconnect these IP nodes, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. One major problem consists in being able to compare choices and strategies in NoC design. To tackle this problem, we propose a complete highly configurable framework called Polymorpher which enables a quantitative comparison of the performance and energy consumption of different NoC communication component architectures. Our models are based on a set of basic VHDL communication components that can be reused for different designs. This common test-bed allows us to fairly and accurately compare different types of communication components in terms of energy consumption, delay and area. In particular, the framework enables easy instantiation and exploration of different types of routers. We have chosen to explore different switching strategies and parameters as an example of the possibilities offered by our tool. Our study compares quantitatively different switching techniques widely used in NoCs (store and forward, virtual cut through, wormhole) in terms of power consumption, area overhead and delay with a post lay-out gate-level simulation.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125715473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of a platform based video streaming server using the Xilinx microblaze processor and a custom H.263 hardware compression core is presented. The design uses a novel data structure to store the input images in external memory, allowing the H.263 core and the associated camera interface to utilise the external memory bandwidth more efficiently. The finished system is capable of encoding and streaming, using the real-time transport protocol, Dl sized video, at 30 frames per second in a Spartan-3 1500 FPGA device.
{"title":"A Low-Cost, FPGA Based, Video Streaming Server","authors":"G. Stewart, D. Renshaw, M. Riley","doi":"10.1109/SPL.2007.371746","DOIUrl":"https://doi.org/10.1109/SPL.2007.371746","url":null,"abstract":"The design of a platform based video streaming server using the Xilinx microblaze processor and a custom H.263 hardware compression core is presented. The design uses a novel data structure to store the input images in external memory, allowing the H.263 core and the associated camera interface to utilise the external memory bandwidth more efficiently. The finished system is capable of encoding and streaming, using the real-time transport protocol, Dl sized video, at 30 frames per second in a Spartan-3 1500 FPGA device.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129368590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Gago, L. Rodríguez-Ramos, G. Herrera, J. Gigante, Angel Alonso, T. Viera, J. Piqueras, J. J. Díaz
This paper describes the development of the tip-tilt mirror control for an adaptive optics system based on the use of FPGA technology instead of using the traditional approach with DSP or microprocessor. The aim of this work is to show that for this kind of application the FPGA technology is not only a viable solution but probably also the best one in some situations, especially when a huge amount of parallel data processing is needed. This will probably be the case of adaptive optics systems for very large telescopes. A brief description of the whole adaptive optics system will be given although the paper will focus especially on the tip-tilt mirror control and its implementation with FPGAs. A new version of the deformable mirror control is also being implemented in FPGAs and will be finished in the near future.
{"title":"Tip-Tilt Mirror Control Based on FPGA for an Adaptive Optics System","authors":"F. Gago, L. Rodríguez-Ramos, G. Herrera, J. Gigante, Angel Alonso, T. Viera, J. Piqueras, J. J. Díaz","doi":"10.1109/SPL.2007.371718","DOIUrl":"https://doi.org/10.1109/SPL.2007.371718","url":null,"abstract":"This paper describes the development of the tip-tilt mirror control for an adaptive optics system based on the use of FPGA technology instead of using the traditional approach with DSP or microprocessor. The aim of this work is to show that for this kind of application the FPGA technology is not only a viable solution but probably also the best one in some situations, especially when a huge amount of parallel data processing is needed. This will probably be the case of adaptive optics systems for very large telescopes. A brief description of the whole adaptive optics system will be given although the paper will focus especially on the tip-tilt mirror control and its implementation with FPGAs. A new version of the deformable mirror control is also being implemented in FPGAs and will be finished in the near future.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127018508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Liberatori, F. Otero, J. C. Bonadero, J. Castiñeira
The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen, has been selected as the official advanced encryption standard (AES) and it is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 64-bit FPGA implementation of the 128- bit block and 128 bit-key AES cipher. Selected FPGA Family is Spartan 3. The cipher consumes 52 clock cycles for algorithm encryption, resulting in a throughput of 120 Mbps. Synthesis results in the use of 1643 slices, 975 flip flops, 3055 4-input look up tables and operates at 224 Mbps (maximum throughput). The design target was optimization of speed and cost.
{"title":"AES-128 Cipher. High Speed, Low Cost FPGA Implementation","authors":"M. Liberatori, F. Otero, J. C. Bonadero, J. Castiñeira","doi":"10.1109/SPL.2007.371748","DOIUrl":"https://doi.org/10.1109/SPL.2007.371748","url":null,"abstract":"The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen, has been selected as the official advanced encryption standard (AES) and it is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 64-bit FPGA implementation of the 128- bit block and 128 bit-key AES cipher. Selected FPGA Family is Spartan 3. The cipher consumes 52 clock cycles for algorithm encryption, resulting in a throughput of 120 Mbps. Synthesis results in the use of 1643 slices, 975 flip flops, 3055 4-input look up tables and operates at 224 Mbps (maximum throughput). The design target was optimization of speed and cost.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121805758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Code compression has been shown to be efficient in minimizing memory sizes for embedded systems as well as in power consumption reduction and performance improvement. In this paper we claim that code compression is also able to minimize the performance penalty of bus encryption schemes, where a ciphered program flows through a deciphering unit and reaches the processing unit. The result on performance for the Leon Processor, using a set of benchmarks from MediaBench and MiBench suites reveals that the AES deciphering unit can be used more rarely (50% less) and performance is never degraded comparing to the original secure system.
{"title":"Bus Decryption Overhead Minimization with Code Compression","authors":"E. Wanderley, G. Gogniat, J. Diguet","doi":"10.1109/SPL.2007.371757","DOIUrl":"https://doi.org/10.1109/SPL.2007.371757","url":null,"abstract":"Code compression has been shown to be efficient in minimizing memory sizes for embedded systems as well as in power consumption reduction and performance improvement. In this paper we claim that code compression is also able to minimize the performance penalty of bus encryption schemes, where a ciphered program flows through a deciphering unit and reaches the processing unit. The result on performance for the Leon Processor, using a set of benchmarks from MediaBench and MiBench suites reveals that the AES deciphering unit can be used more rarely (50% less) and performance is never degraded comparing to the original secure system.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121425094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we present an area optimized FPGA implementation of an IP core to compute the base-N logarithm. Nevertheless, we also discuss the area, speed and precision trade-offs. We selected an algorithm that could be implemented on any FPGA avoiding vendor specific features like block RAMs, embedded multipliers, etc. We report the implementation results of a fixed point version of the algorithm using various common configurations on Xilinx and Actel devices. This implementation achieved the required area goals providing a very good speed-area ratio.
{"title":"FPGA Implementation of Base-N Logarithm","authors":"S. E. Tropea","doi":"10.1109/SPL.2007.371719","DOIUrl":"https://doi.org/10.1109/SPL.2007.371719","url":null,"abstract":"In this work, we present an area optimized FPGA implementation of an IP core to compute the base-N logarithm. Nevertheless, we also discuss the area, speed and precision trade-offs. We selected an algorithm that could be implemented on any FPGA avoiding vendor specific features like block RAMs, embedded multipliers, etc. We report the implementation results of a fixed point version of the algorithm using various common configurations on Xilinx and Actel devices. This implementation achieved the required area goals providing a very good speed-area ratio.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130533390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Rodellar, F. Diaz, Bogdan Belean, R. Malutan, B. Stetter, Pedro Gómez, Rafael Martínez, Eloy García, J. Peldez
There are many fields in biomedical engineering where portability, compactness and robustness at the application level is an important requirement. Genomic microarray tests are becoming a routine exploration in many areas of medicine, biology and pharmacology. These tests have to fulfill strict and cumbersome protocols which prevent them from being universally applied in remote areas or situations where access to hospital facilities is difficult, as in the case of ship crews, military detachments or in the attention to isolated populations in underdeveloped countries. Seeking for solutions to translate sophisticated exploration methods as these may imply the detection and treatment of different genetic-induced illnesses and help in extending high standard medicine to these situations. In the present paper a hand-held portable application to inspect genetic microarrays is presented, which may be used in the field with important advantages on autonomy and robustness. The system is based on CCD microarray image scanning plus advanced image processing software for robust detection and reading supported by an FPGA. The platform is conceived for stand-alone use and low weight and consumption, making it ideal for applications in telemedicine. Facilities for data storage in a laptop are also provided.
{"title":"Genomic Microarray Processing on a FPGA for Portable Remote Applications","authors":"V. Rodellar, F. Diaz, Bogdan Belean, R. Malutan, B. Stetter, Pedro Gómez, Rafael Martínez, Eloy García, J. Peldez","doi":"10.1109/SPL.2007.371717","DOIUrl":"https://doi.org/10.1109/SPL.2007.371717","url":null,"abstract":"There are many fields in biomedical engineering where portability, compactness and robustness at the application level is an important requirement. Genomic microarray tests are becoming a routine exploration in many areas of medicine, biology and pharmacology. These tests have to fulfill strict and cumbersome protocols which prevent them from being universally applied in remote areas or situations where access to hospital facilities is difficult, as in the case of ship crews, military detachments or in the attention to isolated populations in underdeveloped countries. Seeking for solutions to translate sophisticated exploration methods as these may imply the detection and treatment of different genetic-induced illnesses and help in extending high standard medicine to these situations. In the present paper a hand-held portable application to inspect genetic microarrays is presented, which may be used in the field with important advantages on autonomy and robustness. The system is based on CCD microarray image scanning plus advanced image processing software for robust detection and reading supported by an FPGA. The platform is conceived for stand-alone use and low weight and consumption, making it ideal for applications in telemedicine. Facilities for data storage in a laptop are also provided.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134381715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A phase locked loop (PLL) based on digital signal processing and random sampling is proposed in this paper. Field programmable gate array (FPGA) technology is used to implement a prototype. The random sampling scheme is used to reduce the sampling frequency requirements without aliasing effects. The possibility of sampling and processing at lower frequencies allows the implementation of complete-digital high-frequency systems, without limitations imposed by the analog to digital converter and the signal processing unit. The basic principles are presented, and the implemented algorithms are described. Experimental results show the PLL performance.
{"title":"FPGA Implementation of a Phase Locked Loop Based on Random Sampling","authors":"M. O. Sonnaillon, F. Bonetto","doi":"10.1109/SPL.2007.371715","DOIUrl":"https://doi.org/10.1109/SPL.2007.371715","url":null,"abstract":"A phase locked loop (PLL) based on digital signal processing and random sampling is proposed in this paper. Field programmable gate array (FPGA) technology is used to implement a prototype. The random sampling scheme is used to reduce the sampling frequency requirements without aliasing effects. The possibility of sampling and processing at lower frequencies allows the implementation of complete-digital high-frequency systems, without limitations imposed by the analog to digital converter and the signal processing unit. The basic principles are presented, and the implemented algorithms are described. Experimental results show the PLL performance.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134046849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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