Pub Date : 2018-05-07DOI: 10.1109/NATW.2018.8388862
Hui Jiang, Fanchen Zhang, Yi Sun, Jennifer Dworak
More stringent defect detection requirements have led to the creation of new fault models, such as the cell-aware fault model, that attempt to model defects that might be missed by traditional test sets. Unfortunately, the resulting test sets can be long, and thus we have explored a DFT-based approach to reduce test time by harnessing scan shift cycles for defect detection. However, even advanced fault models may still miss some defects (for example, defects between standard cells). The n-detect test approach attempts to detect such defects fortuitously by increasing the number of times that simpler faults (e.g. stuck-at faults) are detected. In this paper, we investigate the ability of our DFT circuitry to provide multiple stuck-at fault detections of the hardest to detect stuck-at faults during scan shift. We will show that significant additional fault detections are possible in the circuits studied, even when only a subset of all scan chain flops are used for scan shift capture.
{"title":"One more time! Increasing fault detection with scan shift capture","authors":"Hui Jiang, Fanchen Zhang, Yi Sun, Jennifer Dworak","doi":"10.1109/NATW.2018.8388862","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388862","url":null,"abstract":"More stringent defect detection requirements have led to the creation of new fault models, such as the cell-aware fault model, that attempt to model defects that might be missed by traditional test sets. Unfortunately, the resulting test sets can be long, and thus we have explored a DFT-based approach to reduce test time by harnessing scan shift cycles for defect detection. However, even advanced fault models may still miss some defects (for example, defects between standard cells). The n-detect test approach attempts to detect such defects fortuitously by increasing the number of times that simpler faults (e.g. stuck-at faults) are detected. In this paper, we investigate the ability of our DFT circuitry to provide multiple stuck-at fault detections of the hardest to detect stuck-at faults during scan shift. We will show that significant additional fault detections are possible in the circuits studied, even when only a subset of all scan chain flops are used for scan shift capture.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125357419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-07DOI: 10.1109/NATW.2018.8388861
Mehmet Ince, E. Yilmaz, S. Ozev
With the advent of built-in self-test (BIST) in analog and RF circuits, it is essential that the fault coverage of potential BIST solutions be evaluated before they are deployed. However, large scale fault simulations are often infeasible even when considering the extensive computational power available today. Fault simulations are more challenging for devices that contain frequency transformation, such as phased locked loops (PLLs) or mixers. Thus, a mixed-mode simulation is necessary that captures fault behavior at the lower levels of the hierarchy and propagates this information to the system-level. Mixed-mode simulators, such as Verilog-A, can be used for evaluating nominal circuit behavior but falls short when evaluating faulty circuit behavior. This paper presents a macro modeling approach for mixed-signal circuits through a case study of voltage controlled oscillators (VCOs) used in PLLs. The evaluated BIST technique is the measurement of the phase transfer function from the input to the output. This requires a long transient simulation due to the need to capture the high frequency behavior of the PLL while covering the settling time of the low-frequency filter and VCO input. As the ratio of the output to the input frequency increases, simulation time also increases, making the analyses prohibitively expensive for some cases. In this paper, we build a MATLAB/Simulink model of the VCO and PLL, which is also designed and simulated at the transistor level using the FinFET technology. By modeling free running frequency, sensitivity, duty cycle, non-linearity, and phase noise characteristic of the VCO, we show that both PLL simulations, one using Spice, and one using the proposed macromodeling technique along with Simulink, match in response whereas the proposed approach only takes a fraction of time of Spice simulations.
{"title":"Enabling fast process variation and fault simulation through macromodelling of analog components","authors":"Mehmet Ince, E. Yilmaz, S. Ozev","doi":"10.1109/NATW.2018.8388861","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388861","url":null,"abstract":"With the advent of built-in self-test (BIST) in analog and RF circuits, it is essential that the fault coverage of potential BIST solutions be evaluated before they are deployed. However, large scale fault simulations are often infeasible even when considering the extensive computational power available today. Fault simulations are more challenging for devices that contain frequency transformation, such as phased locked loops (PLLs) or mixers. Thus, a mixed-mode simulation is necessary that captures fault behavior at the lower levels of the hierarchy and propagates this information to the system-level. Mixed-mode simulators, such as Verilog-A, can be used for evaluating nominal circuit behavior but falls short when evaluating faulty circuit behavior. This paper presents a macro modeling approach for mixed-signal circuits through a case study of voltage controlled oscillators (VCOs) used in PLLs. The evaluated BIST technique is the measurement of the phase transfer function from the input to the output. This requires a long transient simulation due to the need to capture the high frequency behavior of the PLL while covering the settling time of the low-frequency filter and VCO input. As the ratio of the output to the input frequency increases, simulation time also increases, making the analyses prohibitively expensive for some cases. In this paper, we build a MATLAB/Simulink model of the VCO and PLL, which is also designed and simulated at the transistor level using the FinFET technology. By modeling free running frequency, sensitivity, duty cycle, non-linearity, and phase noise characteristic of the VCO, we show that both PLL simulations, one using Spice, and one using the proposed macromodeling technique along with Simulink, match in response whereas the proposed approach only takes a fraction of time of Spice simulations.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122753913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/NATW.2018.8388868
Imtiaz Ahmed, Subhash Baraiya, Rahul Singhal
IC designs have been growing exponentially in size but the number of pins have not kept the same pace. This imbalance poses a difficult challenge when a design has very limited number of test pins but still requires a high quality testing. This problem is exacerbated when additional fault models like transition delay fault model are required for testing. This paper describes how a low pin count test controller was able to meet all these requirements to test a pin limited transceiver chip used in Qualcomm Technologies Inc.'s state-of-the-art chipset. The low pin count test controller supports at-speed testing with on-chip clock controller and exceeded the test coverage requirements for both stuck-at and at-speed testing by 1.22% and 2.16% respectively. During wafer testing, this test-pin savings enabled higher parallel testing of dies using multi-site testing which reduced the test-costs by about 1.6x.
{"title":"Case study on low pin count testing of industry transceiver chip","authors":"Imtiaz Ahmed, Subhash Baraiya, Rahul Singhal","doi":"10.1109/NATW.2018.8388868","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388868","url":null,"abstract":"IC designs have been growing exponentially in size but the number of pins have not kept the same pace. This imbalance poses a difficult challenge when a design has very limited number of test pins but still requires a high quality testing. This problem is exacerbated when additional fault models like transition delay fault model are required for testing. This paper describes how a low pin count test controller was able to meet all these requirements to test a pin limited transceiver chip used in Qualcomm Technologies Inc.'s state-of-the-art chipset. The low pin count test controller supports at-speed testing with on-chip clock controller and exceeded the test coverage requirements for both stuck-at and at-speed testing by 1.22% and 2.16% respectively. During wafer testing, this test-pin savings enabled higher parallel testing of dies using multi-site testing which reduced the test-costs by about 1.6x.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126280167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/NATW.2018.8388865
M. Shur, J. Suarez
The increasing complexity of silicon VLSI circuits makes their comprehensive testing, determination of counterfeit parts, and predictions of reliability a growing challenge. We analyze the response of Si MOSFETs to sub-THz and THz radiation for different feature sizes and temperatures. Our results show that such testing could be expanded to develop unique response signatures for contact and channel regions for feature sizes exceeding 20 nm. They also indicate a possibility of the resonant MOSFET response to the THz radiation at cryogenic temperatures.
{"title":"Nanoscale silicon mosfet response to THz radiation for testing VLSI","authors":"M. Shur, J. Suarez","doi":"10.1109/NATW.2018.8388865","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388865","url":null,"abstract":"The increasing complexity of silicon VLSI circuits makes their comprehensive testing, determination of counterfeit parts, and predictions of reliability a growing challenge. We analyze the response of Si MOSFETs to sub-THz and THz radiation for different feature sizes and temperatures. Our results show that such testing could be expanded to develop unique response signatures for contact and channel regions for feature sizes exceeding 20 nm. They also indicate a possibility of the resonant MOSFET response to the THz radiation at cryogenic temperatures.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"535 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123089916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/NATW.2018.8388864
Timothy M. Platt, Chen Liu
The cost of semiconductor test is often strongly related to the die test time. Reducing this time is always a goal for both the fab customer as well as the semiconductor test house. Techniques to achieve test time reduction have included the use of dedicated hardware to perform certain test functions. While these techniques are effective, they can be time consuming to develop and this effort is often a deterrent to their development and use. This paper describes how a Field Programmable Gate Array (FPGA) accelerator can be used to process wafer test data. Historically, the use of FPGAs required a skilled digital designer to create the necessary logic to implement the intended test processing hardware. With OpenCL, however, the addition of hardware acceleration can be accomplished with traditional software coding. The amount of time required to deliver the test solution can be reduced from multiple weeks (or longer) to just a few days. With OpenCL, the ability to use hardware acceleration is brought to test engineers who do not have skills to designs FPGA logic.
{"title":"Reducing test time with FPGA accelerators using OpenCL","authors":"Timothy M. Platt, Chen Liu","doi":"10.1109/NATW.2018.8388864","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388864","url":null,"abstract":"The cost of semiconductor test is often strongly related to the die test time. Reducing this time is always a goal for both the fab customer as well as the semiconductor test house. Techniques to achieve test time reduction have included the use of dedicated hardware to perform certain test functions. While these techniques are effective, they can be time consuming to develop and this effort is often a deterrent to their development and use. This paper describes how a Field Programmable Gate Array (FPGA) accelerator can be used to process wafer test data. Historically, the use of FPGAs required a skilled digital designer to create the necessary logic to implement the intended test processing hardware. With OpenCL, however, the addition of hardware acceleration can be accomplished with traditional software coding. The amount of time required to deliver the test solution can be reduced from multiple weeks (or longer) to just a few days. With OpenCL, the ability to use hardware acceleration is brought to test engineers who do not have skills to designs FPGA logic.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134080056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/NATW.2018.8388867
Nabil El Belghiti Alaoui, P. Tounsi, A. Boyer, A. Viard
With the density increase of today's printed circuit board assemblies (PCBA), the electronic test methods reached their limits, in the same time the requirements of high reliability and robustness are greater. Original equipment manufacturers are obliged to reduce the number of physical test points and to find better-adapted test methods. Current test methods must be rethought to include a large panel of physical phenomena that can be used to detect electrical defects of components, absence, wrong value, and shorts at component level on the board under test (BUT). We will present the possibility of using electromagnetic signature to diagnose faulty components contactlessly. The technique consists in using small diameter near electromagnetic field probes, which detect the field distribution over powered sensitive components. A giant magnetoresistance (GMR) sensor was used as well to detect variations in low frequency components. The loading of the BUT is specifically chosen to enhance the sensitivity of the EM measurements. Reference EM signatures are extracted from a fault-free circuit, which will be compared to those extracted from a sample PCBA in which we introduced a component level defect by removing or changing the value of critical components. As a result, we will show that the amplitude of a specific harmonic acts as a sensing parameter, which is accurately related to the variation of the component value.
{"title":"New testing approach using near electromagnetic field probing intending to upgrade in-circuit testing of high density PCBAs","authors":"Nabil El Belghiti Alaoui, P. Tounsi, A. Boyer, A. Viard","doi":"10.1109/NATW.2018.8388867","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388867","url":null,"abstract":"With the density increase of today's printed circuit board assemblies (PCBA), the electronic test methods reached their limits, in the same time the requirements of high reliability and robustness are greater. Original equipment manufacturers are obliged to reduce the number of physical test points and to find better-adapted test methods. Current test methods must be rethought to include a large panel of physical phenomena that can be used to detect electrical defects of components, absence, wrong value, and shorts at component level on the board under test (BUT). We will present the possibility of using electromagnetic signature to diagnose faulty components contactlessly. The technique consists in using small diameter near electromagnetic field probes, which detect the field distribution over powered sensitive components. A giant magnetoresistance (GMR) sensor was used as well to detect variations in low frequency components. The loading of the BUT is specifically chosen to enhance the sensitivity of the EM measurements. Reference EM signatures are extracted from a fault-free circuit, which will be compared to those extracted from a sample PCBA in which we introduced a component level defect by removing or changing the value of critical components. As a result, we will show that the amplitude of a specific harmonic acts as a sensing parameter, which is accurately related to the variation of the component value.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126035460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/NATW.2018.8388863
Wei Jiang, Guoan Wang
In this paper, we propose a simplified on-chip calibration method for multi-port devices to de-embed the unwanted but unavoidable parasitics introduced by the probing pads as well as the effects originating from redundant feeding lines. The traditional TRL (Thru, Reflect, Line) calibration technique for single-ended two-port device is extended to a classic on-chip branch-line coupler that can be decomposed as the odd-and even-mode equivalent circuit. Accordingly, the TRL calibration standards in the balanced format are designed as well. As a final step, 4-port single-ended S-parameters of device under test (DUT) are reconstructed through its de-embedded odd-and even-mode S-parameters. To validate the efficacy of our proposed method in extracting S-parameters of DUT, models in HFSS, such as the branch-line coupler with probing pads, and modified TRL calibration standards are generated. After performing the de-embedding procedures with the proposed calibration method in this paper, the extracted S-parameters agree well with the simulated S-parameters of DUT without adding any pads and feeding lines for measurement.
{"title":"A simplified on-chip calibration method for branch-line coupler","authors":"Wei Jiang, Guoan Wang","doi":"10.1109/NATW.2018.8388863","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388863","url":null,"abstract":"In this paper, we propose a simplified on-chip calibration method for multi-port devices to de-embed the unwanted but unavoidable parasitics introduced by the probing pads as well as the effects originating from redundant feeding lines. The traditional TRL (Thru, Reflect, Line) calibration technique for single-ended two-port device is extended to a classic on-chip branch-line coupler that can be decomposed as the odd-and even-mode equivalent circuit. Accordingly, the TRL calibration standards in the balanced format are designed as well. As a final step, 4-port single-ended S-parameters of device under test (DUT) are reconstructed through its de-embedded odd-and even-mode S-parameters. To validate the efficacy of our proposed method in extracting S-parameters of DUT, models in HFSS, such as the branch-line coupler with probing pads, and modified TRL calibration standards are generated. After performing the de-embedding procedures with the proposed calibration method in this paper, the extracted S-parameters agree well with the simulated S-parameters of DUT without adding any pads and feeding lines for measurement.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124667048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/NATW.2018.8388866
Ryan Pennucci, R. Jurasek, W. Hokenmaier, L. Patrick, J. Bucci, D. Labrecque, Dave Kinney
Multi-project wafers have lowered manufacturing costs for semiconductor prototypes, yet test costs remain high, presenting a barrier for innovation in the market. We present and analyze a low-cost test strategy for memory devices.
{"title":"An analysis of an inexpensive memory test solution","authors":"Ryan Pennucci, R. Jurasek, W. Hokenmaier, L. Patrick, J. Bucci, D. Labrecque, Dave Kinney","doi":"10.1109/NATW.2018.8388866","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388866","url":null,"abstract":"Multi-project wafers have lowered manufacturing costs for semiconductor prototypes, yet test costs remain high, presenting a barrier for innovation in the market. We present and analyze a low-cost test strategy for memory devices.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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