Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337677
Z. C. Shen, C. Chu
Congestion has been a topic of great importance in the floorplanning of deep-submicron Odesign. In this paper, we design an accurate and efficient congestion estimation model by performing global routing. We interpret the global routing problem as a flow problem of several commodities and relax the integral flow constraints. The objective of resulting fractional flow problem is to minimize the maximum congestion over all edges in the inner dual graph [ 131. The underlying routing graph for each commodity is derived by assigning directions to the inner dual graph edges. We design an efficient two-phase algorithm to solve this fractional flow problem. The first phase is denoted as Incoming Flow Balancing (IFB) by which a good initial solution is derived. The second phase is called Srepwise Flow Refinement (SFR) by which the maximum congestion of the solution in first phase is iteratively reduced to its optimal value. In addition, a valid global routing solution can be obtained by applying a simple rounding procedure on the fractional flow solution. The maximum congestion after rounding is only increased by 2.82% on average according to our experimental results. which justifies the use of fractional flow to estimate the routing congestion. Finally. we demonstrate our model by integrating it into a simulated annealing (SA) based floorplanner, where we use the maximum congestion as part of the cost of SA. The experimental results show that, on average, our congestion-driven floorplanner can generate a much less congested floorplan (-36.44%) with a slight sacrifice in area (+1.30%) and wirelength (+2.64%). The runtime of the whole SA process is only increased moderately (+270%).
{"title":"Accurate and eff icient flow based congestion estimation in floorplanning","authors":"Z. C. Shen, C. Chu","doi":"10.1109/ASPDAC.2004.1337677","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337677","url":null,"abstract":"Congestion has been a topic of great importance in the floorplanning of deep-submicron Odesign. In this paper, we design an accurate and efficient congestion estimation model by performing global routing. We interpret the global routing problem as a flow problem of several commodities and relax the integral flow constraints. The objective of resulting fractional flow problem is to minimize the maximum congestion over all edges in the inner dual graph [ 131. The underlying routing graph for each commodity is derived by assigning directions to the inner dual graph edges. We design an efficient two-phase algorithm to solve this fractional flow problem. The first phase is denoted as Incoming Flow Balancing (IFB) by which a good initial solution is derived. The second phase is called Srepwise Flow Refinement (SFR) by which the maximum congestion of the solution in first phase is iteratively reduced to its optimal value. In addition, a valid global routing solution can be obtained by applying a simple rounding procedure on the fractional flow solution. The maximum congestion after rounding is only increased by 2.82% on average according to our experimental results. which justifies the use of fractional flow to estimate the routing congestion. Finally. we demonstrate our model by integrating it into a simulated annealing (SA) based floorplanner, where we use the maximum congestion as part of the cost of SA. The experimental results show that, on average, our congestion-driven floorplanner can generate a much less congested floorplan (-36.44%) with a slight sacrifice in area (+1.30%) and wirelength (+2.64%). The runtime of the whole SA process is only increased moderately (+270%).","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122779085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337611
G. Parthasarathy, Madhu K. Iyer, K. Cheng, Li-C. Wang
Reachability checking and preimage computation are fundamental problems in ATPG and formal verification. Traditional sequential search techniques based on ATPG/SAT, or on OBDDS have diverging strengths and weaknesses. Here, we describe how structural analysis and conflict-based learning are combined in order to improve the efficiency of sequential search. We use conflict-based learning and illegal state learning across time-frames. We also address issues in efficiently bounding the search space in a single time-frame and across time-frames. We analyze each of these techniques experimentally and demonstrate the advantages of each technique. We compare performance against a commercial sequential ATPG engine and VIS [RK. Brayton et al., (1996)] on a set of standard benchmarks.
可达性检验和预像计算是ATPG和形式化验证中的基本问题。传统的基于ATPG/SAT的顺序搜索技术和基于OBDDS的顺序搜索技术各有优缺点。在这里，我们描述了如何将结构分析和基于冲突的学习相结合，以提高顺序搜索的效率。我们使用基于冲突的学习和跨时间框架的非法状态学习。我们还解决了在单个时间框架和跨时间框架内有效限定搜索空间的问题。我们通过实验分析了每种技术，并展示了每种技术的优点。我们将性能与商用顺序ATPG发动机和VIS [RK]进行比较。Brayton et al.，(1996)]在一组标准基准上。
{"title":"Efficient reachability checking using sequential SAT","authors":"G. Parthasarathy, Madhu K. Iyer, K. Cheng, Li-C. Wang","doi":"10.1109/ASPDAC.2004.1337611","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337611","url":null,"abstract":"Reachability checking and preimage computation are fundamental problems in ATPG and formal verification. Traditional sequential search techniques based on ATPG/SAT, or on OBDDS have diverging strengths and weaknesses. Here, we describe how structural analysis and conflict-based learning are combined in order to improve the efficiency of sequential search. We use conflict-based learning and illegal state learning across time-frames. We also address issues in efficiently bounding the search space in a single time-frame and across time-frames. We analyze each of these techniques experimentally and demonstrate the advantages of each technique. We compare performance against a commercial sequential ATPG engine and VIS [RK. Brayton et al., (1996)] on a set of standard benchmarks.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129604468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337646
K. Kagawa, Tomoaki Kawakami, Hiroaki Asazu, T. Ikeuchi, A. Fujiuchi, J. Ohta, M. Nunoshita
We have developed an image-sensor-based optical receiver for free-space optical communications. In our scheme, each pixel has a function of an optical receiver as well as an image sensor. The functional mode can be selected pixel hy pixel. The position of a communication target is detected from the image captured in the image sensor mode. Then, functional mode of the pixel receiving optical signals is changed to the optical receiver mode to start Communication. We designed and fabricated a 50x50-pixel photo receiver in a standard 0.35 -pm CMOS technology, and fundamental operations were successfully verified. Total transimpedance gain of more than 200 kR and data rate of 30 Mhps and 50 Mhps for wavelength of 830 nm and 650 nm, respectively, were obtained.
{"title":"An image-sensor-based optical receiver fabricated in a standard 0.35-/spl mu/m CMOS technology for free-space optical communications","authors":"K. Kagawa, Tomoaki Kawakami, Hiroaki Asazu, T. Ikeuchi, A. Fujiuchi, J. Ohta, M. Nunoshita","doi":"10.1109/ASPDAC.2004.1337646","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337646","url":null,"abstract":"We have developed an image-sensor-based optical receiver for free-space optical communications. In our scheme, each pixel has a function of an optical receiver as well as an image sensor. The functional mode can be selected pixel hy pixel. The position of a communication target is detected from the image captured in the image sensor mode. Then, functional mode of the pixel receiving optical signals is changed to the optical receiver mode to start Communication. We designed and fabricated a 50x50-pixel photo receiver in a standard 0.35 -pm CMOS technology, and fundamental operations were successfully verified. Total transimpedance gain of more than 200 kR and data rate of 30 Mhps and 50 Mhps for wavelength of 830 nm and 650 nm, respectively, were obtained.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129159469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337708
T. Aa, M. Jayapala, F. Barat, Geert Deconinck, R. Lauwereins, F. Catthoor, H. Corporaal
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, sofrwcre controlled clustered loop buffers are energy efficient. However current compilers for VLIW do not fully exploit the potentials offered by such a clustered organization This paper presents an algorithm to explore what is the optimal loop huffer configuration and the optimal way to use this configuration for an application or a set of applications. Results for the MediaBeneh application suite show an additional 18% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional nonclustered approaches to the loop huffer without compromising performance.
{"title":"Instruction buffering exploration for low energy VLIWs with instruction clusters","authors":"T. Aa, M. Jayapala, F. Barat, Geert Deconinck, R. Lauwereins, F. Catthoor, H. Corporaal","doi":"10.1109/ASPDAC.2004.1337708","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337708","url":null,"abstract":"For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, sofrwcre controlled clustered loop buffers are energy efficient. However current compilers for VLIW do not fully exploit the potentials offered by such a clustered organization This paper presents an algorithm to explore what is the optimal loop huffer configuration and the optimal way to use this configuration for an application or a set of applications. Results for the MediaBeneh application suite show an additional 18% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional nonclustered approaches to the loop huffer without compromising performance.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122757725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337584
C. Ong, Dongwoo Hong, K. Cheng, Li-C. Wang
We propose a method for extracting the spectral information of a multigigahertz jittery signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multigigahertz signal periods for spectral analysis. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results show that this analysis method can accurately estimate the amount and frequencies of periodic and random jitter of a multigigahertz signal.
{"title":"Jitter spectral extraction for multi-gigahertz signal","authors":"C. Ong, Dongwoo Hong, K. Cheng, Li-C. Wang","doi":"10.1109/ASPDAC.2004.1337584","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337584","url":null,"abstract":"We propose a method for extracting the spectral information of a multigigahertz jittery signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multigigahertz signal periods for spectral analysis. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results show that this analysis method can accurately estimate the amount and frequencies of periodic and random jitter of a multigigahertz signal.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116559867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ISCAS.2004.1329317
O. Hafiz, Pinhong Chen, Janet Roveda
Proper modeling of the switching windows leads to a better estimate of the noise induced delay variations. The present paper proposes a new continous switching window model. This new model is combined with an ordering technique that avoids convergence and multiple solution issues in the fixed point iteration methods. Experimental results show that our new model can achieve 2-3x times speedup over the fixed point iteration methods, and provide better simulation results than the discrete models and the event-driven based method.
{"title":"A non-iterative model for switching window computation with crosstalk noise","authors":"O. Hafiz, Pinhong Chen, Janet Roveda","doi":"10.1109/ISCAS.2004.1329317","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329317","url":null,"abstract":"Proper modeling of the switching windows leads to a better estimate of the noise induced delay variations. The present paper proposes a new continous switching window model. This new model is combined with an ordering technique that avoids convergence and multiple solution issues in the fixed point iteration methods. Experimental results show that our new model can achieve 2-3x times speedup over the fixed point iteration methods, and provide better simulation results than the discrete models and the event-driven based method.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124148614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fei Li, Lei He, J. Basile, Rakesh J. Patel, H. Ramamurthy
Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces large power-up current that may affect circuit reliability as well as introduce performance loss. We present an in-depth study of high-level power-up current modeling and estimation in the context of a full custom design environment with a rich cell library. We propose a methodology to estimate the circuit area in terms of gate count and maximum power-up current for any given logic function. We build novel estimation metrics based on logic synthesis and gate level analysis using only a small number of typical circuits, but no further logic synthesis and gate level analysis are needed during our estimation. Compared to time-consuming logic synthesis and gate level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area and 21.44% for maximum power-up current. In contrast, estimation based on quick synthesis leads to llx area difference in gate count for an Bbit adder.
{"title":"High-level area and power-up current estimation considering rich cell library","authors":"Fei Li, Lei He, J. Basile, Rakesh J. Patel, H. Ramamurthy","doi":"10.5555/1015090.1015329","DOIUrl":"https://doi.org/10.5555/1015090.1015329","url":null,"abstract":"Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces large power-up current that may affect circuit reliability as well as introduce performance loss. We present an in-depth study of high-level power-up current modeling and estimation in the context of a full custom design environment with a rich cell library. We propose a methodology to estimate the circuit area in terms of gate count and maximum power-up current for any given logic function. We build novel estimation metrics based on logic synthesis and gate level analysis using only a small number of typical circuits, but no further logic synthesis and gate level analysis are needed during our estimation. Compared to time-consuming logic synthesis and gate level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area and 21.44% for maximum power-up current. In contrast, estimation based on quick synthesis leads to llx area difference in gate count for an Bbit adder.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126155065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337670
G. Fey, R. Drechsler
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based verification is used. Large testbenches are created and if the design produces the correct output for all stimuli it is said to be correct. But there is no guarantee that the testbench is complete in the sense that it contains test-cases for all ¿important¿ situations. We propose an approach to detect ¿gaps¿ in testbenches, i.e. behavior that is not tested. The approach relies on automatic generation of properties from the testbench in terms of a formal property language. By construction the properties are valid within the testbench. A model checker proves the validity of the property on the design. If this proof succeeds, the testbench covers all possible situations for given signals. In case of failure counter-examples are produced. These counter-examples represent behavior that is not tested, i.e. a gap in the testhench. The feasibility of the approach is underlined by experiments.
{"title":"Improving simulation-based verification by means of formal methods","authors":"G. Fey, R. Drechsler","doi":"10.1109/ASPDAC.2004.1337670","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337670","url":null,"abstract":"The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based verification is used. Large testbenches are created and if the design produces the correct output for all stimuli it is said to be correct. But there is no guarantee that the testbench is complete in the sense that it contains test-cases for all ¿important¿ situations. We propose an approach to detect ¿gaps¿ in testbenches, i.e. behavior that is not tested. The approach relies on automatic generation of properties from the testbench in terms of a formal property language. By construction the properties are valid within the testbench. A model checker proves the validity of the property on the design. If this proof succeeds, the testbench covers all possible situations for given signals. In case of failure counter-examples are produced. These counter-examples represent behavior that is not tested, i.e. a gap in the testhench. The feasibility of the approach is underlined by experiments.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"10 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120856416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337602
K. Vivekanandarajah, T. Srikanthan, S. Bhattacharyya
The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily attributed to the high energy consumption of fetch and decode circuitry, pursuant to the high instruction issue rate required of these high performance processors. Predictive decode filter cache (DFC) has been shown to be effective in reducing the fetch and decode energy consumed by the instruction cache hierarchy of inorder single issue processors. We propose the architectural level enhancements to facilitate the incorporation of the DFC in wide issue superscalar processors for an energy efficient memory hierarchy. Extensive simulations on the modified superscalar architecture shows that the use of the (predictor based) DFC results in an average reduction of 17.33% and 25.09% fetch energy reduction in LI cache along with 37.2% and 46.6% reduction in number of decodes for 64 and 128 instruction DFC respectively. This fetch and decode energy savings are achieved with minimal reduction in the average instruction per cycle (IPC) of 0.54% and 0.73% for 64 and 128 instruction DFC for the selected set of spec2000 benchmarks.
{"title":"Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures","authors":"K. Vivekanandarajah, T. Srikanthan, S. Bhattacharyya","doi":"10.1109/ASPDAC.2004.1337602","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337602","url":null,"abstract":"The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily attributed to the high energy consumption of fetch and decode circuitry, pursuant to the high instruction issue rate required of these high performance processors. Predictive decode filter cache (DFC) has been shown to be effective in reducing the fetch and decode energy consumed by the instruction cache hierarchy of inorder single issue processors. We propose the architectural level enhancements to facilitate the incorporation of the DFC in wide issue superscalar processors for an energy efficient memory hierarchy. Extensive simulations on the modified superscalar architecture shows that the use of the (predictor based) DFC results in an average reduction of 17.33% and 25.09% fetch energy reduction in LI cache along with 37.2% and 46.6% reduction in number of decodes for 64 and 128 instruction DFC respectively. This fetch and decode energy savings are achieved with minimal reduction in the average instruction per cycle (IPC) of 0.54% and 0.73% for 64 and 128 instruction DFC for the selected set of spec2000 benchmarks.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130454383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337643
J. Ohta, T. Furumiya, D. C. Ng, A. Uehara, K. Kagawa, T. Tokuda, M. Nunoshita
This paper describes a retinal prosthetic device using a pulse frequency modulation (PFM) based photosensor with a standard CMOS technology and its modification to stimulate retinal cells effectively. A 32x32-pixel PFM photosensor array chip have been fabricated using 0.6 μm CMOS technology and demonstrated the improved functions.
{"title":"A retinal prosthetic device using a pulse-frequency-modulation CMOS image sensor","authors":"J. Ohta, T. Furumiya, D. C. Ng, A. Uehara, K. Kagawa, T. Tokuda, M. Nunoshita","doi":"10.1109/ASPDAC.2004.1337643","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337643","url":null,"abstract":"This paper describes a retinal prosthetic device using a pulse frequency modulation (PFM) based photosensor with a standard CMOS technology and its modification to stimulate retinal cells effectively. A 32x32-pixel PFM photosensor array chip have been fabricated using 0.6 μm CMOS technology and demonstrated the improved functions.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132116571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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