We employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols, we propose a FSM model, which can help to extract the necessary properties systematically and verify the data part of a bus transfer efficiently. To demonstrate our methodology, we illustrate two OCB protocols, WISHBONE and AMBA AHB, as the study cases. The experimental results show that we can verify the OCB protocols efficiently and detect the design errors when tests fail.
{"title":"On compliance test of on-chip bus for SOC","authors":"Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou","doi":"10.1109/ASPDAC.2004.1337590","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337590","url":null,"abstract":"We employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols, we propose a FSM model, which can help to extract the necessary properties systematically and verify the data part of a bus transfer efficiently. To demonstrate our methodology, we illustrate two OCB protocols, WISHBONE and AMBA AHB, as the study cases. The experimental results show that we can verify the OCB protocols efficiently and detect the design errors when tests fail.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116708908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337685
R. Zhan, H. Feng, Qiong Wu, X. Guan, Guang Chen, Haolu Xie, Albert Z. H. Wang
On-chip ESD (electrostatic discharging) protection is a challenging IC design problem New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification, which has been used to develop the first intelligent CAD tool of such kind. Design examples in 0.35μm BiCMOS are presented.
{"title":"Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification","authors":"R. Zhan, H. Feng, Qiong Wu, X. Guan, Guang Chen, Haolu Xie, Albert Z. H. Wang","doi":"10.1109/ASPDAC.2004.1337685","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337685","url":null,"abstract":"On-chip ESD (electrostatic discharging) protection is a challenging IC design problem New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification, which has been used to develop the first intelligent CAD tool of such kind. Design examples in 0.35μm BiCMOS are presented.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116101952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337707
Hojun Shim, N. Chang, Massoud Pedram
Despite the limited power available in a batteryoperated hand-held device, a display system must still have an enough resolution and sufficient color depth to deliver the necessary information. We introduce some methodologies for frame buffer compression that efficiently reduce the power consumption of display systems and thus distinctly extend battery life for hand-held applications. Our algorithm is based on a run-length encoding for on-the-fly compression, with a negligible burden in resources and time. We present an adaptive and incremental re-compression technique to maintain efficiency under frequent partial frame buffer updates. We save about 30% to 90% frame buffer activity on average for various hand-held applications. We have implemented an LCD controller with frame buffer compression occupying 1,026 slices and 960 flip-flops in a Xilinx Sprantan-I1 FPGA, which has an equivalent gate count of 65,000 gates. It consumes 30mW more power and 10% additional silicon space than an LCD controller without frame buffer compression, but reduces the power consumption of the frame buffer memory by 400mW.
{"title":"A compressed frame buffer to reduce display power consumption in mobile systems","authors":"Hojun Shim, N. Chang, Massoud Pedram","doi":"10.1109/ASPDAC.2004.1337707","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337707","url":null,"abstract":"Despite the limited power available in a batteryoperated hand-held device, a display system must still have an enough resolution and sufficient color depth to deliver the necessary information. We introduce some methodologies for frame buffer compression that efficiently reduce the power consumption of display systems and thus distinctly extend battery life for hand-held applications. Our algorithm is based on a run-length encoding for on-the-fly compression, with a negligible burden in resources and time. We present an adaptive and incremental re-compression technique to maintain efficiency under frequent partial frame buffer updates. We save about 30% to 90% frame buffer activity on average for various hand-held applications. We have implemented an LCD controller with frame buffer compression occupying 1,026 slices and 960 flip-flops in a Xilinx Sprantan-I1 FPGA, which has an equivalent gate count of 65,000 gates. It consumes 30mW more power and 10% additional silicon space than an LCD controller without frame buffer compression, but reduces the power consumption of the frame buffer memory by 400mW.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115460704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337691
Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, H. Onodera
We propose a heterogeneous processor architecture and its design methodology to shonen the design period of the SOC. It enables fast implementation of a system LSI including an embedded CPU and peripheral functional blocks. Each functional block of the system under design is implemented to a customized processor, instead of a peripheral hardwired logic. We customize processors by deleting unneccesarry funclionalities, without adding new features. This eables rapid and bug-free design. Although area, power and performance of the proposed architecture are a little bit inferior to those of hardwired logics, the design period of the processor is considerably minimized. since the ROM pattern (software) and the layout pattern (customized processor, i.e. hardware) can be independently designed in parallel.
{"title":"An SoC architecture and its design methodology using unifunctional heterogeneous processor array","authors":"Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, H. Onodera","doi":"10.1109/ASPDAC.2004.1337691","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337691","url":null,"abstract":"We propose a heterogeneous processor architecture and its design methodology to shonen the design period of the SOC. It enables fast implementation of a system LSI including an embedded CPU and peripheral functional blocks. Each functional block of the system under design is implemented to a customized processor, instead of a peripheral hardwired logic. We customize processors by deleting unneccesarry funclionalities, without adding new features. This eables rapid and bug-free design. Although area, power and performance of the proposed architecture are a little bit inferior to those of hardwired logics, the design period of the processor is considerably minimized. since the ROM pattern (software) and the layout pattern (customized processor, i.e. hardware) can be independently designed in parallel.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123409619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337533
Ning Fu, S. Nakatake, Y. Takashima, Y. Kajitani
We aim at developing floorplan method, a key in topdown design of system LSIs, and provide floorplan abstraction available in high level design. We introduce pillar blocks to represent a frame of a chip layout and propose how to evaluate the chip before the floorplanning with physical dimension. The frame by the pillar blocks is employed as constraints in optimizing block placement. The experiments to MCNC benchmarks showed that the abstraction is faithful to the physically optimized block placement with respect to the chip area and the wire-length.
{"title":"Abstraction and optimization of consistent floorplanning with pillar block constraints","authors":"Ning Fu, S. Nakatake, Y. Takashima, Y. Kajitani","doi":"10.1109/ASPDAC.2004.1337533","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337533","url":null,"abstract":"We aim at developing floorplan method, a key in topdown design of system LSIs, and provide floorplan abstraction available in high level design. We introduce pillar blocks to represent a frame of a chip layout and propose how to evaluate the chip before the floorplanning with physical dimension. The frame by the pillar blocks is employed as constraints in optimizing block placement. The experiments to MCNC benchmarks showed that the abstraction is faithful to the physically optimized block placement with respect to the chip area and the wire-length.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337706
Lukai Cai, Haobo Yu, D. Gajski
It is predicted that 70% of the chip area will he occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cost, performance and energy consumption. This paper proposes a novel memory size model for algorithms which map the variables of a system behavior to memories of a system architecture. To our knowledge, it is the first memory estimation approach that analyzes the variable lifetime for the system behavior, which consists of hierarchically-modelled and concurrently-executed processes and contains variables with different sizes. Experimental results show that significant improvements can be achieved.
{"title":"A novel memory size model for variable-mapping in system level design","authors":"Lukai Cai, Haobo Yu, D. Gajski","doi":"10.1109/ASPDAC.2004.1337706","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337706","url":null,"abstract":"It is predicted that 70% of the chip area will he occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cost, performance and energy consumption. This paper proposes a novel memory size model for algorithms which map the variables of a system behavior to memories of a system architecture. To our knowledge, it is the first memory estimation approach that analyzes the variable lifetime for the system behavior, which consists of hierarchically-modelled and concurrently-executed processes and contains variables with different sizes. Experimental results show that significant improvements can be achieved.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124221257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a functional-space decomposition approach to enhance the capability of symbolic simulation. In our symbolic simulator, the control part and datapath of a circuit is separated, and their simulated results are recorded in different domains. A 2-tuple list structure is used to separate the results in the control and datapath domains. Then, the functional sub-space in the control domain can further be decomposed in order to achieve the optimal OBDD size and run time. We demonstrate the effectiveness of our decomposition approach based on symbolic simulation of arithmetic circuit units.
{"title":"Improved symbolic simulation by functional-space decomposition","authors":"Tao Feng, Li-C. Wang, K. Cheng","doi":"10.5555/1015090.1015263","DOIUrl":"https://doi.org/10.5555/1015090.1015263","url":null,"abstract":"This paper presents a functional-space decomposition approach to enhance the capability of symbolic simulation. In our symbolic simulator, the control part and datapath of a circuit is separated, and their simulated results are recorded in different domains. A 2-tuple list structure is used to separate the results in the control and datapath domains. Then, the functional sub-space in the control domain can further be decomposed in order to achieve the optimal OBDD size and run time. We demonstrate the effectiveness of our decomposition approach based on symbolic simulation of arithmetic circuit units.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128212695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337574
Robertas Damaševičius, V. Stuikys
We address a problem of reusing and customizing soft IP components by introducing a concept of design process-a series of common, well-defined and well-proven domain-specific actions and methods performed to achieve a certain design aim. We especially examine system-level design processes that are aimed at designing a hardware system by integrating soft IPs at a high level of abstraction. We combine this concept with object-oriented hardware design using UML and metaprogramming paradigm for describing generation of domain code.
{"title":"Application of UML for hardware design based on design process model","authors":"Robertas Damaševičius, V. Stuikys","doi":"10.1109/ASPDAC.2004.1337574","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337574","url":null,"abstract":"We address a problem of reusing and customizing soft IP components by introducing a concept of design process-a series of common, well-defined and well-proven domain-specific actions and methods performed to achieve a certain design aim. We especially examine system-level design processes that are aimed at designing a hardware system by integrating soft IPs at a high level of abstraction. We combine this concept with object-oriented hardware design using UML and metaprogramming paradigm for describing generation of domain code.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128534575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337568
O. Sinanoglu, A. Orailoglu
Increasing IC densities necessitate diagnosis methodologies with enhanced defect locating capabilities. Yet the computational effort expended in extracting diagnostic information and the stringent storage requirements constitute major concerns due to the tremendous number of faults in typical ICs. We propose an RT-level diagnosis methodology capable of responding to these challenges. In the proposed scheme, diagnostic information is computed on a grouped fault effect basis, enhancing both the storage and the computational aspects. The fault effect grouping criteria are identified based on a module structure analysis, improving the propagation ability of the diagnostic information through RT modules. Experimental results show that the proposed methodology provides superior speed-ups and significant diagnostic information compression at no sacrifice in diagnostic resolution, compared to the existing gate-level diagnosis approaches.
{"title":"Efficient RT-level fault diagnosis methodology","authors":"O. Sinanoglu, A. Orailoglu","doi":"10.1109/ASPDAC.2004.1337568","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337568","url":null,"abstract":"Increasing IC densities necessitate diagnosis methodologies with enhanced defect locating capabilities. Yet the computational effort expended in extracting diagnostic information and the stringent storage requirements constitute major concerns due to the tremendous number of faults in typical ICs. We propose an RT-level diagnosis methodology capable of responding to these challenges. In the proposed scheme, diagnostic information is computed on a grouped fault effect basis, enhancing both the storage and the computational aspects. The fault effect grouping criteria are identified based on a module structure analysis, improving the propagation ability of the diagnostic information through RT modules. Experimental results show that the proposed methodology provides superior speed-ups and significant diagnostic information compression at no sacrifice in diagnostic resolution, compared to the existing gate-level diagnosis approaches.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128693231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337639
Y. Utsurogi, M. Haruoka, T. Matsuoka, K. Taniguchi
A dual-band image-reject mixer is designed for a GPS L1/L2 dual-band receiver with an extension of the conventional Weaver architecture. The quadrature mixer with phase ermr compensation capability in the quadrature LO signal without calibration and tuning is reported. The measurement of the dual-hand image-reject mixer demonstrated 64dB image reject ratio (IMRR).
{"title":"A dual-band image-reject mixer for GPS with 64dB image rejection","authors":"Y. Utsurogi, M. Haruoka, T. Matsuoka, K. Taniguchi","doi":"10.1109/ASPDAC.2004.1337639","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337639","url":null,"abstract":"A dual-band image-reject mixer is designed for a GPS L1/L2 dual-band receiver with an extension of the conventional Weaver architecture. The quadrature mixer with phase ermr compensation capability in the quadrature LO signal without calibration and tuning is reported. The measurement of the dual-hand image-reject mixer demonstrated 64dB image reject ratio (IMRR).","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128695828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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