Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738965
Jidan Al-Eryani, H. Knapp, J. Wursthorn, K. Aufinger, S. Majied, Hao Li, S. Boguth, R. Lachner, J. Bock, L. Maurer
A 3-stage power amplifier (PA) with 14dBm saturated output power (Psat), 29.5 dB small-signal gain, and 4.8% power-added efficiency (PAE) at a frequency of 162GHz is presented. From 155 to 165 GHz, Psat remains higher than 12.5 dBm, while the small-signal gain varies from 35.4 dB to 28.3 dB. Maximum output power and gain performance are obtained by using a differential cascode topology and operating the transistors well beyond their open-base collector-emitter breakdown voltage (BVCEO), and by optimum matching of the three stages of the PA. To our best knowledge, this is the highest reported output power for a sillicon-based PA beyond 150 GHz. The chip is fabricated in a 130nm SiGe BiCMOS technology with fT/fmax = 250/370 GHz.
{"title":"A 162 GHz power amplifier with 14 dBm output power","authors":"Jidan Al-Eryani, H. Knapp, J. Wursthorn, K. Aufinger, S. Majied, Hao Li, S. Boguth, R. Lachner, J. Bock, L. Maurer","doi":"10.1109/BCTM.2016.7738965","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738965","url":null,"abstract":"A 3-stage power amplifier (PA) with 14dBm saturated output power (Psat), 29.5 dB small-signal gain, and 4.8% power-added efficiency (PAE) at a frequency of 162GHz is presented. From 155 to 165 GHz, Psat remains higher than 12.5 dBm, while the small-signal gain varies from 35.4 dB to 28.3 dB. Maximum output power and gain performance are obtained by using a differential cascode topology and operating the transistors well beyond their open-base collector-emitter breakdown voltage (BVCEO), and by optimum matching of the three stages of the PA. To our best knowledge, this is the highest reported output power for a sillicon-based PA beyond 150 GHz. The chip is fabricated in a 130nm SiGe BiCMOS technology with fT/fmax = 250/370 GHz.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126443723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738964
Shon Yadav, A. Chakravorty, M. Schroter
The state-of-the-art and π-models for the lateral non-quasi-static (NQS) effect are analyzed. The superiority of the π-model to capture the lateral NQS effect is demonstrated through small-signal simulations of both the models, implemented in Verilog-A. A hybrid model is proposed and a corresponding formulation of the base impedance is obtained. The equation gives the base impedance of the state-of-the-art as well as the π-model under appropriate conditions. The methodology to implement the hybrid model in Verilog-A is discussed. The hybrid model shows significantly higher accuracy than both the state-of-the-art model and the π-model when compared with the device simulation data.
{"title":"Hybrid small-signal π-model for the lateral NQS effect in SiGe HBTs","authors":"Shon Yadav, A. Chakravorty, M. Schroter","doi":"10.1109/BCTM.2016.7738964","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738964","url":null,"abstract":"The state-of-the-art and π-models for the lateral non-quasi-static (NQS) effect are analyzed. The superiority of the π-model to capture the lateral NQS effect is demonstrated through small-signal simulations of both the models, implemented in Verilog-A. A hybrid model is proposed and a corresponding formulation of the base impedance is obtained. The equation gives the base impedance of the state-of-the-art as well as the π-model under appropriate conditions. The methodology to implement the hybrid model in Verilog-A is discussed. The hybrid model shows significantly higher accuracy than both the state-of-the-art model and the π-model when compared with the device simulation data.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114487904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738955
V. T. Vu, D. Céli, T. Zimmer, S. Frégonèse, P. Chevalier
This paper presents a novel Fully Self-Aligned (FSA) Si/SiGe HBT architecture using Selective Epitaxial Growth (SEG) and featuring an Epitaxial eXtrinsic Base Isolated from the Collector (EXBIC). The one is integrated into the bulk area of the 28-nm FD-SOI CMOS technology developed at STMicroelectronics. All the parameters of the architecture such as the boron-doped base link, the emitter width and height, the pedestal oxide and sidewall thicknesses are evaluated by TCAD simulation. A low base-collector capacitance, independent from the extrinsic base doping is obtained. Optimized architecture exhibits 420 GHz fT and 780 GHz fMAX.
{"title":"Advanced Si/SiGe HBT architecture for 28-nm FD-SOI BiCMOS","authors":"V. T. Vu, D. Céli, T. Zimmer, S. Frégonèse, P. Chevalier","doi":"10.1109/BCTM.2016.7738955","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738955","url":null,"abstract":"This paper presents a novel Fully Self-Aligned (FSA) Si/SiGe HBT architecture using Selective Epitaxial Growth (SEG) and featuring an Epitaxial eXtrinsic Base Isolated from the Collector (EXBIC). The one is integrated into the bulk area of the 28-nm FD-SOI CMOS technology developed at STMicroelectronics. All the parameters of the architecture such as the boron-doped base link, the emitter width and height, the pedestal oxide and sidewall thicknesses are evaluated by TCAD simulation. A low base-collector capacitance, independent from the extrinsic base doping is obtained. Optimized architecture exhibits 420 GHz fT and 780 GHz fMAX.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"143-147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130634287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738946
J. Babcock, Joel Halbert, H. Yasuda, A. Sadovnikov, Jonggook Kim, A. Buchholz, Robert Malone, M. Corsi, G. Cestra, M. Dahlstrom
The evolution of silicon and silicon-germanium pnp transistors is reviewed in this paper. The motivation for SiGe-pnp transistors in Complementary Bipolar (CBi) and CBiCMOS is discussed with a view on device parametric parameters that help gage the usefulness of these devices in analog and RF design. We review the basic process architectures and process building blocks for CBiCMOS. SiGe-pnp versus Si-pnp performance metrics are highlighted followed by a discussion on circuit blocks that benefit from having near matched complementary bipolar transistors.
{"title":"Advantages of SiGe-pnp over Si-pnp for analog and RF enhanced CBiCMOS and Complementary Bipolar design usage","authors":"J. Babcock, Joel Halbert, H. Yasuda, A. Sadovnikov, Jonggook Kim, A. Buchholz, Robert Malone, M. Corsi, G. Cestra, M. Dahlstrom","doi":"10.1109/BCTM.2016.7738946","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738946","url":null,"abstract":"The evolution of silicon and silicon-germanium pnp transistors is reviewed in this paper. The motivation for SiGe-pnp transistors in Complementary Bipolar (CBi) and CBiCMOS is discussed with a view on device parametric parameters that help gage the usefulness of these devices in analog and RF design. We review the basic process architectures and process building blocks for CBiCMOS. SiGe-pnp versus Si-pnp performance metrics are highlighted followed by a discussion on circuit blocks that benefit from having near matched complementary bipolar transistors.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115135767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738951
V. Trivedi, J. John, J. Young, T. Dao, D. Morgan, I. To, R. Ma, D. Hammock, S. Mehrotra, L. Radic, B. Grote, T. Roggenbauer, J. Kirchgessner
A 90nm BiCMOS technology with a SiGe:C HBT having fMAX >400GHz is presented. Both lateral and vertical scaling of the SiGe bipolar transistor are described, enabling SiGe HBT performance metrics fT/fMAX of ~230GHz/400GHz to be achieved with a minimum gate delay of <;3ps. A medium breakdown device is also integrated, achieving an fT*BVCEO product of 310GHz*V. CMOS implant and HBT process optimizations to address the additional thermal budget of the HBT module are also discussed. In concert with high-quality passives, this technology is especially suited for millimeter wave applications with high digital gate density requirements.
{"title":"A 90nm BiCMOS technology featuring 400GHz fMAX SiGe:C HBT","authors":"V. Trivedi, J. John, J. Young, T. Dao, D. Morgan, I. To, R. Ma, D. Hammock, S. Mehrotra, L. Radic, B. Grote, T. Roggenbauer, J. Kirchgessner","doi":"10.1109/BCTM.2016.7738951","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738951","url":null,"abstract":"A 90nm BiCMOS technology with a SiGe:C HBT having fMAX >400GHz is presented. Both lateral and vertical scaling of the SiGe bipolar transistor are described, enabling SiGe HBT performance metrics fT/fMAX of ~230GHz/400GHz to be achieved with a minimum gate delay of <;3ps. A medium breakdown device is also integrated, achieving an fT*BVCEO product of 310GHz*V. CMOS implant and HBT process optimizations to address the additional thermal budget of the HBT module are also discussed. In concert with high-quality passives, this technology is especially suited for millimeter wave applications with high digital gate density requirements.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738950
Sri Navaneeth Easwaran, Sunil K. Venugopal, R. Weigel
A new technique for limiting the surge current during short to battery in the unpowered state of low side driver is presented. This technique does not affect the main current regulation behavior in the powered state. The energy is limited to 28 micron Joules in the unpowered state and regulates the current to 3A in the powered state of the driver.
{"title":"Current regulator with energy limitation in the unpowered state featuring bipolar discharge path","authors":"Sri Navaneeth Easwaran, Sunil K. Venugopal, R. Weigel","doi":"10.1109/BCTM.2016.7738950","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738950","url":null,"abstract":"A new technique for limiting the surge current during short to battery in the unpowered state of low side driver is presented. This technique does not affect the main current regulation behavior in the powered state. The energy is limited to 28 micron Joules in the unpowered state and regulates the current to 3A in the powered state of the driver.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131112210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738943
Takeji Fujibayashi, Y. Takeda, Weihu Wang, Yi-Shin Yeh, Willem Stapelbroek, S. Takeuchi, B. Floyd
This paper presents a flip-chip packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS technology for both long-range and short-range automotive radar applications. The single chip contains a two-channel transmitter with +18-dBm saturated output power per channel; an LO chain with ×4 multiplier, wide-band 20-GHz VCO with -100-dBc/Hz phase noise at 1-MHz offset referenced to a 77-GHz carrier, and divide-by-four prescaler; and a six-channel receiver with 10- to 11-dB noise figure, 14- to 15-dB conversion gain and +1-dBm input P1dB in unpackaged condition. The interconnect loss through the BGA package at 80 GHz is 1.5 to 2 dB. Built-in self-test (BIST) circuits are integrated to enable RF output power, receiver gain, relative channel-to-channel phase and internal temperature measurement.
{"title":"A 76- to 81-GHz packaged single-chip transceiver for automotive radar","authors":"Takeji Fujibayashi, Y. Takeda, Weihu Wang, Yi-Shin Yeh, Willem Stapelbroek, S. Takeuchi, B. Floyd","doi":"10.1109/BCTM.2016.7738943","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738943","url":null,"abstract":"This paper presents a flip-chip packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS technology for both long-range and short-range automotive radar applications. The single chip contains a two-channel transmitter with +18-dBm saturated output power per channel; an LO chain with ×4 multiplier, wide-band 20-GHz VCO with -100-dBc/Hz phase noise at 1-MHz offset referenced to a 77-GHz carrier, and divide-by-four prescaler; and a six-channel receiver with 10- to 11-dB noise figure, 14- to 15-dB conversion gain and +1-dBm input P1dB in unpackaged condition. The interconnect loss through the BGA package at 80 GHz is 1.5 to 2 dB. Built-in self-test (BIST) circuits are integrated to enable RF output power, receiver gain, relative channel-to-channel phase and internal temperature measurement.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123371736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738941
Xuan Guo, Danyu Wu, Lei Zhou, Huasen Liu, Jin Wu, Xinyu Liu
A 32-bit direct digital frequency synthesizer with a maximum operating frequency of 4.5 GHz fabricated in 0.25 μm SiGe HBT is presented. The phase-to-amplitude mapping circuit is implemented with nonlinear DAC coarse quantization and ROM-based piecewise linear interpolation. The measured SFDR is between 46 dBc and 60 dBc under a 4.0 GHz clock and the hopping time is less than 10 ns. This chip occupies 5.25 mm2 including bond pads and dissipates 3.46 W with a 4.0 V digital supply and 4.0V analog supply. The proposed DDFS demonstrates excellent performance achieving a FOM of 234.9 GHz · 2(SFDR/6)/W.
{"title":"A 4-GHz 32-bit direct digital frequency synthesizer in 0.25 µm SiGe HBT with SFDR > 46 dBc up to Nyquist bandwidth","authors":"Xuan Guo, Danyu Wu, Lei Zhou, Huasen Liu, Jin Wu, Xinyu Liu","doi":"10.1109/BCTM.2016.7738941","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738941","url":null,"abstract":"A 32-bit direct digital frequency synthesizer with a maximum operating frequency of 4.5 GHz fabricated in 0.25 μm SiGe HBT is presented. The phase-to-amplitude mapping circuit is implemented with nonlinear DAC coarse quantization and ROM-based piecewise linear interpolation. The measured SFDR is between 46 dBc and 60 dBc under a 4.0 GHz clock and the hopping time is less than 10 ns. This chip occupies 5.25 mm2 including bond pads and dissipates 3.46 W with a 4.0 V digital supply and 4.0V analog supply. The proposed DDFS demonstrates excellent performance achieving a FOM of 234.9 GHz · 2(SFDR/6)/W.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125331022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738957
Guido Belfiore, R. Henker, F. Ellinger
In this paper the design of a VCSEL driver with strong equalization is presented. Unlike other published works the pre-emphasis provided from the proposed driver and the output voltage swing are independently tunable up to the saturation of the output stage (~700 mVpp in 50 Ω load environment). The driver is designed in 130 nm SiGe BiCMOS technology. Thanks to the various bandwidth extension techniques, the electrical data-rate at which the driver can operate is higher than 50 Gbit/s. A wide open optical eye diagram is measured at 48 Gbit/s with a 20 GHz VCSEL. The driver and the VCSEL consume only 188 mW from a dual voltage supply of 2.5 and 3.4 V. To the best of the authors knowledge 3.9 mW/(Gbit/s) is the highest reported energy-efficiency for a common-cathode VCSEL driver with data-rate higher than 40 Gbit/s. Moreover an open eye at 48 Gbit/s is the fastest reported for a common cathode VCSEL driver without pre-emphasis in the receiver.
{"title":"The effect of strong equalization in high-speed VCSEL-based optical communications up to 48 Gbit/s","authors":"Guido Belfiore, R. Henker, F. Ellinger","doi":"10.1109/BCTM.2016.7738957","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738957","url":null,"abstract":"In this paper the design of a VCSEL driver with strong equalization is presented. Unlike other published works the pre-emphasis provided from the proposed driver and the output voltage swing are independently tunable up to the saturation of the output stage (~700 mVpp in 50 Ω load environment). The driver is designed in 130 nm SiGe BiCMOS technology. Thanks to the various bandwidth extension techniques, the electrical data-rate at which the driver can operate is higher than 50 Gbit/s. A wide open optical eye diagram is measured at 48 Gbit/s with a 20 GHz VCSEL. The driver and the VCSEL consume only 188 mW from a dual voltage supply of 2.5 and 3.4 V. To the best of the authors knowledge 3.9 mW/(Gbit/s) is the highest reported energy-efficiency for a common-cathode VCSEL driver with data-rate higher than 40 Gbit/s. Moreover an open eye at 48 Gbit/s is the fastest reported for a common cathode VCSEL driver without pre-emphasis in the receiver.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114358981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738963
M. Koričić, J. Žilak, T. Suligoj
Breakdown behavior of double-emitter reduced-surface-field horizontal current bipolar transistor is extensively analyzed by measurements and 3D device simulations. By the addition of the 2nd drift region, BVCEO of double-emitter structure is improved from 12 V up to 36 V and can be tuned by the length of the drift region. By increasing the length of the drift region, positive feedback loop of the common-emitter soft-breakdown can be completely broken making the BVCEO independent on transistor current gain. Transistors with BVCEO and BVCBO equal to the collector-substrate breakdown voltage are demonstrated. We also report that base current reversal in forced-VBE measurement does not occur and cannot be used for accurate determination of BVCEO of analyzed structures.
{"title":"Investigation of double-emitter reduced-surface-field horizontal current bipolar transistor breakdown mechanisms","authors":"M. Koričić, J. Žilak, T. Suligoj","doi":"10.1109/BCTM.2016.7738963","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738963","url":null,"abstract":"Breakdown behavior of double-emitter reduced-surface-field horizontal current bipolar transistor is extensively analyzed by measurements and 3D device simulations. By the addition of the 2nd drift region, BVCEO of double-emitter structure is improved from 12 V up to 36 V and can be tuned by the length of the drift region. By increasing the length of the drift region, positive feedback loop of the common-emitter soft-breakdown can be completely broken making the BVCEO independent on transistor current gain. Transistors with BVCEO and BVCBO equal to the collector-substrate breakdown voltage are demonstrated. We also report that base current reversal in forced-VBE measurement does not occur and cannot be used for accurate determination of BVCEO of analyzed structures.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131660942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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