Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738961
Moon-Kyu Cho, I. Song, Zachary E. Fleetwood, J. Cressler
A 6-bit active bi-directional silicon-germanium (SiGe) digital step attenuator (DSA) with multi-octave bandwidth using an active double-pole double-throw (DPDT) switch is demonstrated. To compensate the insertion loss (IL) and frequency dependent loss characteristics of conventional passive attenuators without using any additional amplifier and equalizer, the proposed attenuator employs active DPDT switches, which provide 4-way switching and bi-directional operation. The measured gain is 7.0-9.6 dB and the input and output return loss is better than 9 dB for 2-20 GHz. The measured root mean square (RMS) amplitude and phase errors in the major state are less than 0.4 dB and 3.0 degree, respectively. The chip size is 1.43 × 1.23 mm2, including pads. The proposed active bi-directional DSA consumes 30 mA from a 2.5 V supply.
{"title":"Wideband active bi-directional SiGe digital step attenuator using an active DPDT switch","authors":"Moon-Kyu Cho, I. Song, Zachary E. Fleetwood, J. Cressler","doi":"10.1109/BCTM.2016.7738961","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738961","url":null,"abstract":"A 6-bit active bi-directional silicon-germanium (SiGe) digital step attenuator (DSA) with multi-octave bandwidth using an active double-pole double-throw (DPDT) switch is demonstrated. To compensate the insertion loss (IL) and frequency dependent loss characteristics of conventional passive attenuators without using any additional amplifier and equalizer, the proposed attenuator employs active DPDT switches, which provide 4-way switching and bi-directional operation. The measured gain is 7.0-9.6 dB and the input and output return loss is better than 9 dB for 2-20 GHz. The measured root mean square (RMS) amplitude and phase errors in the major state are less than 0.4 dB and 3.0 degree, respectively. The chip size is 1.43 × 1.23 mm2, including pads. The proposed active bi-directional DSA consumes 30 mA from a 2.5 V supply.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116045209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738968
Danyu Wu, Lei Zhou, Yinkun Huang, Peng Wang, Jin Wu, Zhi Jin, Xinyu Liu
In this paper, a time-interleaved 30GS/s 6bit ADC fabricated in 0.18μm SiGe BiCMOS technology has been demonstrated. A bandwidth boosting technique and packaging solution has been proposed which enables the ADC to achieve input bandwidth over 18GHz. A full data rate interface is integrated to transmit all the data in real time. The ADC has a SFDR >35dBc over the entire Nyquist frequency. An effective number of bits (ENOB) above 5.0 are achieved for low frequency input tones, dropping to 3.5 at 16GHz.
{"title":"A 30GS/s 6bit SiGe ADC with input bandwidth over 18GHz and full data rate interface","authors":"Danyu Wu, Lei Zhou, Yinkun Huang, Peng Wang, Jin Wu, Zhi Jin, Xinyu Liu","doi":"10.1109/BCTM.2016.7738968","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738968","url":null,"abstract":"In this paper, a time-interleaved 30GS/s 6bit ADC fabricated in 0.18μm SiGe BiCMOS technology has been demonstrated. A bandwidth boosting technique and packaging solution has been proposed which enables the ADC to achieve input bandwidth over 18GHz. A full data rate interface is integrated to transmit all the data in real time. The ADC has a SFDR >35dBc over the entire Nyquist frequency. An effective number of bits (ENOB) above 5.0 are achieved for low frequency input tones, dropping to 3.5 at 16GHz.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132366322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738975
J. Buckwalter
Millimeter-wave systems require circuit innovations that enable high efficiency with complex waveforms. Injection locking circuit techniques are presented that enable low-power outphasing modulation and phase shifting for millimeter-wave radio transmitters integrated in highly-scaled Silicon CMOS and BiCMOS technologies. This paper reviews the efficiency penalties for operating arrays under back-off conditions to compare the advantages of transmit architectures at mm-wave bands. A microwave injection locking outphasing modulator is described to realize wideband, high-efficiency operation confronting these array architectures. An injection-locked outphasing modulator circuit is implemented in 45-nm SOI CMOS and exhibits 22.7% overall system efficiency with 64-QAM at 2.1% EVM. Injection locking techniques for phase shifters are demonstrated to offer high phase and low amplitude variation in a 90-nm SiGe BiCMOS 2 × 2 transmit/receiver phased array at 71-86 GHz.
{"title":"Injection locking circuit techniques for high-efficiency millimeter-wave transmitter arrays in SiGe and CMOS SOI processes","authors":"J. Buckwalter","doi":"10.1109/BCTM.2016.7738975","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738975","url":null,"abstract":"Millimeter-wave systems require circuit innovations that enable high efficiency with complex waveforms. Injection locking circuit techniques are presented that enable low-power outphasing modulation and phase shifting for millimeter-wave radio transmitters integrated in highly-scaled Silicon CMOS and BiCMOS technologies. This paper reviews the efficiency penalties for operating arrays under back-off conditions to compare the advantages of transmit architectures at mm-wave bands. A microwave injection locking outphasing modulator is described to realize wideband, high-efficiency operation confronting these array architectures. An injection-locked outphasing modulator circuit is implemented in 45-nm SOI CMOS and exhibits 22.7% overall system efficiency with 64-QAM at 2.1% EVM. Injection locking techniques for phase shifters are demonstrated to offer high phase and low amplitude variation in a 90-nm SiGe BiCMOS 2 × 2 transmit/receiver phased array at 71-86 GHz.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133959243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738972
J. Cressler
SiGe HBT technology has enjoyed substantial success over the past 25 years for use in realizing performance-constrained, highly-integrated mixed-signal electronics spanning the range of DC to sub-mm-wave operational frequencies. This success has been bolstered by advances in device scaling which have been truly impressive, now routinely achieving multi-hundred GHz frequencies, a fact which is currently opening many new and interesting application possibilities. Most of these emerging opportunities were never envisioned at the very beginning of this field (which is reflective of the inherent nature of innovation), and many involve using the SiGe HBT in ways which may appear counterintuitive to “classical” circuit designers. Examples include operation: in radiation environments, in inverse mode, in weak saturation, and beyond SoA boundaries. This invited paper will explore this emerging design space, both from device and circuit perspectives.
{"title":"Beyond the boundaries: Enabling new circuit opportunities by using SiGe HBTs in counterintuitive ways","authors":"J. Cressler","doi":"10.1109/BCTM.2016.7738972","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738972","url":null,"abstract":"SiGe HBT technology has enjoyed substantial success over the past 25 years for use in realizing performance-constrained, highly-integrated mixed-signal electronics spanning the range of DC to sub-mm-wave operational frequencies. This success has been bolstered by advances in device scaling which have been truly impressive, now routinely achieving multi-hundred GHz frequencies, a fact which is currently opening many new and interesting application possibilities. Most of these emerging opportunities were never envisioned at the very beginning of this field (which is reflective of the inherent nature of innovation), and many involve using the SiGe HBT in ways which may appear counterintuitive to “classical” circuit designers. Examples include operation: in radiation environments, in inverse mode, in weak saturation, and beyond SoA boundaries. This invited paper will explore this emerging design space, both from device and circuit perspectives.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132871074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738949
E. S. Malotaux, M. Spirito
In this paper we present a high sensitivity total power radiometer front-end integrated in a 0.25 μm SiGe BiCMOS technology. The radiometer consists of a two-stage LNA co-integrated with a common-emitter square-law detector. Together these stages provide a peak responsivity of 61 MV/W and a 6 GHz system bandwidth around 56 GHz. An optimized non-50-Ohm impedance interface between the LNA and the detector results in an improved system responsivity and sensitivity. Furthermore, the use of a large area load resistor in the detector results in a sub-300 Hz noise corner. Combining the peak responsivity with the 194 nV/√Hz noise floor at the output results in a minimum NEP of 3.2 fW/√Hz at 300 Hz.
{"title":"A passive total power radiometer in 0.25 µm SiGe BiCMOS for millimeter-wave imaging","authors":"E. S. Malotaux, M. Spirito","doi":"10.1109/BCTM.2016.7738949","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738949","url":null,"abstract":"In this paper we present a high sensitivity total power radiometer front-end integrated in a 0.25 μm SiGe BiCMOS technology. The radiometer consists of a two-stage LNA co-integrated with a common-emitter square-law detector. Together these stages provide a peak responsivity of 61 MV/W and a 6 GHz system bandwidth around 56 GHz. An optimized non-50-Ohm impedance interface between the LNA and the detector results in an improved system responsivity and sensitivity. Furthermore, the use of a large area load resistor in the detector results in a sub-300 Hz noise corner. Combining the peak responsivity with the 194 nV/√Hz noise floor at the output results in a minimum NEP of 3.2 fW/√Hz at 300 Hz.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"66 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738960
I. Lopez, P. Rito, A. Awny, B. Heinemann, D. Kissinger, A. Ulusoy
This paper presents the design and electrical characterization of a transimpedance amplifier (TIA) implemented in a complementary 0.25 μm SiGe:C BiCMOS technology which offers a fT/fmax of 110 GHz/180 GHz for the npn and 95 GHz/140 GHz for the pnp transistor, respectively. Featuring folded cascode architecture by making use of the available pnp HBTs, the amplifier exhibits a differential transimpedance gain of 52.5 dBΩ and a 3 dB bandwidth of 32 GHz with a measured differential average input referred current noise density of 13.1 pA/√Hz, dissipating 70 mW of power. Clear eye diagrams up to 50 Gb/s data rate are reported. To the best of the authors' knowledge, this is the first time pnp transistors are used at such speed, achieving an overall performance comparable to, or better than, other TIA implementations in faster technologies.
{"title":"A 50 Gb/s TIA in 0.25µm SiGe:C BiCMOS in folded cascode architecture with pnp HBTs","authors":"I. Lopez, P. Rito, A. Awny, B. Heinemann, D. Kissinger, A. Ulusoy","doi":"10.1109/BCTM.2016.7738960","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738960","url":null,"abstract":"This paper presents the design and electrical characterization of a transimpedance amplifier (TIA) implemented in a complementary 0.25 μm SiGe:C BiCMOS technology which offers a fT/fmax of 110 GHz/180 GHz for the npn and 95 GHz/140 GHz for the pnp transistor, respectively. Featuring folded cascode architecture by making use of the available pnp HBTs, the amplifier exhibits a differential transimpedance gain of 52.5 dBΩ and a 3 dB bandwidth of 32 GHz with a measured differential average input referred current noise density of 13.1 pA/√Hz, dissipating 70 mW of power. Clear eye diagrams up to 50 Gb/s data rate are reported. To the best of the authors' knowledge, this is the first time pnp transistors are used at such speed, achieving an overall performance comparable to, or better than, other TIA implementations in faster technologies.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126870809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738971
Thé Linh Nguyen, Arash Izadi, Gilles Denoyer
In this paper we will discuss the challenges of circuit design for high-speed and high-volume optical interconnect and how SiGe BiCMOS technologies are best suited to address these challenges. Advantages of SiGe BiCMOS are illustrated through examples of design requirements from optical front-ends (transimpedance amplifier (TIA) and modulator and laser driver) to clock and data recovery (CDR) and serializer and deserializer (SerDes). We will also look ahead to the future and predict product evolution and key requirements of optical interconnects and define the required performance of SiGe BiCMOS technology to address such specifications.
{"title":"SiGe BiCMOS technologies for high-speed and high-volume optical interconnect applications","authors":"Thé Linh Nguyen, Arash Izadi, Gilles Denoyer","doi":"10.1109/BCTM.2016.7738971","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738971","url":null,"abstract":"In this paper we will discuss the challenges of circuit design for high-speed and high-volume optical interconnect and how SiGe BiCMOS technologies are best suited to address these challenges. Advantages of SiGe BiCMOS are illustrated through examples of design requirements from optical front-ends (transimpedance amplifier (TIA) and modulator and laser driver) to clock and data recovery (CDR) and serializer and deserializer (SerDes). We will also look ahead to the future and predict product evolution and key requirements of optical interconnects and define the required performance of SiGe BiCMOS technology to address such specifications.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116772637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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