Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738973
M. Urteaga, A. Carter, Z. Griffith, R. Pierson, J. Bergman, A. Arias, P. Rowell, J. Hacker, B. Brar, M. Rodwell
Through aggressive lithographical and epitaxial scaling, the bandwidths of InP-based heterojunction bipolar transistors have been extended to THz frequencies. At 130nm emitter dimensions, transistors with maximum frequencies of oscillation (fmax) of >1THz have been demonstrated with accompanying circuit demonstrations at 670GHz. At 250nm emitter dimensions, high efficiency and high power density mm-wave power amplifiers covering E-band (71GHz) to G-band (235GHz) have been fabricated. The utility of these high performance transistors can be further enhanced through heterogeneous integration with Si CMOS. We have demonstrated wafer-scale 3D integration of InP and Si using a low temperature oxide-to-oxide bonding process with embedded Cu interconnects.
{"title":"THz bandwidth InP HBT technologies and heterogeneous integration with Si CMOS","authors":"M. Urteaga, A. Carter, Z. Griffith, R. Pierson, J. Bergman, A. Arias, P. Rowell, J. Hacker, B. Brar, M. Rodwell","doi":"10.1109/BCTM.2016.7738973","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738973","url":null,"abstract":"Through aggressive lithographical and epitaxial scaling, the bandwidths of InP-based heterojunction bipolar transistors have been extended to THz frequencies. At 130nm emitter dimensions, transistors with maximum frequencies of oscillation (fmax) of >1THz have been demonstrated with accompanying circuit demonstrations at 670GHz. At 250nm emitter dimensions, high efficiency and high power density mm-wave power amplifiers covering E-band (71GHz) to G-band (235GHz) have been fabricated. The utility of these high performance transistors can be further enhanced through heterogeneous integration with Si CMOS. We have demonstrated wafer-scale 3D integration of InP and Si using a low temperature oxide-to-oxide bonding process with embedded Cu interconnects.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115257053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738959
V. Issakov, M. Wojnowski, H. Knapp, S. Trotta, H. Forstner, K. Pressel, A. Hagelauer
The level of integration for RF and mm-wave systems is continuously increasing. Highly-integrated system on chip solutions have to be encapsulated in a package and assembled on a board. In addition, to be more attractive as a product, the trend goes towards further integration of passives and antennas in a package. This drives the system in package solutions. However, electrical properties of the package and board may have a significant effect on system parameters, especially at high frequencies. Hence, layout features of package and board must be carefully modelled and considered during the design. Furthermore, it is often insufficient to model chip, package and board separately, as some high-frequency effects may not be captured. An example is electromagnetic coupling between integrated coils on chip and routing traces in package. In this paper we describe considerations on co-simulation and co-design of highly-integrated RF systems by means of accurate electromagnetic modelling. We demonstrate the approach and various aspects of chip-package-board co-design based on examples of systems for various applications: 6 GHz VCO using embedded inductor; backhaul communication system in package for V-band and E-band and a four-channel 77 GHz automotive radar transceiver in a package with four dipole antennas.
{"title":"Co-simulation and co-design of chip-package-board interfaces in highly-integrated RF systems","authors":"V. Issakov, M. Wojnowski, H. Knapp, S. Trotta, H. Forstner, K. Pressel, A. Hagelauer","doi":"10.1109/BCTM.2016.7738959","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738959","url":null,"abstract":"The level of integration for RF and mm-wave systems is continuously increasing. Highly-integrated system on chip solutions have to be encapsulated in a package and assembled on a board. In addition, to be more attractive as a product, the trend goes towards further integration of passives and antennas in a package. This drives the system in package solutions. However, electrical properties of the package and board may have a significant effect on system parameters, especially at high frequencies. Hence, layout features of package and board must be carefully modelled and considered during the design. Furthermore, it is often insufficient to model chip, package and board separately, as some high-frequency effects may not be captured. An example is electromagnetic coupling between integrated coils on chip and routing traces in package. In this paper we describe considerations on co-simulation and co-design of highly-integrated RF systems by means of accurate electromagnetic modelling. We demonstrate the approach and various aspects of chip-package-board co-design based on examples of systems for various applications: 6 GHz VCO using embedded inductor; backhaul communication system in package for V-band and E-band and a four-channel 77 GHz automotive radar transceiver in a package with four dipole antennas.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122665462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738967
J. Tsay, Juan José Vaquero López, D. Lie
This paper investigates the design of a linear highly-efficient SiGe power amplifier (PA) where its linearity, power-added efficiency (PAE) and POUT are studied vs. different LTE 16QAM signal BW and a relatively small bias resistance Rbias is used to set up the base bias from a DC voltage source in lieu of using a large choke inductor. The PA is designed in a 0.35-μm SiGe BiCMOS technology with through-silicon via (TSV), passing the stringent LTE spectrum emission mask (SEM) at average linear POUT = 23.5/23.1/23.1 dBm with 48.0/45.2/44.6% PAE for LTE 5/10/20 MHz inputs at Rbias = 500 Ω. However, both linearity and PAE degrade when Rbias decreases to 330 Ω or increases to 1000 Ω. The adjacent channel leakage ratios ACLR1/ACLR2 exhibit over 10-21 dB degradation at Rbias = 330 Ω and 1000 Ω for LTE 20 MHz input at POUT = 23.1 dBm (P1dB = 22.3 dBm), while they are practically unchanged against Rbias for 5 MHz LTE input or at 6 dB POUT back-off at 17.1 dBm. Envelope-tracking (ET) is also used to improve PA's efficiency at back-off for Rbias = 500 Ω. The data suggests for SiGe PA design with TSV, a small bias Rbias may be used in lieu of a large inductor to save area, while its performance is dependent on the optimal bias Rbias value - too high or too low of Rbias will degrade its RF gain, stability and linearity for both CW and LTE modulated signal inputs.
{"title":"The impacts of base bias resistor and LTE 16QAM signal bandwidth on high-efficiency linear SiGe power amplifier design","authors":"J. Tsay, Juan José Vaquero López, D. Lie","doi":"10.1109/BCTM.2016.7738967","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738967","url":null,"abstract":"This paper investigates the design of a linear highly-efficient SiGe power amplifier (PA) where its linearity, power-added efficiency (PAE) and P<sub>OUT</sub> are studied vs. different LTE 16QAM signal BW and a relatively small bias resistance R<sub>bias</sub> is used to set up the base bias from a DC voltage source in lieu of using a large choke inductor. The PA is designed in a 0.35-μm SiGe BiCMOS technology with through-silicon via (TSV), passing the stringent LTE spectrum emission mask (SEM) at average linear P<sub>OUT</sub> = 23.5/23.1/23.1 dBm with 48.0/45.2/44.6% PAE for LTE 5/10/20 MHz inputs at R<sub>bias</sub> = 500 Ω. However, both linearity and PAE degrade when R<sub>bias</sub> decreases to 330 Ω or increases to 1000 Ω. The adjacent channel leakage ratios ACLR1/ACLR2 exhibit over 10-21 dB degradation at R<sub>bias</sub> = 330 Ω and 1000 Ω for LTE 20 MHz input at P<sub>OUT</sub> = 23.1 dBm (P<sub>1dB</sub> = 22.3 dBm), while they are practically unchanged against R<sub>bias</sub> for 5 MHz LTE input or at 6 dB P<sub>OUT</sub> back-off at 17.1 dBm. Envelope-tracking (ET) is also used to improve PA's efficiency at back-off for R<sub>bias</sub> = 500 Ω. The data suggests for SiGe PA design with TSV, a small bias R<sub>bias</sub> may be used in lieu of a large inductor to save area, while its performance is dependent on the optimal bias R<sub>bias</sub> value - too high or too low of R<sub>bias</sub> will degrade its RF gain, stability and linearity for both CW and LTE modulated signal inputs.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116740367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738948
V. Jain, H. Ding, R. Camillo-Castillo, A. Joseph
Breakdown voltage and RF characteristics relevant for RF power amplifiers (PA) are presented in this paper. Typically, DC collector-to-emitter breakdown voltage with base open (BVCEO) or DC collector-to-base breakdown with emitter open (BVCBO) has been presented as the metric for voltage limit of PA devices. In practical PA circuits, the RF envelope voltage can swing well beyond BVCEO without causing a failure. An analysis of output power swing limitations and DC breakdown is presented with attention to biasing and temperature.
{"title":"DC and RF breakdown voltage characteristics of SiGe HBTs for WiFi PA applications","authors":"V. Jain, H. Ding, R. Camillo-Castillo, A. Joseph","doi":"10.1109/BCTM.2016.7738948","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738948","url":null,"abstract":"Breakdown voltage and RF characteristics relevant for RF power amplifiers (PA) are presented in this paper. Typically, DC collector-to-emitter breakdown voltage with base open (BVCEO) or DC collector-to-base breakdown with emitter open (BVCBO) has been presented as the metric for voltage limit of PA devices. In practical PA circuits, the RF envelope voltage can swing well beyond BVCEO without causing a failure. An analysis of output power swing limitations and DC breakdown is presented with attention to biasing and temperature.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121297800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738958
G. Fischer
By means of long-term mixed-mode stress tests of high-speed SiGe HBTs an empirical ageing function for compact models was constructed. This ageing function models saturation of the aging rate as a function of stress time and stress current and is applicable for all relevant mixed-mode stress conditions of this HBT type. Additionally, 1000h stress tests on a high-voltage HBT revealed that not only saturation but even reversal of ageing rate is possible in the long run.
{"title":"Analysis and modeling of the long-term ageing rate of SiGe HBTs under mixed-mode stress","authors":"G. Fischer","doi":"10.1109/BCTM.2016.7738958","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738958","url":null,"abstract":"By means of long-term mixed-mode stress tests of high-speed SiGe HBTs an empirical ageing function for compact models was constructed. This ageing function models saturation of the aging rate as a function of stress time and stress current and is applicable for all relevant mixed-mode stress conditions of this HBT type. Additionally, 1000h stress tests on a high-voltage HBT revealed that not only saturation but even reversal of ageing rate is possible in the long run.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122299313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738979
E. Coyne, S. Lynch, P. McGuinness, Christine McLoughline, Catriona O'Sullivan, B. Lane, L. O'Sullivan, J. Liddy
Known to the power industry, there is an increasing functional safety need to isolate delicate control systems from the violent world of the Insulated Gate Bipolar Transistor (IGBT), which has resulted in a growing demand for Digital Isolators. This is where the gate control signal for the IGBT can be coupled across a dielectric barrier, while the barrier itself is capable of withstanding high working voltages and surge events. Preventing the formation of a complete integrated system solution for the end customer is the fact that while the control signal can be coupled across the isolation barrier - the transient power needed to drive the IGBT gate cannot. To solve that problem, this paper describes the development of an innovative IGBT architecture that targets the 1200V voltage node, has a first silicon VCE(SAT) = 2.7V at JC=10Amm-1, provides latch-up immunity, and critically has gate drive capacitances that are over two orders of magnitude smaller, at 0.58pF for every Amp of IGBT current, relative to conventional IGBT architectures that report values in the range of 70 - 150pFA-1 at 25°C. This low input capacitance opens the door for the gate of this IGBT to be directly powered by integrated magnetically coupled isolation coils. For future work, further optimization of the VCE(SAT), and transient switching times are required.
{"title":"Low gate drive IGBT enabling direct control through Digital Isolator power","authors":"E. Coyne, S. Lynch, P. McGuinness, Christine McLoughline, Catriona O'Sullivan, B. Lane, L. O'Sullivan, J. Liddy","doi":"10.1109/BCTM.2016.7738979","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738979","url":null,"abstract":"Known to the power industry, there is an increasing functional safety need to isolate delicate control systems from the violent world of the Insulated Gate Bipolar Transistor (IGBT), which has resulted in a growing demand for Digital Isolators. This is where the gate control signal for the IGBT can be coupled across a dielectric barrier, while the barrier itself is capable of withstanding high working voltages and surge events. Preventing the formation of a complete integrated system solution for the end customer is the fact that while the control signal can be coupled across the isolation barrier - the transient power needed to drive the IGBT gate cannot. To solve that problem, this paper describes the development of an innovative IGBT architecture that targets the 1200V voltage node, has a first silicon VCE(SAT) = 2.7V at JC=10Amm-1, provides latch-up immunity, and critically has gate drive capacitances that are over two orders of magnitude smaller, at 0.58pF for every Amp of IGBT current, relative to conventional IGBT architectures that report values in the range of 70 - 150pFA-1 at 25°C. This low input capacitance opens the door for the gate of this IGBT to be directly powered by integrated magnetically coupled isolation coils. For future work, further optimization of the VCE(SAT), and transient switching times are required.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126713058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738956
Brian R. Wier, U. Raghunathan, Zachary E. Fleetwood, Michael A. Oakley, A. Joseph, V. Jain, J. Cressler
The implementation of a “superjunction” collector design in a silicon-germanium heterojunction bipolar transistor is explored for enhancing breakdown performance. The superjunction collector is formed through the placement of a series of alternating pn-junction layers in the collector-base space charge region to modify the carrier energy profile and reduce avalanche generation. An overview of the physics underlying superjunction collector operation is presented with TCAD simulations, and practical superjunction design techniques are discussed. The first measured data on a superjunction collector is also presented and shows a 57% improvement in breakdown performance.
{"title":"On the use of vertical superjunction collectors for enhanced breakdown performance in SiGe HBTs","authors":"Brian R. Wier, U. Raghunathan, Zachary E. Fleetwood, Michael A. Oakley, A. Joseph, V. Jain, J. Cressler","doi":"10.1109/BCTM.2016.7738956","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738956","url":null,"abstract":"The implementation of a “superjunction” collector design in a silicon-germanium heterojunction bipolar transistor is explored for enhancing breakdown performance. The superjunction collector is formed through the placement of a series of alternating pn-junction layers in the collector-base space charge region to modify the carrier energy profile and reduce avalanche generation. An overview of the physics underlying superjunction collector operation is presented with TCAD simulations, and practical superjunction design techniques are discussed. The first measured data on a superjunction collector is also presented and shows a 57% improvement in breakdown performance.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127742053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738942
J. Yau, J. Yoon, J. Cai, T. Ning, K. Chan, S. Engelmann, D. Park, R. Mo, G. Shahidi
We report the first demonstration of thin-base symmetric lateral NPN bipolar transistors built on 8-inch Ge-on-insulator (Ge-OI) wafers. A Ge-OI device can achieve the same collector current as a Si-OI device but at ~ 460 mV lower VBE due to the bandgap of Ge being 460 meV smaller than that of Si. Lower operation voltage should translate directly into lower power dissipation. CMOS-like process was used to fabricate lateral Ge-OI bipolar transistors. The measured collector and base currents are examined and compared with those of Si-OI and SiGe-OI devices to shed light on process-related device physics. The large observed base current at small VBE is attributed to recombination at the Ge/BOX interface in the emitter-base diode space-charge region.
{"title":"Ge-on-insulator lateral bipolar transistors","authors":"J. Yau, J. Yoon, J. Cai, T. Ning, K. Chan, S. Engelmann, D. Park, R. Mo, G. Shahidi","doi":"10.1109/BCTM.2016.7738942","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738942","url":null,"abstract":"We report the first demonstration of thin-base symmetric lateral NPN bipolar transistors built on 8-inch Ge-on-insulator (Ge-OI) wafers. A Ge-OI device can achieve the same collector current as a Si-OI device but at ~ 460 mV lower VBE due to the bandgap of Ge being 460 meV smaller than that of Si. Lower operation voltage should translate directly into lower power dissipation. CMOS-like process was used to fabricate lateral Ge-OI bipolar transistors. The measured collector and base currents are examined and compared with those of Si-OI and SiGe-OI devices to shed light on process-related device physics. The large observed base current at small VBE is attributed to recombination at the Ge/BOX interface in the emitter-base diode space-charge region.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127198315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738974
E. McCune
Dynamic power supply transmitters (DPST), including the techniques of envelope tracking (ET) and direct polar (DP) modulation, have a century of success in some applications. The original motivation was to improve the energy efficiency of the final power amplifier (PA), and that remains true today. These are methods to improve overall energy efficiency across wide signal and tuning bandwidths. Not all transistor types perform equally well in the various DPST architectures. This paper provides a quick review of DPST techniques and then examines how the presently available bipolar transistors apply to the various DPST options. It is concluded that bipolar transistors are presently much more suitable for ET than for DP implementations. Measurements demonstrate and explain this difference.
{"title":"Applying bipolar transistors in dynamic power supply transmitters","authors":"E. McCune","doi":"10.1109/BCTM.2016.7738974","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738974","url":null,"abstract":"Dynamic power supply transmitters (DPST), including the techniques of envelope tracking (ET) and direct polar (DP) modulation, have a century of success in some applications. The original motivation was to improve the energy efficiency of the final power amplifier (PA), and that remains true today. These are methods to improve overall energy efficiency across wide signal and tuning bandwidths. Not all transistor types perform equally well in the various DPST architectures. This paper provides a quick review of DPST techniques and then examines how the presently available bipolar transistors apply to the various DPST options. It is concluded that bipolar transistors are presently much more suitable for ET than for DP implementations. Measurements demonstrate and explain this difference.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121819407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/BCTM.2016.7738969
U. Raghunathan, Brian R. Wier, Rafael Perez Martinez, Zachary E. Fleetwood, Anup P. Omprakash, Hanbin Ying, S. Zeinolabedinzadeh, J. Cressler
High-current pulsed stress measurements are performed on SiGe HBTs to characterize the damage behavior and create a comprehensive physics-based TCAD damage model for Auger-induced hot-carrier damage. The Auger hot-carrier generation is decoupled from classical mixed-mode damage and annealing on the output plane by using pulsed stress conditions to modulate the self-heating within the device under stress. The physics of high-current degradation is analyzed, and a temperature dependent degradation model is presented. This model is the first of its kind in both the CMOS and bipolar communities and solves a significant portion of the puzzle for predictive modeling of SiGe HBT safe-operating-area (SOA) and reliability.
{"title":"Modeling of high-current damage in SiGe HBTs under pulsed stress","authors":"U. Raghunathan, Brian R. Wier, Rafael Perez Martinez, Zachary E. Fleetwood, Anup P. Omprakash, Hanbin Ying, S. Zeinolabedinzadeh, J. Cressler","doi":"10.1109/BCTM.2016.7738969","DOIUrl":"https://doi.org/10.1109/BCTM.2016.7738969","url":null,"abstract":"High-current pulsed stress measurements are performed on SiGe HBTs to characterize the damage behavior and create a comprehensive physics-based TCAD damage model for Auger-induced hot-carrier damage. The Auger hot-carrier generation is decoupled from classical mixed-mode damage and annealing on the output plane by using pulsed stress conditions to modulate the self-heating within the device under stress. The physics of high-current degradation is analyzed, and a temperature dependent degradation model is presented. This model is the first of its kind in both the CMOS and bipolar communities and solves a significant portion of the puzzle for predictive modeling of SiGe HBT safe-operating-area (SOA) and reliability.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131569524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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