2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)最新文献

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Improving the Detection of Undefined State Faults in FinFET SRAMs 改进FinFET ram中未定义状态故障的检测

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)

Pub Date : 2021-06-01 DOI: 10.1109/DTIS53253.2021.9505130

G. Medeiros, M. Fieback, T. Copetti, A. Gebregiorgis, M. Taouil, L. Poehls, S. Hamdioui

Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Undefined State Faults (USFs). Detection of USFs is not trivial, as they may not lead to incorrect functionality. Nevertheless, undetected USFs may have a severe impact on the memory’s quality: they can cause random read outputs, which might lead to test escapes and no-trouble-found devices later when the device is already in the field, as well as compromise the circuit’s quality by reducing the memory cell’s Static Noise Margin (SNM). Therefore, the detection of USF is critical. This paper proposes a test solution to improve the detection of USFs in FinFET SRAMs. To achieve this, we first analyze the impact of USFs on the cell’s SNM and bitline swing during read operations. Then, we perform an experimental study of stress conditions’ (SCs) impact on sensitizing and detecting USFs. Finally, we propose a dedicated Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults. This scheme introduces a small area overhead while significantly improving USF detection. Hence, using the proposed DFT leads to fewer test escapes and higher-quality FinFET SRAMs.

FinFET sram的制造缺陷可能导致难以检测的故障，如未定义状态故障(usf)。usf的检测不是微不足道的，因为它们可能不会导致不正确的功能。然而，未检测到的usf可能会对存储器的质量产生严重影响:它们可能会导致随机读取输出，这可能会导致测试逃逸和后来在设备已经在现场时没有发现故障的设备，以及通过降低存储器单元的静态噪声裕度(SNM)而损害电路的质量。因此，USF的检测至关重要。本文提出了一种改进FinFET sram中usf检测的测试方案。为了实现这一点，我们首先分析了usf在读操作期间对单元的SNM和位行摆动的影响。然后，我们进行了应激条件(SCs)对usf敏化和检测的影响的实验研究。最后，我们提出了一种专门的可测试性设计(DFT)方案，用于FinFET sram检测此类故障。该方案引入了较小的面积开销，同时显着提高了USF检测。因此，使用所提出的DFT导致更少的测试逃逸和更高质量的FinFET sram。

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