Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505137
P. Devoge, H. Aziza, P. Lorenzini, F. Julien, A. Marzaki, A. Malherbe, M. Mantelli, Thomas Sardin, S. Haendler, A. Régnier, S. Niel
This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing high-voltage transistor and is free in terms of photomasks and process steps, making it ideal for low-cost products. The new transistor is fabricated then electrically characterized, showing good analog performances. A SPICE (Simulation Program with Integrated Circuit Emphasis) model of the new device is developed to assess its circuit-level performances through electrical circuit simulation. The in-circuit performances of the new device are evaluated based on different ring oscillator circuits. A comparison with the existing high-voltage transistor is carried out considering performance parameters such as the oscillating frequency to demonstrate the appeal of our new transistor.
这项工作提出了一种新的晶体管架构，通过重用嵌入式非易失性存储器(eNVM) CMOS技术中已有的制造工艺步骤来开发。所提出的晶体管源自现有的高压晶体管，并且在光罩和工艺步骤方面是免费的，使其成为低成本产品的理想选择。该新型晶体管在制备过程中表现出良好的模拟性能。开发了新器件的SPICE (Integrated Circuit Simulation Program with Integrated Circuit Emphasis)模型，通过电路仿真来评估其电路级性能。基于不同的环形振荡器电路，对新器件的在线性能进行了评估。通过与现有高压晶体管的振荡频率等性能参数的比较，证明了新型晶体管的吸引力。
{"title":"Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology","authors":"P. Devoge, H. Aziza, P. Lorenzini, F. Julien, A. Marzaki, A. Malherbe, M. Mantelli, Thomas Sardin, S. Haendler, A. Régnier, S. Niel","doi":"10.1109/DTIS53253.2021.9505137","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505137","url":null,"abstract":"This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing high-voltage transistor and is free in terms of photomasks and process steps, making it ideal for low-cost products. The new transistor is fabricated then electrically characterized, showing good analog performances. A SPICE (Simulation Program with Integrated Circuit Emphasis) model of the new device is developed to assess its circuit-level performances through electrical circuit simulation. The in-circuit performances of the new device are evaluated based on different ring oscillator circuits. A comparison with the existing high-voltage transistor is carried out considering performance parameters such as the oscillating frequency to demonstrate the appeal of our new transistor.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115002063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505054
D. Santos, Lucas Matana Luza, M. Kastriotou, C. Cazzaniga, C. Zeferino, D. Melo, L. Dilillo
Systems for harsh environments often use embedded processors for tasks that require reliability. However, harsh environments cause faulty behavior in electronics, which eventually lead to system failure. Therefore, embedded processors must use techniques to improve their reliability. In this context, this work presents the implementation and characterization of a RISC-V-based system-on-chip. We characterized our implementation by carrying out test campaigns at the ChipIr irradiation facility. This facility provides a beamline for testing electronics against neutrons, mimicking atmospheric-like environments. With this first test campaign, we identified the most critical parts of our system-on-chip and essential tips to improve the test effectiveness. In the second test campaign, we used an improved version of the system setup with higher reliability error observability features. The version embedding all the hardening techniques could correct or mitigate 98.1 % of the detected upsets under irradiation.
{"title":"Characterization of a RISC-V System-on-Chip under Neutron Radiation","authors":"D. Santos, Lucas Matana Luza, M. Kastriotou, C. Cazzaniga, C. Zeferino, D. Melo, L. Dilillo","doi":"10.1109/DTIS53253.2021.9505054","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505054","url":null,"abstract":"Systems for harsh environments often use embedded processors for tasks that require reliability. However, harsh environments cause faulty behavior in electronics, which eventually lead to system failure. Therefore, embedded processors must use techniques to improve their reliability. In this context, this work presents the implementation and characterization of a RISC-V-based system-on-chip. We characterized our implementation by carrying out test campaigns at the ChipIr irradiation facility. This facility provides a beamline for testing electronics against neutrons, mimicking atmospheric-like environments. With this first test campaign, we identified the most critical parts of our system-on-chip and essential tips to improve the test effectiveness. In the second test campaign, we used an improved version of the system setup with higher reliability error observability features. The version embedding all the hardening techniques could correct or mitigate 98.1 % of the detected upsets under irradiation.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114643557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505023
{"title":"[Title page]","authors":"","doi":"10.1109/dtis53253.2021.9505023","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505023","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127140256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505101
L. Ammoura, M. Flottes, P. Girard, A. Virazel
In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.
{"title":"Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures","authors":"L. Ammoura, M. Flottes, P. Girard, A. Virazel","doi":"10.1109/DTIS53253.2021.9505101","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505101","url":null,"abstract":"In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127811760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505050
{"title":"DTIS 2021 Organizing Committee","authors":"","doi":"10.1109/dtis53253.2021.9505050","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505050","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114993248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505131
Heba Saleh, Rayan Bajwa, I. Tekin, M. Yapici
This work reports on the design and optimization of a low voltage shunt MEMS switch for 5G mobile applications. As opposed to clamped-clamped beams conventionally serving as RF-MEMS shunt switches, the present switch design utilizes a fixed-free cantilever beam in a shunt configuration to minimize the actuation voltage requirements. Moreover, RF performance parameters (ON-state insertion loss and OFF-state signal isolation) for the proposed switch design are optimized by means of extensive high-frequency simulations to enable the use of such devices in mm-wave regime. To critically analyze the key controlling factors affecting switch performance, a parameterized study on the geometrical parameters of the proposed topology is performed. The simulations were carried out using commercially available finite element solvers (CoventorWare® and HFSS) which validate the low-voltage operation of the reported switch with actuation voltage as low as 7.5V while maintaining the RF insertion loss and RF isolation values below -0.3dB and above -36dB, respectively, for frequencies up to 45GHz.
{"title":"Design and Optimization of Cantilever Based RF-MEMS Shunt Switch for 5G Applications","authors":"Heba Saleh, Rayan Bajwa, I. Tekin, M. Yapici","doi":"10.1109/DTIS53253.2021.9505131","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505131","url":null,"abstract":"This work reports on the design and optimization of a low voltage shunt MEMS switch for 5G mobile applications. As opposed to clamped-clamped beams conventionally serving as RF-MEMS shunt switches, the present switch design utilizes a fixed-free cantilever beam in a shunt configuration to minimize the actuation voltage requirements. Moreover, RF performance parameters (ON-state insertion loss and OFF-state signal isolation) for the proposed switch design are optimized by means of extensive high-frequency simulations to enable the use of such devices in mm-wave regime. To critically analyze the key controlling factors affecting switch performance, a parameterized study on the geometrical parameters of the proposed topology is performed. The simulations were carried out using commercially available finite element solvers (CoventorWare® and HFSS) which validate the low-voltage operation of the reported switch with actuation voltage as low as 7.5V while maintaining the RF insertion loss and RF isolation values below -0.3dB and above -36dB, respectively, for frequencies up to 45GHz.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127756894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505061
Sehmi Saad, F. Haddad, Aymen Ben Hammadi
This paper presents a high-resolution Class-C type voltage-controlled oscillator (VCO) with a robust start-up. The proposed oscillator achieves a minimum frequency quantification step of 270 Hz without adding any additional dithering approach. The very fine tuning is obtained through a capacitive-inductive degeneration coupling (CIDC) technique which reduces the capacitance value without appreciably affecting the intrinsic oscillator phase noise (PN). This technique also provides a negative transconductance to compensate for losses in the LC tank, resulting in high oscillation amplitude and relatively low power consumption in the oscillator core. The proposed design, implemented in 130 nm CMOS technology, achieves 45% tuning range. It exhibits a phase noise of –107 dBc/Hz @ 1-MHz offset, while it draws 5.75 mA from a supply of 1.2 V, resulting in a FoM of 165 dBc/Hz.
{"title":"A 270 Hz, Fine Frequency Tuning Class-C Oscillator Using Capacitive--Inductive Degeneration Technique in 130 -nm CMOS","authors":"Sehmi Saad, F. Haddad, Aymen Ben Hammadi","doi":"10.1109/DTIS53253.2021.9505061","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505061","url":null,"abstract":"This paper presents a high-resolution Class-C type voltage-controlled oscillator (VCO) with a robust start-up. The proposed oscillator achieves a minimum frequency quantification step of 270 Hz without adding any additional dithering approach. The very fine tuning is obtained through a capacitive-inductive degeneration coupling (CIDC) technique which reduces the capacitance value without appreciably affecting the intrinsic oscillator phase noise (PN). This technique also provides a negative transconductance to compensate for losses in the LC tank, resulting in high oscillation amplitude and relatively low power consumption in the oscillator core. The proposed design, implemented in 130 nm CMOS technology, achieves 45% tuning range. It exhibits a phase noise of –107 dBc/Hz @ 1-MHz offset, while it draws 5.75 mA from a supply of 1.2 V, resulting in a FoM of 165 dBc/Hz.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"26 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116789228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505109
Gabriel Rocherolle, R. Chotin
Along with performance, one of the main concerns in cryptographer circuits implementation is Side Channel Attacks robustness. Given a cipher, many functionally equivalent circuits can be associated, with mixed performances and robustness. The work presented in this paper consists in a methodological effort to assist and qualify cipher circuits designs with a framework for a modular, sustained and iterative workflow through know-how capitalization. Simulation allows qualifying cipher hardware implementations against threats such as physical cryptanalysis. New versions are to be compared with respect to references early in design workflow, judging counter-measure efficiency or preventing security regressions.
{"title":"Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits","authors":"Gabriel Rocherolle, R. Chotin","doi":"10.1109/DTIS53253.2021.9505109","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505109","url":null,"abstract":"Along with performance, one of the main concerns in cryptographer circuits implementation is Side Channel Attacks robustness. Given a cipher, many functionally equivalent circuits can be associated, with mixed performances and robustness. The work presented in this paper consists in a methodological effort to assist and qualify cipher circuits designs with a framework for a modular, sustained and iterative workflow through know-how capitalization. Simulation allows qualifying cipher hardware implementations against threats such as physical cryptanalysis. New versions are to be compared with respect to references early in design workflow, judging counter-measure efficiency or preventing security regressions.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130311366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505135
Andrea Marchesin, G. Turvani, A. Coluccio, F. Riente, M. Vacca, Massimo Ruo Roch, M. Graziano, M. Zamboni
Nowadays, the modern electronic systems are facing an important limitation in terms of performance, known as von Neumann bottleneck. It affects the communications between two crucial elements, the CPU and the memory, which suffer from a saturation in bandwidth. Many solutions are currently under investigation and among them the concept of Logic-in-Memory (LiM) has been introduced: a memory enriched in its array of computational elements which enable the implementation of a flexible distributed processing system. The current work introduces Octantis, a High-Level Synthesizer useful for the exploration of LiM architectures. The proposed software analyzes an input algorithm described in standard C language and identifies which LiM architecture would implement it better. At its output, the synthesized solution is provided together with a test-bench, to properly characterize it, in terms of performance, spatial occupation and power consumption. Many algorithms have been successfully synthesized by Octantis and some of the results achieved will be discussed along the document.
{"title":"Octantis: An Exploration Tool for Beyond von Neumann architectures","authors":"Andrea Marchesin, G. Turvani, A. Coluccio, F. Riente, M. Vacca, Massimo Ruo Roch, M. Graziano, M. Zamboni","doi":"10.1109/DTIS53253.2021.9505135","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505135","url":null,"abstract":"Nowadays, the modern electronic systems are facing an important limitation in terms of performance, known as von Neumann bottleneck. It affects the communications between two crucial elements, the CPU and the memory, which suffer from a saturation in bandwidth. Many solutions are currently under investigation and among them the concept of Logic-in-Memory (LiM) has been introduced: a memory enriched in its array of computational elements which enable the implementation of a flexible distributed processing system. The current work introduces Octantis, a High-Level Synthesizer useful for the exploration of LiM architectures. The proposed software analyzes an input algorithm described in standard C language and identifies which LiM architecture would implement it better. At its output, the synthesized solution is provided together with a test-bench, to properly characterize it, in terms of performance, spatial occupation and power consumption. Many algorithms have been successfully synthesized by Octantis and some of the results achieved will be discussed along the document.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129203624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505053
D. Melo, C. Zeferino, E. Bezerra, L. Dilillo
This work investigates synthesis alternatives to minimize error propagation in the controllers responsible for flow regulation, packet routing, and resource arbitration in a Network-on-Chip router. The controllers are based on Finite-State Machines to provide flexibility and favor low resource usage in programmable logic devices. The proposed router embeds hardening techniques by using triple modular redundancy on controllers and the Hamming code on buffers. Experimental results show that the packet routing controller has the most impact on the metrics evaluated and that the migration from a Moore to a Mealy controller implementation reduces the error propagation and offers a higher throughput than hardening the controllers. The main contribution of this work consists of assessing the impact of different implementations of a router in terms of error propagation.
{"title":"Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router","authors":"D. Melo, C. Zeferino, E. Bezerra, L. Dilillo","doi":"10.1109/DTIS53253.2021.9505053","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505053","url":null,"abstract":"This work investigates synthesis alternatives to minimize error propagation in the controllers responsible for flow regulation, packet routing, and resource arbitration in a Network-on-Chip router. The controllers are based on Finite-State Machines to provide flexibility and favor low resource usage in programmable logic devices. The proposed router embeds hardening techniques by using triple modular redundancy on controllers and the Hamming code on buffers. Experimental results show that the packet routing controller has the most impact on the metrics evaluated and that the migration from a Moore to a Mealy controller implementation reduces the error propagation and offers a higher throughput than hardening the controllers. The main contribution of this work consists of assessing the impact of different implementations of a router in terms of error propagation.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133858420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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