Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505144
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen
Massive multisite testing significantly reduces test cost and immensely increases production throughput by simultaneously screening multiple devices under test (DUTs). However, non-trivial variations in measurement from site to site are inevitable, and they often alter the actual DUTs specifications leading to yield loss (good DUTs rejected as bad) or necessitate poorer DUT specifications. These site-induced variations make it challenging to know the true silicon performance in a multisite probing environment, making statistical processing control difficult. In this paper, we propose and compare three methods to remove the variability introduced by multisite test hardware for accurate estimation of DUTs true performance distributions. The key idea is to select high confidence good test sites for parametric analysis. We demonstrate the accuracy of the proposed methods using simulation and measurement data.
{"title":"Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation","authors":"Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen","doi":"10.1109/DTIS53253.2021.9505144","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505144","url":null,"abstract":"Massive multisite testing significantly reduces test cost and immensely increases production throughput by simultaneously screening multiple devices under test (DUTs). However, non-trivial variations in measurement from site to site are inevitable, and they often alter the actual DUTs specifications leading to yield loss (good DUTs rejected as bad) or necessitate poorer DUT specifications. These site-induced variations make it challenging to know the true silicon performance in a multisite probing environment, making statistical processing control difficult. In this paper, we propose and compare three methods to remove the variability introduced by multisite test hardware for accurate estimation of DUTs true performance distributions. The key idea is to select high confidence good test sites for parametric analysis. We demonstrate the accuracy of the proposed methods using simulation and measurement data.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134187144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505128
G. Mezzina, D. Venuto
This paper proposes the re-design of the functionalities of the personal care robot (PCR) Pepper by SoftBank Robotics. Pepper is mainly designed for verbal interaction with patients and despite the presence of two upper arms, it lacks object manipulation capabilities. In the proposed re-design, a combination of data from Pepper RGB camera and 3D depth sensor is used to identify and localize a specific pharmaceutical envelope in a dedicated repository. In this context, the semantic segmentation of the RGB image has been entrusted to a dedicated pretrained YOLOv3 object detector, while a dedicated algorithm has been realized for the hand (gripper) positioning. Basing on this 3D positional information, the PCR operates an ad-hoc designed routine to grasp the object and to scan it. Once the scanning procedure confirms that the grasping has been successfully completed and that the grasped package matches with the needed drug, the PCR must be able to safely navigate towards the user (e.g., physician, patient), delivering the drug. The proposed procedure is fully automatic, and no internet connection is needed for the nominal use case, preserving -in this way- sensitive data like home/hospital maps, patient’s data and so on. Experimental results on the here proposed object manipulation routine demonstrated a grasping success rate up to 96 %, even if the objects are not properly positioned in the dedicated repository. Finally, a proof of concept that implements a sequential pick-up, object recognition and delivery operation is also provided demonstrating real-life scenario applicability.
{"title":"RGB and 3D-Segmentation Data Combination for the Autonomous Object Manipulation in Personal Care Robotics","authors":"G. Mezzina, D. Venuto","doi":"10.1109/DTIS53253.2021.9505128","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505128","url":null,"abstract":"This paper proposes the re-design of the functionalities of the personal care robot (PCR) Pepper by SoftBank Robotics. Pepper is mainly designed for verbal interaction with patients and despite the presence of two upper arms, it lacks object manipulation capabilities. In the proposed re-design, a combination of data from Pepper RGB camera and 3D depth sensor is used to identify and localize a specific pharmaceutical envelope in a dedicated repository. In this context, the semantic segmentation of the RGB image has been entrusted to a dedicated pretrained YOLOv3 object detector, while a dedicated algorithm has been realized for the hand (gripper) positioning. Basing on this 3D positional information, the PCR operates an ad-hoc designed routine to grasp the object and to scan it. Once the scanning procedure confirms that the grasping has been successfully completed and that the grasped package matches with the needed drug, the PCR must be able to safely navigate towards the user (e.g., physician, patient), delivering the drug. The proposed procedure is fully automatic, and no internet connection is needed for the nominal use case, preserving -in this way- sensitive data like home/hospital maps, patient’s data and so on. Experimental results on the here proposed object manipulation routine demonstrated a grasping success rate up to 96 %, even if the objects are not properly positioned in the dedicated repository. Finally, a proof of concept that implements a sequential pick-up, object recognition and delivery operation is also provided demonstrating real-life scenario applicability.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126392188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505141
{"title":"[Copyright notice]","authors":"","doi":"10.1109/dtis53253.2021.9505141","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505141","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114416485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505075
M. Taouil, Abdullah Aljuffri, S. Hamdioui
Side channel attacks are a serious threat to integrated circuits. They are hardly detectable and use inherent information leaked by the hardware to infer sensitive information like secret keys. Over the last ten years, numerous side channel attacks have been examined, exploring various forms of leakage channels such as time, power, electromagnetic field, photon emission, and acoustic. Among them, power side channel attacks are the most popular ones. Developing an appropriate counter-measure against such attacks requires a deep understanding of these attacks. This paper presents a study of the most popular power attacks such as differential power attack and correlation power attack and discusses the latest countermeasures in this domain and their shortcomings.
{"title":"Power Side Channel Attacks: Where Are We Standing?","authors":"M. Taouil, Abdullah Aljuffri, S. Hamdioui","doi":"10.1109/DTIS53253.2021.9505075","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505075","url":null,"abstract":"Side channel attacks are a serious threat to integrated circuits. They are hardly detectable and use inherent information leaked by the hardware to infer sensitive information like secret keys. Over the last ten years, numerous side channel attacks have been examined, exploring various forms of leakage channels such as time, power, electromagnetic field, photon emission, and acoustic. Among them, power side channel attacks are the most popular ones. Developing an appropriate counter-measure against such attacks requires a deep understanding of these attacks. This paper presents a study of the most popular power attacks such as differential power attack and correlation power attack and discusses the latest countermeasures in this domain and their shortcomings.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505151
Antoine Linarès, D. Hély, F. Lhermet, G. D. Natale
Software Hardening against memory safety exploits can be achieved from the silicon, up to the software, with both compilers and operating systems features. Unfortunately, due to the growing evolution of attacks, security architects have no guarantees, at an early stage of the development, that defenses will match the security needs and overcome the targeted threats. In addition, after product release, it is difficult to evaluate the architecture performance against new threats. This paper presents a dynamic analysis technique that allows the evaluation of the security profile of a given architecture during design exploration. The method is designed to highlight and quantify the security threats covered by the countermeasures embedded at any level of a given architecture. The provided results will help for protection evaluation, classification, and architecture choices. The method comes with a tool that implements this approach and has been applied to several architectures. This tool helps to classify architecture along with its alternatives thanks to metrics.
{"title":"Design Space Exploration Applied to Security","authors":"Antoine Linarès, D. Hély, F. Lhermet, G. D. Natale","doi":"10.1109/DTIS53253.2021.9505151","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505151","url":null,"abstract":"Software Hardening against memory safety exploits can be achieved from the silicon, up to the software, with both compilers and operating systems features. Unfortunately, due to the growing evolution of attacks, security architects have no guarantees, at an early stage of the development, that defenses will match the security needs and overcome the targeted threats. In addition, after product release, it is difficult to evaluate the architecture performance against new threats. This paper presents a dynamic analysis technique that allows the evaluation of the security profile of a given architecture during design exploration. The method is designed to highlight and quantify the security threats covered by the countermeasures embedded at any level of a given architecture. The provided results will help for protection evaluation, classification, and architecture choices. The method comes with a tool that implements this approach and has been applied to several architectures. This tool helps to classify architecture along with its alternatives thanks to metrics.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"15 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113935117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9525422
Antaryami Panigrahi, Agile Mathew
A low dropout regulator(LDO) based on flipped voltage follower (FVF) assisted by a voltage combiner is presented in this work. This LDO offers stable regulation over wide range of load capacitances starting from 10pF to 50nF, without depending upon on-chip or off-chip load capacitance. It also offers extended the load regulation operation from 200µA to 50mA. This enhancement is achieved by incorporating a a voltage combiner stage, small feed-forward capacitor (CF) and compensation circuitry. For improving stability, Miller’s Compensation with a nulling resistor is implemented using 75pF capacitor, 4.5kΩ resistor. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot during sharp load current transitions down to 200mV at 100pF. The designed LDO is verified with simulation in 45-nm CMOS process. For an input voltage of a 1.2V and output voltage of 1.08V, the simulated worst case undershoot and overshoot are respectively 115 mV and 74 mV, respectively, for load transient of 200µA to 50mA within edge times of 10 nSec. The quiescent current is 25uA. The simulated PSR is -42 dB over the band of 10-1kHz, -20dB at 1MHz over 200uA-50mA of load currents.
{"title":"A 1.2V On-chip Output-capacitor-less Low Dropout Regulator based on Flipped Voltage Follower in 45nm CMOS Technology","authors":"Antaryami Panigrahi, Agile Mathew","doi":"10.1109/DTIS53253.2021.9525422","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9525422","url":null,"abstract":"A low dropout regulator(LDO) based on flipped voltage follower (FVF) assisted by a voltage combiner is presented in this work. This LDO offers stable regulation over wide range of load capacitances starting from 10pF to 50nF, without depending upon on-chip or off-chip load capacitance. It also offers extended the load regulation operation from 200µA to 50mA. This enhancement is achieved by incorporating a a voltage combiner stage, small feed-forward capacitor (CF) and compensation circuitry. For improving stability, Miller’s Compensation with a nulling resistor is implemented using 75pF capacitor, 4.5kΩ resistor. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot during sharp load current transitions down to 200mV at 100pF. The designed LDO is verified with simulation in 45-nm CMOS process. For an input voltage of a 1.2V and output voltage of 1.08V, the simulated worst case undershoot and overshoot are respectively 115 mV and 74 mV, respectively, for load transient of 200µA to 50mA within edge times of 10 nSec. The quiescent current is 25uA. The simulated PSR is -42 dB over the band of 10-1kHz, -20dB at 1MHz over 200uA-50mA of load currents.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505024
{"title":"DTIS 2021 Foreword","authors":"","doi":"10.1109/dtis53253.2021.9505024","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505024","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"19 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120910308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505160
{"title":"[Title page]","authors":"","doi":"10.1109/dtis53253.2021.9505160","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505160","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124565356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505139
Luca Zulberti, P. Nannipieri, L. Fanucci
The complexity of heterogenous Systems-on-Chip has overgrown in the last decades, and the effort necessary to set up a verification workflow has increased as well. The time spent on the verification phase of a design takes on average 57% of the project time, and in these years, several solutions aimed to automate that task have been developed. Some relevant works in this field automate the VLSI design flow from synthesis to Place-And-Route and Layout-Vs-Schematic design check but miss software design in the automated verification loop. Our work focuses on the early stages of the design phase, where designers take software and hardware choices to explore a larger design space. In this work, we present a flexible, Make-based framework to build up verification and design environments. It aids the development of Systems-on-Chip running RISC-V processors, automating software compilation, cycle-true simulations and post-synthesis analyses. It exploits the parallelism of the Make build tool to ensure results consistency, provide flow reproducibility, and accelerate the design space exploration using different flow recipes provided by the designer. Its modular structure allows it to perform each task with various third-party tools and makes the workflow execution chain customizable. Using the proposed framework, we show how the reduced designer effort increases design productivity. Indeed, the time needed to build up a validated development environment is consistently reduced by using few configuration properties to setup all the tools used in the workflow.
{"title":"A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture","authors":"Luca Zulberti, P. Nannipieri, L. Fanucci","doi":"10.1109/DTIS53253.2021.9505139","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505139","url":null,"abstract":"The complexity of heterogenous Systems-on-Chip has overgrown in the last decades, and the effort necessary to set up a verification workflow has increased as well. The time spent on the verification phase of a design takes on average 57% of the project time, and in these years, several solutions aimed to automate that task have been developed. Some relevant works in this field automate the VLSI design flow from synthesis to Place-And-Route and Layout-Vs-Schematic design check but miss software design in the automated verification loop. Our work focuses on the early stages of the design phase, where designers take software and hardware choices to explore a larger design space. In this work, we present a flexible, Make-based framework to build up verification and design environments. It aids the development of Systems-on-Chip running RISC-V processors, automating software compilation, cycle-true simulations and post-synthesis analyses. It exploits the parallelism of the Make build tool to ensure results consistency, provide flow reproducibility, and accelerate the design space exploration using different flow recipes provided by the designer. Its modular structure allows it to perform each task with various third-party tools and makes the workflow execution chain customizable. Using the proposed framework, we show how the reduced designer effort increases design productivity. Indeed, the time needed to build up a validated development environment is consistently reduced by using few configuration properties to setup all the tools used in the workflow.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124417282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505143
Lucas Matana Luza, D. Söderström, André Martins Pio de Mattos, E. Bezerra, C. Cazzaniga, M. Kastriotou, C. Poivey, L. Dilillo
This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studied and characterized, presenting the occurrence of single-bit upsets and stuck bits. The cross sections for each type of event and technology node show that the 110 nm model is more sensitive to neutron-induced single-event effects than the other models.
{"title":"Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study","authors":"Lucas Matana Luza, D. Söderström, André Martins Pio de Mattos, E. Bezerra, C. Cazzaniga, M. Kastriotou, C. Poivey, L. Dilillo","doi":"10.1109/DTIS53253.2021.9505143","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505143","url":null,"abstract":"This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studied and characterized, presenting the occurrence of single-bit upsets and stuck bits. The cross sections for each type of event and technology node show that the 110 nm model is more sensitive to neutron-induced single-event effects than the other models.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126801769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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