Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505053
D. Melo, C. Zeferino, E. Bezerra, L. Dilillo
This work investigates synthesis alternatives to minimize error propagation in the controllers responsible for flow regulation, packet routing, and resource arbitration in a Network-on-Chip router. The controllers are based on Finite-State Machines to provide flexibility and favor low resource usage in programmable logic devices. The proposed router embeds hardening techniques by using triple modular redundancy on controllers and the Hamming code on buffers. Experimental results show that the packet routing controller has the most impact on the metrics evaluated and that the migration from a Moore to a Mealy controller implementation reduces the error propagation and offers a higher throughput than hardening the controllers. The main contribution of this work consists of assessing the impact of different implementations of a router in terms of error propagation.
{"title":"Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router","authors":"D. Melo, C. Zeferino, E. Bezerra, L. Dilillo","doi":"10.1109/DTIS53253.2021.9505053","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505053","url":null,"abstract":"This work investigates synthesis alternatives to minimize error propagation in the controllers responsible for flow regulation, packet routing, and resource arbitration in a Network-on-Chip router. The controllers are based on Finite-State Machines to provide flexibility and favor low resource usage in programmable logic devices. The proposed router embeds hardening techniques by using triple modular redundancy on controllers and the Hamming code on buffers. Experimental results show that the packet routing controller has the most impact on the metrics evaluated and that the migration from a Moore to a Mealy controller implementation reduces the error propagation and offers a higher throughput than hardening the controllers. The main contribution of this work consists of assessing the impact of different implementations of a router in terms of error propagation.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133858420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505135
Andrea Marchesin, G. Turvani, A. Coluccio, F. Riente, M. Vacca, Massimo Ruo Roch, M. Graziano, M. Zamboni
Nowadays, the modern electronic systems are facing an important limitation in terms of performance, known as von Neumann bottleneck. It affects the communications between two crucial elements, the CPU and the memory, which suffer from a saturation in bandwidth. Many solutions are currently under investigation and among them the concept of Logic-in-Memory (LiM) has been introduced: a memory enriched in its array of computational elements which enable the implementation of a flexible distributed processing system. The current work introduces Octantis, a High-Level Synthesizer useful for the exploration of LiM architectures. The proposed software analyzes an input algorithm described in standard C language and identifies which LiM architecture would implement it better. At its output, the synthesized solution is provided together with a test-bench, to properly characterize it, in terms of performance, spatial occupation and power consumption. Many algorithms have been successfully synthesized by Octantis and some of the results achieved will be discussed along the document.
{"title":"Octantis: An Exploration Tool for Beyond von Neumann architectures","authors":"Andrea Marchesin, G. Turvani, A. Coluccio, F. Riente, M. Vacca, Massimo Ruo Roch, M. Graziano, M. Zamboni","doi":"10.1109/DTIS53253.2021.9505135","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505135","url":null,"abstract":"Nowadays, the modern electronic systems are facing an important limitation in terms of performance, known as von Neumann bottleneck. It affects the communications between two crucial elements, the CPU and the memory, which suffer from a saturation in bandwidth. Many solutions are currently under investigation and among them the concept of Logic-in-Memory (LiM) has been introduced: a memory enriched in its array of computational elements which enable the implementation of a flexible distributed processing system. The current work introduces Octantis, a High-Level Synthesizer useful for the exploration of LiM architectures. The proposed software analyzes an input algorithm described in standard C language and identifies which LiM architecture would implement it better. At its output, the synthesized solution is provided together with a test-bench, to properly characterize it, in terms of performance, spatial occupation and power consumption. Many algorithms have been successfully synthesized by Octantis and some of the results achieved will be discussed along the document.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129203624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505141
{"title":"[Copyright notice]","authors":"","doi":"10.1109/dtis53253.2021.9505141","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505141","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114416485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505075
M. Taouil, Abdullah Aljuffri, S. Hamdioui
Side channel attacks are a serious threat to integrated circuits. They are hardly detectable and use inherent information leaked by the hardware to infer sensitive information like secret keys. Over the last ten years, numerous side channel attacks have been examined, exploring various forms of leakage channels such as time, power, electromagnetic field, photon emission, and acoustic. Among them, power side channel attacks are the most popular ones. Developing an appropriate counter-measure against such attacks requires a deep understanding of these attacks. This paper presents a study of the most popular power attacks such as differential power attack and correlation power attack and discusses the latest countermeasures in this domain and their shortcomings.
{"title":"Power Side Channel Attacks: Where Are We Standing?","authors":"M. Taouil, Abdullah Aljuffri, S. Hamdioui","doi":"10.1109/DTIS53253.2021.9505075","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505075","url":null,"abstract":"Side channel attacks are a serious threat to integrated circuits. They are hardly detectable and use inherent information leaked by the hardware to infer sensitive information like secret keys. Over the last ten years, numerous side channel attacks have been examined, exploring various forms of leakage channels such as time, power, electromagnetic field, photon emission, and acoustic. Among them, power side channel attacks are the most popular ones. Developing an appropriate counter-measure against such attacks requires a deep understanding of these attacks. This paper presents a study of the most popular power attacks such as differential power attack and correlation power attack and discusses the latest countermeasures in this domain and their shortcomings.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505024
{"title":"DTIS 2021 Foreword","authors":"","doi":"10.1109/dtis53253.2021.9505024","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505024","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"19 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120910308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505151
Antoine Linarès, D. Hély, F. Lhermet, G. D. Natale
Software Hardening against memory safety exploits can be achieved from the silicon, up to the software, with both compilers and operating systems features. Unfortunately, due to the growing evolution of attacks, security architects have no guarantees, at an early stage of the development, that defenses will match the security needs and overcome the targeted threats. In addition, after product release, it is difficult to evaluate the architecture performance against new threats. This paper presents a dynamic analysis technique that allows the evaluation of the security profile of a given architecture during design exploration. The method is designed to highlight and quantify the security threats covered by the countermeasures embedded at any level of a given architecture. The provided results will help for protection evaluation, classification, and architecture choices. The method comes with a tool that implements this approach and has been applied to several architectures. This tool helps to classify architecture along with its alternatives thanks to metrics.
{"title":"Design Space Exploration Applied to Security","authors":"Antoine Linarès, D. Hély, F. Lhermet, G. D. Natale","doi":"10.1109/DTIS53253.2021.9505151","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505151","url":null,"abstract":"Software Hardening against memory safety exploits can be achieved from the silicon, up to the software, with both compilers and operating systems features. Unfortunately, due to the growing evolution of attacks, security architects have no guarantees, at an early stage of the development, that defenses will match the security needs and overcome the targeted threats. In addition, after product release, it is difficult to evaluate the architecture performance against new threats. This paper presents a dynamic analysis technique that allows the evaluation of the security profile of a given architecture during design exploration. The method is designed to highlight and quantify the security threats covered by the countermeasures embedded at any level of a given architecture. The provided results will help for protection evaluation, classification, and architecture choices. The method comes with a tool that implements this approach and has been applied to several architectures. This tool helps to classify architecture along with its alternatives thanks to metrics.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"15 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113935117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9525422
Antaryami Panigrahi, Agile Mathew
A low dropout regulator(LDO) based on flipped voltage follower (FVF) assisted by a voltage combiner is presented in this work. This LDO offers stable regulation over wide range of load capacitances starting from 10pF to 50nF, without depending upon on-chip or off-chip load capacitance. It also offers extended the load regulation operation from 200µA to 50mA. This enhancement is achieved by incorporating a a voltage combiner stage, small feed-forward capacitor (CF) and compensation circuitry. For improving stability, Miller’s Compensation with a nulling resistor is implemented using 75pF capacitor, 4.5kΩ resistor. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot during sharp load current transitions down to 200mV at 100pF. The designed LDO is verified with simulation in 45-nm CMOS process. For an input voltage of a 1.2V and output voltage of 1.08V, the simulated worst case undershoot and overshoot are respectively 115 mV and 74 mV, respectively, for load transient of 200µA to 50mA within edge times of 10 nSec. The quiescent current is 25uA. The simulated PSR is -42 dB over the band of 10-1kHz, -20dB at 1MHz over 200uA-50mA of load currents.
{"title":"A 1.2V On-chip Output-capacitor-less Low Dropout Regulator based on Flipped Voltage Follower in 45nm CMOS Technology","authors":"Antaryami Panigrahi, Agile Mathew","doi":"10.1109/DTIS53253.2021.9525422","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9525422","url":null,"abstract":"A low dropout regulator(LDO) based on flipped voltage follower (FVF) assisted by a voltage combiner is presented in this work. This LDO offers stable regulation over wide range of load capacitances starting from 10pF to 50nF, without depending upon on-chip or off-chip load capacitance. It also offers extended the load regulation operation from 200µA to 50mA. This enhancement is achieved by incorporating a a voltage combiner stage, small feed-forward capacitor (CF) and compensation circuitry. For improving stability, Miller’s Compensation with a nulling resistor is implemented using 75pF capacitor, 4.5kΩ resistor. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot during sharp load current transitions down to 200mV at 100pF. The designed LDO is verified with simulation in 45-nm CMOS process. For an input voltage of a 1.2V and output voltage of 1.08V, the simulated worst case undershoot and overshoot are respectively 115 mV and 74 mV, respectively, for load transient of 200µA to 50mA within edge times of 10 nSec. The quiescent current is 25uA. The simulated PSR is -42 dB over the band of 10-1kHz, -20dB at 1MHz over 200uA-50mA of load currents.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/dtis53253.2021.9505160
{"title":"[Title page]","authors":"","doi":"10.1109/dtis53253.2021.9505160","DOIUrl":"https://doi.org/10.1109/dtis53253.2021.9505160","url":null,"abstract":"","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124565356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505139
Luca Zulberti, P. Nannipieri, L. Fanucci
The complexity of heterogenous Systems-on-Chip has overgrown in the last decades, and the effort necessary to set up a verification workflow has increased as well. The time spent on the verification phase of a design takes on average 57% of the project time, and in these years, several solutions aimed to automate that task have been developed. Some relevant works in this field automate the VLSI design flow from synthesis to Place-And-Route and Layout-Vs-Schematic design check but miss software design in the automated verification loop. Our work focuses on the early stages of the design phase, where designers take software and hardware choices to explore a larger design space. In this work, we present a flexible, Make-based framework to build up verification and design environments. It aids the development of Systems-on-Chip running RISC-V processors, automating software compilation, cycle-true simulations and post-synthesis analyses. It exploits the parallelism of the Make build tool to ensure results consistency, provide flow reproducibility, and accelerate the design space exploration using different flow recipes provided by the designer. Its modular structure allows it to perform each task with various third-party tools and makes the workflow execution chain customizable. Using the proposed framework, we show how the reduced designer effort increases design productivity. Indeed, the time needed to build up a validated development environment is consistently reduced by using few configuration properties to setup all the tools used in the workflow.
{"title":"A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture","authors":"Luca Zulberti, P. Nannipieri, L. Fanucci","doi":"10.1109/DTIS53253.2021.9505139","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505139","url":null,"abstract":"The complexity of heterogenous Systems-on-Chip has overgrown in the last decades, and the effort necessary to set up a verification workflow has increased as well. The time spent on the verification phase of a design takes on average 57% of the project time, and in these years, several solutions aimed to automate that task have been developed. Some relevant works in this field automate the VLSI design flow from synthesis to Place-And-Route and Layout-Vs-Schematic design check but miss software design in the automated verification loop. Our work focuses on the early stages of the design phase, where designers take software and hardware choices to explore a larger design space. In this work, we present a flexible, Make-based framework to build up verification and design environments. It aids the development of Systems-on-Chip running RISC-V processors, automating software compilation, cycle-true simulations and post-synthesis analyses. It exploits the parallelism of the Make build tool to ensure results consistency, provide flow reproducibility, and accelerate the design space exploration using different flow recipes provided by the designer. Its modular structure allows it to perform each task with various third-party tools and makes the workflow execution chain customizable. Using the proposed framework, we show how the reduced designer effort increases design productivity. Indeed, the time needed to build up a validated development environment is consistently reduced by using few configuration properties to setup all the tools used in the workflow.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124417282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505143
Lucas Matana Luza, D. Söderström, André Martins Pio de Mattos, E. Bezerra, C. Cazzaniga, M. Kastriotou, C. Poivey, L. Dilillo
This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studied and characterized, presenting the occurrence of single-bit upsets and stuck bits. The cross sections for each type of event and technology node show that the 110 nm model is more sensitive to neutron-induced single-event effects than the other models.
{"title":"Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study","authors":"Lucas Matana Luza, D. Söderström, André Martins Pio de Mattos, E. Bezerra, C. Cazzaniga, M. Kastriotou, C. Poivey, L. Dilillo","doi":"10.1109/DTIS53253.2021.9505143","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505143","url":null,"abstract":"This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studied and characterized, presenting the occurrence of single-bit upsets and stuck bits. The cross sections for each type of event and technology node show that the 110 nm model is more sensitive to neutron-induced single-event effects than the other models.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126801769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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