Abstract Digital transformation affects many aspects of our everyday lives. This paper focuses on challenges and opportunities in the area of factory automation. It presents the layout and components of the Pilotfabrik Industrie 4.0 of TU Wien as an example of a modern, flexible, and highly digitized smart factory. Furthermore, the paper presents use cases that were implemented based on the available IoPT devices in the Pilotfabrik Industrie 4.0. The first use case aims to improve product quality by detecting chatter – a vibrational phenomenon in machine tools – and taking appropriate countermeasures. The second use case tries to predict tool breakage by closely monitoring the power consumption of the machine tool and, thus, reducing the probability of damaged products.
{"title":"IoPT integration on the factory floor: a case study","authors":"Alexander Raschendorfer, Thomas Frühwirth","doi":"10.1515/itit-2023-0005","DOIUrl":"https://doi.org/10.1515/itit-2023-0005","url":null,"abstract":"Abstract Digital transformation affects many aspects of our everyday lives. This paper focuses on challenges and opportunities in the area of factory automation. It presents the layout and components of the Pilotfabrik Industrie 4.0 of TU Wien as an example of a modern, flexible, and highly digitized smart factory. Furthermore, the paper presents use cases that were implemented based on the available IoPT devices in the Pilotfabrik Industrie 4.0. The first use case aims to improve product quality by detecting chatter – a vibrational phenomenon in machine tools – and taking appropriate countermeasures. The second use case tries to predict tool breakage by closely monitoring the power consumption of the machine tool and, thus, reducing the probability of damaged products.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41553612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IoPT: internet of processes and things","authors":"Christoph Pollak","doi":"10.1515/itit-2023-0054","DOIUrl":"https://doi.org/10.1515/itit-2023-0054","url":null,"abstract":"","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43341551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diana Strutzenberger, M. Kunz, Lisa Magdalena Schuster, Juergen Mangler, Ronald Hinterbichler
Abstract In the course of efforts to develop and define uniform routines for the implementation of Internet of Things (IoT) in industrial environments, it has become essential to integrate industrial communication standards such as OPC UA in the context of IoT ontologies and implications for practical implementation. The Sensor, Observation, Sampling, and Actuator Ontology (SOSA) offers the possibility of mapping OPC UA services such as read and write functions to the underlying system in the sense of IoT. As an aid for the practical implementation of industrial use cases, an architecture based on the considerations of a generic modular system is proposed. Variable elements in the implementation of OPC UA interfaces are identified and discussed. The architectural approach is being evaluated by implementing an OPC UA server and supplementary applications in order to embed machine tools with different control systems in industrial production networks.
{"title":"An IoT architecture to integrate different machine tools into a compound OPC UA interface","authors":"Diana Strutzenberger, M. Kunz, Lisa Magdalena Schuster, Juergen Mangler, Ronald Hinterbichler","doi":"10.1515/itit-2023-0007","DOIUrl":"https://doi.org/10.1515/itit-2023-0007","url":null,"abstract":"Abstract In the course of efforts to develop and define uniform routines for the implementation of Internet of Things (IoT) in industrial environments, it has become essential to integrate industrial communication standards such as OPC UA in the context of IoT ontologies and implications for practical implementation. The Sensor, Observation, Sampling, and Actuator Ontology (SOSA) offers the possibility of mapping OPC UA services such as read and write functions to the underlying system in the sense of IoT. As an aid for the practical implementation of industrial use cases, an architecture based on the considerations of a generic modular system is proposed. Variable elements in the implementation of OPC UA interfaces are identified and discussed. The architectural approach is being evaluated by implementing an OPC UA server and supplementary applications in order to embed machine tools with different control systems in industrial production networks.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42274762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Achim Guldner, Maximilian Hoffmann, Christian Lohr, Rüdiger Machhamer, Lukas Malburg, Marlies Morgen, Stephanie C. Rodermund, Florian Schäfer, Lars Schaupeter, Jens Schneider, Felix Theusch, R. Bergmann, Guido Dartmann, Norbert Kuhn, Stefan Naumann, I. Timm, M. Vette-Steinkamp, B. Weyers
Abstract Digital transformation is both an opportunity and a challenge. To take advantage of this opportunity for humans and the environment, the transformation process must be understood as a design process that affects almost all areas of life. In this paper, we investigate AI-Based Self-Adaptive Cyber-Physical Process Systems (AI-CPPS) as an extension of the traditional CPS view. As contribution, we present a framework that addresses challenges that arise from recent literature. The aim of the AI-CPPS framework is to enable an adaptive integration of IoT environments with higher-level process-oriented systems. In addition, the framework integrates humans as actors into the system, which is often neglected by recent related approaches. The framework consists of three layers, i.e., processes, semantic modeling, and systems and actors, and we describe for each layer challenges and solution outlines for application. We also address the requirement to enable the integration of new networked devices under the premise of a targeted process that is optimally designed for humans, while profitably integrating AI and IoT. It is expected that AI-CPPS can contribute significantly to increasing sustainability and quality of life and offer solutions to pressing problems such as environmental protection, mobility, or demographic change. Thus, it is all the more important that the systems themselves do not become a driver of resource consumption.
{"title":"A framework for AI-based self-adaptive cyber-physical process systems","authors":"Achim Guldner, Maximilian Hoffmann, Christian Lohr, Rüdiger Machhamer, Lukas Malburg, Marlies Morgen, Stephanie C. Rodermund, Florian Schäfer, Lars Schaupeter, Jens Schneider, Felix Theusch, R. Bergmann, Guido Dartmann, Norbert Kuhn, Stefan Naumann, I. Timm, M. Vette-Steinkamp, B. Weyers","doi":"10.1515/itit-2023-0001","DOIUrl":"https://doi.org/10.1515/itit-2023-0001","url":null,"abstract":"Abstract Digital transformation is both an opportunity and a challenge. To take advantage of this opportunity for humans and the environment, the transformation process must be understood as a design process that affects almost all areas of life. In this paper, we investigate AI-Based Self-Adaptive Cyber-Physical Process Systems (AI-CPPS) as an extension of the traditional CPS view. As contribution, we present a framework that addresses challenges that arise from recent literature. The aim of the AI-CPPS framework is to enable an adaptive integration of IoT environments with higher-level process-oriented systems. In addition, the framework integrates humans as actors into the system, which is often neglected by recent related approaches. The framework consists of three layers, i.e., processes, semantic modeling, and systems and actors, and we describe for each layer challenges and solution outlines for application. We also address the requirement to enable the integration of new networked devices under the premise of a targeted process that is optimally designed for humans, while profitably integrating AI and IoT. It is expected that AI-CPPS can contribute significantly to increasing sustainability and quality of life and offer solutions to pressing problems such as environmental protection, mobility, or demographic change. Thus, it is all the more important that the systems themselves do not become a driver of resource consumption.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43928188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shima Hosseinzadeh, Marius Klemm, Georg Fischer, D. Fey
Abstract With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA.
摘要随着芯片尺寸的减小和在单个单元中存储多个位的能力，电阻式随机存取存储器（ReRAM）可以用来提高存储密度，使其成为下一代存储器的一种有前途的技术。然而，多级写入操作会受到诸如大延迟、高能耗和可靠性问题之类的损害。在本文中，我们研究了在元件和电路层面的瞬态模拟中，在1-晶体管-1-电阻器（1T1R）模型上影响“带验证算法的多级增量阶跃脉冲”（M-ISPVA）的不同机制，重点关注整个状态转换过程中的电阻控制和能量消耗。通过将M-ISPVA划分为触发期和控制期，我们发现晶体管在触发期内作为压控电阻在欧姆区工作，在控制期内作为电压控制限流器在饱和区工作。在触发周期中控制栅极电压可以将触发点移动到期望的写入电压，并且在控制周期中可以增加或减少每个脉冲的电阻步长以获得期望的电阻变化速度。此外，主要能量部分被消耗用于触发期间的复位操作和控制时段期间的设置操作。为了优化写入性能，在用目标读出电流和栅极电压定义电阻状态时必须采取额外的预防措施，重点是所有转换之间的均匀平衡延迟。直接多级写入操作显示67.5 % 延迟和62.5 % 与间接控制相比节能，但仅受到单向控制的影响，使其不可行。如果是4 k 位内存，更可靠的M-ISPVA面临几乎37 % 与基本ISPVA相比具有更高的延迟和能量。
{"title":"Optimizing multi-level ReRAM memory for low latency and low energy consumption","authors":"Shima Hosseinzadeh, Marius Klemm, Georg Fischer, D. Fey","doi":"10.1515/itit-2023-0022","DOIUrl":"https://doi.org/10.1515/itit-2023-0022","url":null,"abstract":"Abstract With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46377268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vincent Rietz, Christopher Münch, M. Mayahinia, M. Tahoori
Abstract Data-intensive applications have a huge demand on processor-memory communication. To reduce the amount of data transfers and their associated latency and energy, Compute-in-Memory (CIM) architectures can be used to perform operations ranging from simple binary operations to more complex operations such as additions and matrix-vector multiplications directly within the memory. However, proper adjustments to the memory hierarchy are needed to enable the execution of CIM operations. To evaluate the trade-off between the usage of different emerging non-volatile memories for CIM and conventional computing architectures, this work extends the widely used gem5 simulation framework with an extensible timing-aware main memory CIM simulation capability. This framework is used to analyze the performance of CIM extended main memory with various emerging memory technologies, namely Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), Redox-based RAM (ReRAM) and Phase-Change Memory (PCM). We evaluate different workloads from the PolyBench/C benchmark suite and other selected examples. In comparison to a processor-centric system, the results show a significant reduction in execution time for the majority of applications.
{"title":"Timing-accurate simulation framework for NVM-based compute-in-memory architecture exploration","authors":"Vincent Rietz, Christopher Münch, M. Mayahinia, M. Tahoori","doi":"10.1515/itit-2023-0019","DOIUrl":"https://doi.org/10.1515/itit-2023-0019","url":null,"abstract":"Abstract Data-intensive applications have a huge demand on processor-memory communication. To reduce the amount of data transfers and their associated latency and energy, Compute-in-Memory (CIM) architectures can be used to perform operations ranging from simple binary operations to more complex operations such as additions and matrix-vector multiplications directly within the memory. However, proper adjustments to the memory hierarchy are needed to enable the execution of CIM operations. To evaluate the trade-off between the usage of different emerging non-volatile memories for CIM and conventional computing architectures, this work extends the widely used gem5 simulation framework with an extensible timing-aware main memory CIM simulation capability. This framework is used to analyze the performance of CIM extended main memory with various emerging memory technologies, namely Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), Redox-based RAM (ReRAM) and Phase-Change Memory (PCM). We evaluate different workloads from the PolyBench/C benchmark suite and other selected examples. In comparison to a processor-centric system, the results show a significant reduction in execution time for the majority of applications.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45209748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract Resistive Random Access Memory (RRAM), also termed as memristors, is a non-volatile memory where information is stored in memory cells in the form of resistance. Due to its non-volatile resistive switching properties, memristors, in the form of crossbars, are used for storing information, neuromorpic computing, and logic synthesis. In spite of the wide range of applications, memristive crossbars suffer from a so-called sneak path problem which results in an erroneous reading of memristor’s state. Till date, no or very few logic synthesis approaches for in-memory computing have considered the sneak path problem during the realizations of Boolean functions. In other words, the effects of sneak paths on the Boolean function realizations in crossbars still remain an open problem. In this paper, we have addressed this issue. In particular, we study the impacts of function realizations in two memristive crossbar structures: Zero-Transistor-One-Resistor (0T1R) and One-Transistor-One-Resistor (1T1R) in the presence of sneak paths. Experimental analysis on IWLS and ISCAS-85 benchmarks shows that even in the presence of sneak paths, the 1T1R crossbar structures with multiple rows and columns are the most efficient as compared to the 1T1R structures with single row and multiple columns in terms of crossbar size and number of execution cycles.
{"title":"Impact of sneak paths on in-memory logic design in memristive crossbars","authors":"K. Datta, Arighna Deb, Abhoy Kole, R. Drechsler","doi":"10.1515/itit-2023-0020","DOIUrl":"https://doi.org/10.1515/itit-2023-0020","url":null,"abstract":"Abstract Resistive Random Access Memory (RRAM), also termed as memristors, is a non-volatile memory where information is stored in memory cells in the form of resistance. Due to its non-volatile resistive switching properties, memristors, in the form of crossbars, are used for storing information, neuromorpic computing, and logic synthesis. In spite of the wide range of applications, memristive crossbars suffer from a so-called sneak path problem which results in an erroneous reading of memristor’s state. Till date, no or very few logic synthesis approaches for in-memory computing have considered the sneak path problem during the realizations of Boolean functions. In other words, the effects of sneak paths on the Boolean function realizations in crossbars still remain an open problem. In this paper, we have addressed this issue. In particular, we study the impacts of function realizations in two memristive crossbar structures: Zero-Transistor-One-Resistor (0T1R) and One-Transistor-One-Resistor (1T1R) in the presence of sneak paths. Experimental analysis on IWLS and ISCAS-85 benchmarks shows that even in the presence of sneak paths, the 1T1R crossbar structures with multiple rows and columns are the most efficient as compared to the 1T1R structures with single row and multiple columns in terms of crossbar size and number of execution cycles.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49226140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abhinav Vishwakarma, Markus Fritscher, Amelie Hagelauer, M. Reichenbach
Abstract RRAM devices have recently seen wide-spread adoption into applications such as neural networks and storage elements since their inherent non-volatility and multi-bit-capability renders them a possible candidate for mitigating the von-Neumann bottleneck. Researchers often face difficulties when developing edge devices, since dealing with sensors detecting parameters such as humidity or temperature often requires large and power-consuming ADCs. We propose a possible mitigation, namely using a RRAM device in combination with a comparator circuit to form a basic block for threshold detection. This can be expanded towards programmable non-uniform sampling ADCs, significantly reducing both area and power consumption since significantly smaller bit-resolutions are required. We demonstrate how a comparator circuit designed in 130 nm technology can be reprogrammed by programming the incorporated RRAM device. Our proposed building block consumes 83 µW.
{"title":"An RRAM-based building block for reprogrammable non-uniform sampling ADCs","authors":"Abhinav Vishwakarma, Markus Fritscher, Amelie Hagelauer, M. Reichenbach","doi":"10.1515/itit-2023-0021","DOIUrl":"https://doi.org/10.1515/itit-2023-0021","url":null,"abstract":"Abstract RRAM devices have recently seen wide-spread adoption into applications such as neural networks and storage elements since their inherent non-volatility and multi-bit-capability renders them a possible candidate for mitigating the von-Neumann bottleneck. Researchers often face difficulties when developing edge devices, since dealing with sensors detecting parameters such as humidity or temperature often requires large and power-consuming ADCs. We propose a possible mitigation, namely using a RRAM device in combination with a comparator circuit to form a basic block for threshold detection. This can be expanded towards programmable non-uniform sampling ADCs, significantly reducing both area and power consumption since significantly smaller bit-resolutions are required. We demonstrate how a comparator circuit designed in 130 nm technology can be reprogrammed by programming the incorporated RRAM device. Our proposed building block consumes 83 µW.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":null,"pages":null},"PeriodicalIF":0.9,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42429321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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