Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199969
R. Libeskind-Hadas, C.L. Liu
A number of reconfiguration strategies have been proposed for increasing the yield of VLSI chips. In most cases the associated reconfiguration problems are NP-complete. Therefore, exhaustive search algorithms are generally used in order to find a solution when one exists. In this paper we present the notion of admissible sets and show how such sets can be used to significantly reduce the running time of many exhaustive search algorithms for reconfiguration problems. As an example, the authors find a class of admissible sets called excess-k critical sets that can be used in the design of fast search algorithms for the problem of reconfiguring redundant random access memories (RRAMs). They also consider applications to the problems of reconfiguring RRAMs with shared spares and reconfiguring redundant programmable logic arrays (RPLAs). Experimental results indicate that this approach is very powerful.<>
{"title":"Fast search algorithms for reconfiguration problems","authors":"R. Libeskind-Hadas, C.L. Liu","doi":"10.1109/DFTVS.1991.199969","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199969","url":null,"abstract":"A number of reconfiguration strategies have been proposed for increasing the yield of VLSI chips. In most cases the associated reconfiguration problems are NP-complete. Therefore, exhaustive search algorithms are generally used in order to find a solution when one exists. In this paper we present the notion of admissible sets and show how such sets can be used to significantly reduce the running time of many exhaustive search algorithms for reconfiguration problems. As an example, the authors find a class of admissible sets called excess-k critical sets that can be used in the design of fast search algorithms for the problem of reconfiguring redundant random access memories (RRAMs). They also consider applications to the problems of reconfiguring RRAMs with shared spares and reconfiguring redundant programmable logic arrays (RPLAs). Experimental results indicate that this approach is very powerful.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"5 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120858793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199967
S. Tewksbury
Several interconnection issues relating to faults and reliability are reviewed. Whereas the occurrence of opens in interconnections or shorts between interconnections is well understood within conventional models of digital systems, the faults originating from the analog characteristics of signals propagating across interconnection lines (particularly long lines) is less often discussed. However, such functional faults are likely to become increasingly important, not only due to the higher frequency operation of VLSI circuits but also due to the development of advanced packaging schemes using thin film technologies and multichip modules (MCMs). Such MCMs are characterized by line lengths much longer than typically encountered within VLSI circuits. The 'digital' signal being transmitted across a long VLSI or MCM interconnection line is represented here as an 'analog' signal which must be restored to a legitimate digital signal level at the specified times imposed by flip-flops. Incorrect restoration of the 'digital' signal at the far end is treated as a fault.<>
{"title":"Physical boundaries of performance: the interconnection perspective","authors":"S. Tewksbury","doi":"10.1109/DFTVS.1991.199967","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199967","url":null,"abstract":"Several interconnection issues relating to faults and reliability are reviewed. Whereas the occurrence of opens in interconnections or shorts between interconnections is well understood within conventional models of digital systems, the faults originating from the analog characteristics of signals propagating across interconnection lines (particularly long lines) is less often discussed. However, such functional faults are likely to become increasingly important, not only due to the higher frequency operation of VLSI circuits but also due to the development of advanced packaging schemes using thin film technologies and multichip modules (MCMs). Such MCMs are characterized by line lengths much longer than typically encountered within VLSI circuits. The 'digital' signal being transmitted across a long VLSI or MCM interconnection line is represented here as an 'analog' signal which must be restored to a legitimate digital signal level at the specified times imposed by flip-flops. Incorrect restoration of the 'digital' signal at the far end is treated as a fault.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199970
K. Raghunandan, F. Coakley
A time-multiplexed version of a binary tree channeliser can be implemented as a pipelined structure. Reconfiguration aspects of such a pipeline are considered in this paper. By developing a serial-module scheme for reconfiguration it is shown that the SM scheme offers better reliability than its equivalent binary trees. A digital filter is assumed as the basic processing element of the pipeline and the design trade-offs needed to implement a digital channeliser on a single chip using CMOS technology are described.<>
{"title":"Reconfiguration of time-multiplexed binary trees for satellite communication","authors":"K. Raghunandan, F. Coakley","doi":"10.1109/DFTVS.1991.199970","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199970","url":null,"abstract":"A time-multiplexed version of a binary tree channeliser can be implemented as a pipelined structure. Reconfiguration aspects of such a pipeline are considered in this paper. By developing a serial-module scheme for reconfiguration it is shown that the SM scheme offers better reliability than its equivalent binary trees. A digital filter is assumed as the basic processing element of the pipeline and the design trade-offs needed to implement a digital channeliser on a single chip using CMOS technology are described.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116902353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199973
A. Boubekeur, J. Patry, G. Saucier, J. Trilhe
ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a whole wafer instead of implementing it in VLSI chips each containing a few processing elements. Potential advantages of wafer scale integration over conventional VLSI systems include lower power, higher speed and small volume. However, WSI suffers from low yield. Redundancy and reconfiguration techniques are used to enhance the overall yield. Both of these have been implemented in ELSA. Three software packages have been developed to completely (re)configure the wafer and build a working target array.<>
{"title":"State-of-the-art of the wafer scale ELSA project","authors":"A. Boubekeur, J. Patry, G. Saucier, J. Trilhe","doi":"10.1109/DFTVS.1991.199973","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199973","url":null,"abstract":"ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a whole wafer instead of implementing it in VLSI chips each containing a few processing elements. Potential advantages of wafer scale integration over conventional VLSI systems include lower power, higher speed and small volume. However, WSI suffers from low yield. Redundancy and reconfiguration techniques are used to enhance the overall yield. Both of these have been implemented in ELSA. Three software packages have been developed to completely (re)configure the wafer and build a working target array.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123502728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199966
K. El-Ayat, R. Cahn, C. L. Chan, T. Speers
Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results.<>
{"title":"Array architecture for ATG with 100% fault coverage","authors":"K. El-Ayat, R. Cahn, C. L. Chan, T. Speers","doi":"10.1109/DFTVS.1991.199966","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199966","url":null,"abstract":"Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"35 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115730286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199952
A.W. Nordsieck, W. Yost, C. A. Young
Greater integration of avionics and flight control electronics with the need for higher reliability while maintaining or improving safety and availability and the need for reduced line maintenance costs are key drivers for the examination of a fault tolerant core computer architecture. The authors' approach is to develop a computer using commercially available microprocessors and memory with an ASIC performing the fault management. They use a tightly synchronous mesh architecture with distributed dynamic fault detection, isolation and reconfiguration. They examine key impediments to the achievements of fault tolerance for the mesh architecture.<>
{"title":"Key issues in the design of a fault-tolerant core avionics computer based on the mesh architecture","authors":"A.W. Nordsieck, W. Yost, C. A. Young","doi":"10.1109/DFTVS.1991.199952","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199952","url":null,"abstract":"Greater integration of avionics and flight control electronics with the need for higher reliability while maintaining or improving safety and availability and the need for reduced line maintenance costs are key drivers for the examination of a fault tolerant core computer architecture. The authors' approach is to develop a computer using commercially available microprocessors and memory with an ASIC performing the fault management. They use a tightly synchronous mesh architecture with distributed dynamic fault detection, isolation and reconfiguration. They examine key impediments to the achievements of fault tolerance for the mesh architecture.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199953
K. Bolding, L. Snyder
The chaos router is an adaptive nonminimal message router for multicomputers that is simple enough to compete with the fast, oblivious routers now in use in commercial machines. It improves on previous adaptive routers by using randomization, which eliminates the need for complex livelock protection and speeds the router. This randomization, however, greatly complicates the fault detection because there is no worstcase bound on the time required to deliver a message. Distinguishing between lost and very slow messages is difficult. A new method of fault detection is presented that applies not only to the chaos router but also to other adaptive routers as well. In addition, solutions to several practical fault diagnosis and recovery problems in the chaos router are presented. The presentation supports the claim that fault tolerance can be incorporated into a practical router without harming performance for the normal, fault-free cases.<>
{"title":"Overview of fault handling for the chaos router","authors":"K. Bolding, L. Snyder","doi":"10.1109/DFTVS.1991.199953","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199953","url":null,"abstract":"The chaos router is an adaptive nonminimal message router for multicomputers that is simple enough to compete with the fast, oblivious routers now in use in commercial machines. It improves on previous adaptive routers by using randomization, which eliminates the need for complex livelock protection and speeds the router. This randomization, however, greatly complicates the fault detection because there is no worstcase bound on the time required to deliver a message. Distinguishing between lost and very slow messages is difficult. A new method of fault detection is presented that applies not only to the chaos router but also to other adaptive routers as well. In addition, solutions to several practical fault diagnosis and recovery problems in the chaos router are presented. The presentation supports the claim that fault tolerance can be incorporated into a practical router without harming performance for the normal, fault-free cases.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129557935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199950
V. Piuri, M. Sami, R. Stefanelli
The problem of defect- and fault-tolerance in neural networks becomes increasingly important as a growing number of silicon implementations become available and mission-critical applications are envisioned. As an alternative to architecture-specific policies, intrinsic characteristics of the neural paradigm with respect to a functional error model are considered. In particular, this has been done for multilayered back-propagation networks, where both the classification errors induced by insurgence of a fault and the possibility of masking such errors through a repeated learning phase have been studied. Such abstract results can be used to analyze various silicon architectures implementing the multi-layered nets; physical faults are mapped onto the functional error classes, so as the evaluate both the intrinsic robustness of the various architectures and their critical areas, where ad-hoc design modifications or redundancies must be inserted to increase fault-tolerance properties. In the present paper some relevant implementations, representative of various design philosophies, are considered from this point of view.<>
{"title":"Neural networks on silicon: the mapping of hardware faults onto behavioral errors","authors":"V. Piuri, M. Sami, R. Stefanelli","doi":"10.1109/DFTVS.1991.199950","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199950","url":null,"abstract":"The problem of defect- and fault-tolerance in neural networks becomes increasingly important as a growing number of silicon implementations become available and mission-critical applications are envisioned. As an alternative to architecture-specific policies, intrinsic characteristics of the neural paradigm with respect to a functional error model are considered. In particular, this has been done for multilayered back-propagation networks, where both the classification errors induced by insurgence of a fault and the possibility of masking such errors through a repeated learning phase have been studied. Such abstract results can be used to analyze various silicon architectures implementing the multi-layered nets; physical faults are mapped onto the functional error classes, so as the evaluate both the intrinsic robustness of the various architectures and their critical areas, where ad-hoc design modifications or redundancies must be inserted to increase fault-tolerance properties. In the present paper some relevant implementations, representative of various design philosophies, are considered from this point of view.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129961848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199949
W. Shi, Ming-Feng Chang, W. Fuchs
Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.<>
由于缺陷分布和可重构算法的不规则性，可重构结构的良品率分析通常比较困难。在本文中，作者针对以下模型给出了一种分析可重构流水线良品率的方法：给定具有 m 个阶段的 n 条流水线，其中流水线的每个阶段都以恒定概率存在缺陷，并且为重新配置提供了备用导线，作者计算了重新配置后可收获流水线的预期百分比。通过将 "移位 "重新配置建模为网格中的加权链，并应用 poset 理论，他们给出了作为 m 和 n 函数的收获率上限和下限。
{"title":"Harvest rate of reconfigurable pipelines","authors":"W. Shi, Ming-Feng Chang, W. Fuchs","doi":"10.1109/DFTVS.1991.199949","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199949","url":null,"abstract":"Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131069224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199943
M. Patyra, Wojciech Maly
The methodology for circuit design of large area ICs (LAICs) is discussed. The partitioning and layout strategies for a self-testing, self-reconfigurating LAIC are formulated. It is shown that by proper layout design the circuit sensitivity to the manufacturing defects can be drastically decreased. A LAIC crossbar switch chip, which served as a vehicle for the experimental verification of the described ideas, was designed, fabricated and successfully tested. The built-in current (BIC) sensor was used in the fabricated crossbar IC in order to perform self-testing and self-reconfiguration purposes.<>
{"title":"Circuit design for a large area high-performance crossbar switch","authors":"M. Patyra, Wojciech Maly","doi":"10.1109/DFTVS.1991.199943","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199943","url":null,"abstract":"The methodology for circuit design of large area ICs (LAICs) is discussed. The partitioning and layout strategies for a self-testing, self-reconfigurating LAIC are formulated. It is shown that by proper layout design the circuit sensitivity to the manufacturing defects can be drastically decreased. A LAIC crossbar switch chip, which served as a vehicle for the experimental verification of the described ideas, was designed, fabricated and successfully tested. The built-in current (BIC) sensor was used in the fabricated crossbar IC in order to perform self-testing and self-reconfiguration purposes.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115362561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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