Capacitors have been made on textile substrates. Stainless steel yarns were used as electrodes. The dielectric material was a mixture of PEDOT and PSS. Stainless steel yarns were used as the electrodes. These capacitors are developed to be inserted in wearable textiles, a research field called smart textiles. After charging, a spontaneous discharge was observed lasting for several hours. By connecting a small resistance or even a short circuit for a certain time, it was observed that the voltage starts to rise afterwards when the load resistor or the short circuit was removed. This phenomenon is known as dielectric absorption. It was observed for the PEDOT:PSS cells that the voltage recovery is relatively high as compared to other materials.
{"title":"Dielectric absorption in PEDOT:PSS capacitors with stainless steel yarn electrodes in textile substrates","authors":"S. Odhiambo, M. De, C. Hertleer, L. Van","doi":"10.2298/fuee2201137o","DOIUrl":"https://doi.org/10.2298/fuee2201137o","url":null,"abstract":"Capacitors have been made on textile substrates. Stainless steel yarns were used as electrodes. The dielectric material was a mixture of PEDOT and PSS. Stainless steel yarns were used as the electrodes. These capacitors are developed to be inserted in wearable textiles, a research field called smart textiles. After charging, a spontaneous discharge was observed lasting for several hours. By connecting a small resistance or even a short circuit for a certain time, it was observed that the voltage starts to rise afterwards when the load resistor or the short circuit was removed. This phenomenon is known as dielectric absorption. It was observed for the PEDOT:PSS cells that the voltage recovery is relatively high as compared to other materials.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"57 3","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72623508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Marjanović, Aleksandra Stojković, A. Prijić, D. Danković, Z. Prijić
This paper presents a spatial SPICE model of a wireless sensor network node that enables simulation of performances in the steady-state and time-domain. The model includes constructive non-electrical parts of the node and a thermoelectric generator employing the thermoelectric effects. The simulation results are compared with the experiment to validate the model. It enabled the characterization of WSN nodes comprising different thermoelectric generators and heatsinks in terms of energy conversion efficiency.
{"title":"Spatial spice model of a wireless sensor network node based on a thermoelectric generator","authors":"M. Marjanović, Aleksandra Stojković, A. Prijić, D. Danković, Z. Prijić","doi":"10.2298/fuee2204513m","DOIUrl":"https://doi.org/10.2298/fuee2204513m","url":null,"abstract":"This paper presents a spatial SPICE model of a wireless sensor network node that enables simulation of performances in the steady-state and time-domain. The model includes constructive non-electrical parts of the node and a thermoelectric generator employing the thermoelectric effects. The simulation results are compared with the experiment to validate the model. It enabled the characterization of WSN nodes comprising different thermoelectric generators and heatsinks in terms of energy conversion efficiency.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"46 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75809211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Atanasković, N. Males-Ilic, Aleksandra Djorić, D. Budimir
Verification of two linearization methods, applied on asymmetrical two-way microstrip Doherty amplifier in experiment and on symmetrical two-way Doherty amplifier in simulation, is performed in this paper. The laboratory set-ups are formed to generate the baseband nonlinear linearization signals of the second-order. After being tuned in magnitude and phase in the digital domain the linearization signals modulate the second harmonics of fundamental carrier. In the first method, adequately processed signals are then inserted at the input and output of the main Doherty amplifier transistor, whereas in the second method, they are injected at the outputs of the Doherty main and auxiliary amplifier transistors. The experimental results are obtained for 64QAM digitally modulated signals. As a proof of concept, the linearization methods are also verified in simulation, for Doherty amplifier designed to work in 5G band below 6 GHz, utilizing 20 MHz LTE signal.
{"title":"Doherty amplifier linearization by digital injection methods","authors":"A. Atanasković, N. Males-Ilic, Aleksandra Djorić, D. Budimir","doi":"10.2298/fuee2204587a","DOIUrl":"https://doi.org/10.2298/fuee2204587a","url":null,"abstract":"Verification of two linearization methods, applied on asymmetrical two-way microstrip Doherty amplifier in experiment and on symmetrical two-way Doherty amplifier in simulation, is performed in this paper. The laboratory set-ups are formed to generate the baseband nonlinear linearization signals of the second-order. After being tuned in magnitude and phase in the digital domain the linearization signals modulate the second harmonics of fundamental carrier. In the first method, adequately processed signals are then inserted at the input and output of the main Doherty amplifier transistor, whereas in the second method, they are injected at the outputs of the Doherty main and auxiliary amplifier transistors. The experimental results are obtained for 64QAM digitally modulated signals. As a proof of concept, the linearization methods are also verified in simulation, for Doherty amplifier designed to work in 5G band below 6 GHz, utilizing 20 MHz LTE signal.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"18 4","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72507176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a new non-isolated high step-up interleaved cascade converter is presented. In comparison with the conventional cascade boost converter, the proposed converter has a higher voltage gain, lower input current ripple and reduced voltage stress for the switches and diodes. Besides, unlike the conventional cascade boost converter, in the proposed converter the input current is shared between inductors and hence the converter can be implemented with lower current rated inductors. Thus, the converter size and conduction losses are reduced and the efficiency is increased. The proposed converter is analyzed and experimental results of a 200W laboratory prototype are presented.
{"title":"A non-isolated high step-up converter with low ripple input current and reduced voltage stress","authors":"Asghar Salehi, M. Ershadi, M. Baharizadeh","doi":"10.2298/fuee2201093s","DOIUrl":"https://doi.org/10.2298/fuee2201093s","url":null,"abstract":"In this paper a new non-isolated high step-up interleaved cascade converter is presented. In comparison with the conventional cascade boost converter, the proposed converter has a higher voltage gain, lower input current ripple and reduced voltage stress for the switches and diodes. Besides, unlike the conventional cascade boost converter, in the proposed converter the input current is shared between inductors and hence the converter can be implemented with lower current rated inductors. Thus, the converter size and conduction losses are reduced and the efficiency is increased. The proposed converter is analyzed and experimental results of a 200W laboratory prototype are presented.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"19 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85363773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Srinivasa, M. Aditya, R. Karthik, CH. Manisai, S. Tharun, Girija Sravani
In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product).
{"title":"Design and performance analysis of full adder using 6-T XOR-XNOR cell","authors":"R. Srinivasa, M. Aditya, R. Karthik, CH. Manisai, S. Tharun, Girija Sravani","doi":"10.2298/fuee2202187r","DOIUrl":"https://doi.org/10.2298/fuee2202187r","url":null,"abstract":"In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product).","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"159 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83844272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anomaly-based intrusion detection systems identify abnormal computer network traffic based on deviations from the derived statistical model that describes the normal network behavior. The basic problem with anomaly detection is deciding what is considered normal. Supervised machine learning can be viewed as binary classification, since models are trained and tested on a data set containing a binary label to detect anomalies. Weighted k-Nearest Neighbor and Feedforward Neural Network are high-precision classifiers for decision-making. However, their decisions sometimes differ. In this paper, we present a WK-FNN hybrid model for the detection of the opposite decisions. It is shown that results can be improved with the xor bitwise operation. The sum of the binary ?ones? is used to decide whether additional alerts are activated or not.
{"title":"Wk-fnn design for detection of anomalies in the computer network traffic","authors":"D. Protić, Miomir Stanković, V. Antić","doi":"10.2298/fuee2202269p","DOIUrl":"https://doi.org/10.2298/fuee2202269p","url":null,"abstract":"Anomaly-based intrusion detection systems identify abnormal computer network traffic based on deviations from the derived statistical model that describes the normal network behavior. The basic problem with anomaly detection is deciding what is considered normal. Supervised machine learning can be viewed as binary classification, since models are trained and tested on a data set containing a binary label to detect anomalies. Weighted k-Nearest Neighbor and Feedforward Neural Network are high-precision classifiers for decision-making. However, their decisions sometimes differ. In this paper, we present a WK-FNN hybrid model for the detection of the opposite decisions. It is shown that results can be improved with the xor bitwise operation. The sum of the binary ?ones? is used to decide whether additional alerts are activated or not.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"1 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87994836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Dehbozorgi, Reza Akbari-Hasanjani, R. Sabbaghi‐Nadooshan
Since ancient times, people have tried to predict earthquakes using simple perceptions such as animal behavior. The prediction of the time and strength of an earthquake is of primary concern. In this study chaotic signal modeling is used based on noise and detecting anomalies before an earthquake using artificial neural networks (ANNs). Artificial neural networks are efficient tools for solving complex problems such as prediction and identification. In this study, the effective features of chaotic signal model is obtained considering noise and detection of anomalies five minutes before an earthquake occurrence. Neuro-fuzzy classifier and MLP neural network approaches showed acceptable accuracy of 84.6491% and 82.8947%, respectively. Results demonstrate that the proposed method is an effective seismic signal model based on noise and anomaly detection before an earthquake.
{"title":"Chaotic seismic signal modeling based on noise and earthquake anomaly detection","authors":"L. Dehbozorgi, Reza Akbari-Hasanjani, R. Sabbaghi‐Nadooshan","doi":"10.2298/fuee2204603d","DOIUrl":"https://doi.org/10.2298/fuee2204603d","url":null,"abstract":"Since ancient times, people have tried to predict earthquakes using simple perceptions such as animal behavior. The prediction of the time and strength of an earthquake is of primary concern. In this study chaotic signal modeling is used based on noise and detecting anomalies before an earthquake using artificial neural networks (ANNs). Artificial neural networks are efficient tools for solving complex problems such as prediction and identification. In this study, the effective features of chaotic signal model is obtained considering noise and detection of anomalies five minutes before an earthquake occurrence. Neuro-fuzzy classifier and MLP neural network approaches showed acceptable accuracy of 84.6491% and 82.8947%, respectively. Results demonstrate that the proposed method is an effective seismic signal model based on noise and anomaly detection before an earthquake.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"6 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90074744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.
{"title":"Area and power-efficient reconfigurable digital down converter on FPGA","authors":"Debarshi Datta, H. Dutta","doi":"10.2298/fuee2202243d","DOIUrl":"https://doi.org/10.2298/fuee2202243d","url":null,"abstract":"This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"44 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74138831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The satisfaction of electricity customers and environmental constraints imposed have made the trend towards renewable energies more essential given its advantages such as reducing power losses and enhancing voltage profiles. This study addresses the optimal sizing and setting of Photovoltaic Distributed Generator (PVDG) connected to Radial Distribution Network (RDN) using various novel optimization algorithms. These algorithms are implemented to minimize the Multi-Objective Function (MOF), which devoted to optimize the Total Active Power Loss (TAPL), the Total Voltage Deviation (TVD), and the overcurrent protection relays (OCRs)?s Total Operation Time (TOT). The effectiveness of the proposed algorithms is validated on the test system standard IEEE 33-bus RDN. In this paper is presented a recent meta-heuristic optimization algorithm of the Slime Mould Algorithm (SMA), where the results reveal its effectiveness and robustness among all the applied optimization algorithms, in identifying the optimal allocation (locate and size) of the PVDG units into RDN for mitigating the power losses, enhance the RDN system's voltage profiles and improve the overcurrent protection system. Accordingly, the SMA approach can be a very favorable algorithm to cope with the optimal PVDG allocation problem.
{"title":"Optimal location and sizing of multiple distributed generators in radial distribution network using metaheuristic optimization algorithms","authors":"N. Belbachir, M. Zellagui, B. Bekkouche","doi":"10.2298/fuee2202229b","DOIUrl":"https://doi.org/10.2298/fuee2202229b","url":null,"abstract":"The satisfaction of electricity customers and environmental constraints imposed have made the trend towards renewable energies more essential given its advantages such as reducing power losses and enhancing voltage profiles. This study addresses the optimal sizing and setting of Photovoltaic Distributed Generator (PVDG) connected to Radial Distribution Network (RDN) using various novel optimization algorithms. These algorithms are implemented to minimize the Multi-Objective Function (MOF), which devoted to optimize the Total Active Power Loss (TAPL), the Total Voltage Deviation (TVD), and the overcurrent protection relays (OCRs)?s Total Operation Time (TOT). The effectiveness of the proposed algorithms is validated on the test system standard IEEE 33-bus RDN. In this paper is presented a recent meta-heuristic optimization algorithm of the Slime Mould Algorithm (SMA), where the results reveal its effectiveness and robustness among all the applied optimization algorithms, in identifying the optimal allocation (locate and size) of the PVDG units into RDN for mitigating the power losses, enhance the RDN system's voltage profiles and improve the overcurrent protection system. Accordingly, the SMA approach can be a very favorable algorithm to cope with the optimal PVDG allocation problem.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"120 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75792648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nataša J. Nešić, N. Dončov, Slavko Rupčić, V. Mandric-Radivojevic
In this paper, the impact of an electromagnetic absorber inside a protective metal enclosure is analyzed. The absorber is put inside the enclosure in order to improve its shielding effectiveness, especially at the first resonant frequency. Different absorber's sheet positions inside the enclosure are analyzed. The absorber sheet dimensions are fitted to correspond the enclosure's walls. The experimental procedure is conducted in a semi-anechoic room. The numerical TLM simulations of the EM filed distribution inside enclosure are conducted in order to consider position of the absorber sheet on different walls.
{"title":"Experimental shielding effectiveness study of metal enclosure with electromagnetic absorber inside","authors":"Nataša J. Nešić, N. Dončov, Slavko Rupčić, V. Mandric-Radivojevic","doi":"10.2298/fuee2203455n","DOIUrl":"https://doi.org/10.2298/fuee2203455n","url":null,"abstract":"In this paper, the impact of an electromagnetic absorber inside a protective metal enclosure is analyzed. The absorber is put inside the enclosure in order to improve its shielding effectiveness, especially at the first resonant frequency. Different absorber's sheet positions inside the enclosure are analyzed. The absorber sheet dimensions are fitted to correspond the enclosure's walls. The experimental procedure is conducted in a semi-anechoic room. The numerical TLM simulations of the EM filed distribution inside enclosure are conducted in order to consider position of the absorber sheet on different walls.","PeriodicalId":44296,"journal":{"name":"Facta Universitatis-Series Electronics and Energetics","volume":"2 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88787936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：