Efficiently mapping binary functions to adiabatic quantum computers is an important problem because the resulting circuits can be used as oracles in Grover's algorithm. This paper presents a method for mapping binary functions to a two-dimensional grid of qubits with nearest neighbor interactions which is used in a prototype from D-Wave Systems. This is done by writing the binary function in a special form. This allows the binary function to be implemented by converting each gate into a 3-local Hamiltonian. These 3-local Hamiltonians are then converted into two-local Hamiltonians which are mapped to the grid of qubits.
{"title":"Mapping Binary Functions to a Practical Adiabatic Quantum Computer","authors":"David J. Rosenbaum, M. Perkowski","doi":"10.1109/ISMVL.2010.57","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.57","url":null,"abstract":"Efficiently mapping binary functions to adiabatic quantum computers is an important problem because the resulting circuits can be used as oracles in Grover's algorithm. This paper presents a method for mapping binary functions to a two-dimensional grid of qubits with nearest neighbor interactions which is used in a prototype from D-Wave Systems. This is done by writing the binary function in a special form. This allows the binary function to be implemented by converting each gate into a 3-local Hamiltonian. These 3-local Hamiltonians are then converted into two-local Hamiltonians which are mapped to the grid of qubits.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122541530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The task of modeling and reasoning about real-world problems often involves analyzing overconstrained representations, where not all constraints of a problem can be simultaneously satisfied. The need to analyze over-constrained (or unsatisfiable) problems occurs in many settings, including data and knowledge bases, artificial intelligence, applied formal methods, operations research and description logics. In most cases, the problem to solve is related with some form of minimal unsatisfiability, i.e. an irreducible set of constraints that explains unsatisfiability. This paper provides an overview of some of the computational problems related with minimal unsatisfiability in Boolean logic, including the identification of one minimal unsatisfiable sub-formula and the identification of all minimal unsatisfiable sub-formulas. In addition, the paper briefly overviews practical applications of minimal unsatisfiability. Finally, the paper highlights recent work on minimal unsatisfiability in other domains.
{"title":"Minimal Unsatisfiability: Models, Algorithms and Applications (Invited Paper)","authors":"Joao Marques-Silva","doi":"10.1109/ISMVL.2010.11","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.11","url":null,"abstract":"The task of modeling and reasoning about real-world problems often involves analyzing overconstrained representations, where not all constraints of a problem can be simultaneously satisfied. The need to analyze over-constrained (or unsatisfiable) problems occurs in many settings, including data and knowledge bases, artificial intelligence, applied formal methods, operations research and description logics. In most cases, the problem to solve is related with some form of minimal unsatisfiability, i.e. an irreducible set of constraints that explains unsatisfiability. This paper provides an overview of some of the computational problems related with minimal unsatisfiability in Boolean logic, including the identification of one minimal unsatisfiable sub-formula and the identification of all minimal unsatisfiable sub-formulas. In addition, the paper briefly overviews practical applications of minimal unsatisfiability. Finally, the paper highlights recent work on minimal unsatisfiability in other domains.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125496240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper shows a direct correspondence between the first partial derivatives of a continuous Archimedean triangular norm and the first derivatives of its additive generator. An explicit formula for the additive generator is obtained. Application of the result is demonstrated on the problem of convex combinations of strict triangular norms.
{"title":"Reconstruction of Additive Generators from Partial Derivatives of Continuous Archimedean t-Norms","authors":"M. Navara, Milan Petrík, Peter Sarkoci","doi":"10.1109/ISMVL.2010.52","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.52","url":null,"abstract":"The paper shows a direct correspondence between the first partial derivatives of a continuous Archimedean triangular norm and the first derivatives of its additive generator. An explicit formula for the additive generator is obtained. Application of the result is demonstrated on the problem of convex combinations of strict triangular norms.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127592139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Using the lattice-theoretic version of the Euler characteristic introduced by V. Klee and G.-C. Rota, we define the Euler characteristic of a formula in Gödel logic (over finitely or infinitely many truth-values). We then prove that the information encoded by the Euler characteristic is classical, i.e., coincides with the analogous notion defined over Boolean logic. Building on this, we define k-valued versions of the Euler characteristic of a formula φ, for each integer k ≥ 2, and prove that they indeed provide information about the logical status of φ in Gödel k-valued logic. Specifically, our main result shows that the k-valued Euler characteristic is an invariant that separates k-valued tautologies from non-tautologies.
利用V. Klee和g . c . c .引入的欧拉特性的格论版本。首先，我们定义了一个公式在Gödel逻辑中的欧拉特性(在有限或无限多个真值上)。然后，我们证明了由欧拉特征编码的信息是经典的，即与布尔逻辑上定义的类似概念一致。在此基础上，我们定义公式φ的k值欧拉特征，对于每个整数k ≥2，并证明它们确实提供了φ的逻辑状态信息;在Gödel k值逻辑。具体地说，我们的主要结果表明，k值欧拉特征是区分k值重言式和非重言式的不变量。
{"title":"The Euler Characteristic of a Formula in Godel Logic","authors":"P. Codara, O. D'Antona, V. Marra","doi":"10.1109/ISMVL.2010.28","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.28","url":null,"abstract":"Using the lattice-theoretic version of the Euler characteristic introduced by V. Klee and G.-C. Rota, we define the Euler characteristic of a formula in Gödel logic (over finitely or infinitely many truth-values). We then prove that the information encoded by the Euler characteristic is classical, i.e., coincides with the analogous notion defined over Boolean logic. Building on this, we define k-valued versions of the Euler characteristic of a formula φ, for each integer k ≥ 2, and prove that they indeed provide information about the logical status of φ in Gödel k-valued logic. Specifically, our main result shows that the k-valued Euler characteristic is an invariant that separates k-valued tautologies from non-tautologies.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116368733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Synchronous multiple-valued networks are a discrete-space discrete-time model of the gene regulatory network of living cells. In this model, cell types are represented by the cycles in the state transition graph of a network, called attractors. When the effect of a disease or a mutation on a cell is studied, attractors have to be re-computed each time a fault is injected in the model. This motivates research on algorithms for finding attractors. Existing decision diagram-based approaches have limited capacity due to the excessive memory requirements of decision diagrams. Simulation-based approaches can be applied to larger networks, however, they are incomplete. We present an algorithm for finding attractors which uses a SAT-based bounded model checking. Our model checking approach exploits the deterministic nature of the network model to reduce runtime. Although the idea of applying model checking to the analysis of gene regulatory networks is not new, to our best knowledge, we are the first to use it for computing all attractors in a model. The efficiency of the presented algorithm is evaluated by analyzing 7 networks models of real biological processes as well as 35.000 randomly generated 4-valued networks. The results show that our approach has a potential to handle an order of magnitude larger models than currently possible.
{"title":"Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-Based Bounded Model Checking","authors":"E. Dubrova, Ming Liu, M. Teslenko","doi":"10.1109/ISMVL.2010.35","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.35","url":null,"abstract":"Synchronous multiple-valued networks are a discrete-space discrete-time model of the gene regulatory network of living cells. In this model, cell types are represented by the cycles in the state transition graph of a network, called attractors. When the effect of a disease or a mutation on a cell is studied, attractors have to be re-computed each time a fault is injected in the model. This motivates research on algorithms for finding attractors. Existing decision diagram-based approaches have limited capacity due to the excessive memory requirements of decision diagrams. Simulation-based approaches can be applied to larger networks, however, they are incomplete. We present an algorithm for finding attractors which uses a SAT-based bounded model checking. Our model checking approach exploits the deterministic nature of the network model to reduce runtime. Although the idea of applying model checking to the analysis of gene regulatory networks is not new, to our best knowledge, we are the first to use it for computing all attractors in a model. The efficiency of the presented algorithm is evaluated by analyzing 7 networks models of real biological processes as well as 35.000 randomly generated 4-valued networks. The results show that our approach has a potential to handle an order of magnitude larger models than currently possible.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126119833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Behounek, P. Cintula, Ulrich Bodenhofer, Susanne Saminger-Platz, Peter Sarkoci
The paper studies graded properties of MTL_Delta-valued binary connectives, focusing on conjunctive connectives such as t-norms, uninorms, aggregation operators, or quasicopulas. The graded properties studied include monotony, a generalized Lipschitz property, unit and null elements, commutativity, associativity, and idempotence. Finally, a graded notion of dominance is investigated and applied to transmission of graded properties of fuzzy relations. The framework of Fuzzy Class Theory (or higher-order fuzzy logic) is employed as a tool for easy derivation of graded theorems on the connectives.
{"title":"On a Graded Notion of t-Norm and Dominance","authors":"L. Behounek, P. Cintula, Ulrich Bodenhofer, Susanne Saminger-Platz, Peter Sarkoci","doi":"10.1109/ISMVL.2010.21","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.21","url":null,"abstract":"The paper studies graded properties of MTL_Delta-valued binary connectives, focusing on conjunctive connectives such as t-norms, uninorms, aggregation operators, or quasicopulas. The graded properties studied include monotony, a generalized Lipschitz property, unit and null elements, commutativity, associativity, and idempotence. Finally, a graded notion of dominance is investigated and applied to transmission of graded properties of fuzzy relations. The framework of Fuzzy Class Theory (or higher-order fuzzy logic) is employed as a tool for easy derivation of graded theorems on the connectives.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Perkowski, Nouraddin Alhagi, M. Lukac, N. Saxena, S. Blakely
This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.
{"title":"Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates","authors":"M. Perkowski, Nouraddin Alhagi, M. Lukac, N. Saxena, S. Blakely","doi":"10.1109/ISMVL.2010.53","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.53","url":null,"abstract":"This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134113176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the present paper we extend the results of cite{BuCa} by completely characterizing dual canonical subvarieties of BL-algebras. These are subvarieties of algebras that satisfy the equation $x^k=x^{k+1}$ for some integer $kge 1$. As a corollary we get a full description of subvarieties of BL-algebras that admit completions.
{"title":"Completions in Subvarieties of BL-Algebras","authors":"M. Busaniche, L. Cabrer","doi":"10.1109/ISMVL.2010.24","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.24","url":null,"abstract":"In the present paper we extend the results of cite{BuCa} by completely characterizing dual canonical subvarieties of BL-algebras. These are subvarieties of algebras that satisfy the equation $x^k=x^{k+1}$ for some integer $kge 1$. As a corollary we get a full description of subvarieties of BL-algebras that admit completions.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122451426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present low-voltage multiple-valued gates. The low voltage gates may operate at a supply voltage below 250mV. We utilize the ultra low voltage CMOS logic style [1][2] to implement simple multiple-valued circuits. The radix used is determined by the supply voltage and is limited to 4 for a supply voltage equal to 250mV . Simulated data presented are valid for a ST 90nm CMOS process.
{"title":"Low Voltage Semi Floating-Gate Binary to Multiple-Value and Multiple-Value to Binary Converters","authors":"Y. Berg","doi":"10.1109/ISMVL.2010.22","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.22","url":null,"abstract":"In this paper we present low-voltage multiple-valued gates. The low voltage gates may operate at a supply voltage below 250mV. We utilize the ultra low voltage CMOS logic style [1][2] to implement simple multiple-valued circuits. The radix used is determined by the supply voltage and is limited to 4 for a supply voltage equal to 250mV . Simulated data presented are valid for a ST 90nm CMOS process.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124748304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several classes of optimization problems have been considered. In this context Pseudo Kronecker Expressions (PSDKROs) are highly relevant, since they allow very compact representations while the optimization can be carried out efficiently. But the size of PSDKROs depends on a chosen order in which the variables are considered. In this paper an Evolutionary Algorithm (EA) is presented for determining a good decomposition order for PSDKROs. Experimental results are given to demonstrate the efficiency of the approach.
{"title":"An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions","authors":"A. Finder, R. Drechsler","doi":"10.1109/ISMVL.2010.36","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.36","url":null,"abstract":"Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several classes of optimization problems have been considered. In this context Pseudo Kronecker Expressions (PSDKROs) are highly relevant, since they allow very compact representations while the optimization can be carried out efficiently. But the size of PSDKROs depends on a chosen order in which the variables are considered. In this paper an Evolutionary Algorithm (EA) is presented for determining a good decomposition order for PSDKROs. Experimental results are given to demonstrate the efficiency of the approach.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116809800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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