This paper is inspired by the paper of Tarasov in which he investigates maximal partial clones on a two-element set. It happens that the approach of Tarasov can be translated into the language of hyperclone theory. He introduced a notion of quasicomposition which assigns to extended hyperoperations extension of their composition. We introduce a new operation in the set of extended hyperoperation and define a quasiclone as a composition closed set of extended hyperoperations containing all projections which is closed with respect to the new operation. For a Galois connection between sets of extended hyperoperations and power relations, we prove that the set of all extended hyperoperations e-preserving every relation is a quasiclone and that each quasiclone is of the form ePolR for a set R of relations on the power set of A without empty-set. Finally, we re-state results of Tarasov in hyperclone framework.
{"title":"Galois Connection for Hyperclones","authors":"Hajime Machida, J. Pantović, I. Rosenberg","doi":"10.1109/ISMVL.2010.45","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.45","url":null,"abstract":"This paper is inspired by the paper of Tarasov in which he investigates maximal partial clones on a two-element set. It happens that the approach of Tarasov can be translated into the language of hyperclone theory. He introduced a notion of quasicomposition which assigns to extended hyperoperations extension of their composition. We introduce a new operation in the set of extended hyperoperation and define a quasiclone as a composition closed set of extended hyperoperations containing all projections which is closed with respect to the new operation. For a Galois connection between sets of extended hyperoperations and power relations, we prove that the set of all extended hyperoperations e-preserving every relation is a quasiclone and that each quasiclone is of the form ePolR for a set R of relations on the power set of A without empty-set. Finally, we re-state results of Tarasov in hyperclone framework.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122459057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates the significance of truth-functional three valued logics of ill-known sets described by pairs of disjoint (or pairs of nested) subsets. In particular the case of three-valued logics of rough sets is studied in more details, showing that, while the mathematical underpinnings are sound, the relevance of these logics for reasoning about data-tables containing incomplete descriptions of objects is questionable.
{"title":"Truth-Functionality, Rough Sets and Three-Valued Logics","authors":"D. Ciucci, D. Dubois","doi":"10.1109/ISMVL.2010.26","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.26","url":null,"abstract":"This paper investigates the significance of truth-functional three valued logics of ill-known sets described by pairs of disjoint (or pairs of nested) subsets. In particular the case of three-valued logics of rough sets is studied in more details, showing that, while the mathematical underpinnings are sound, the relevance of these logics for reasoning about data-tables containing incomplete descriptions of objects is questionable.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132262651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work and generates a cascade of inverted-control-Toffoli gates from the ESOP representation of a multi-output function. The algorithm first generates a circuit with n + m lines, where n and m are the number of inputs and outputs, respectively. A set of gate transformations are applied to the circuits to remove some of the output lines. The improvements of this new algorithm are twofold: most NOT gates are eliminated and the number of lines is reduced. A significant reduction is the quantum cost of the resulting networks can be observed.
{"title":"ESOP-Based Toffoli Network Generation with Transformations","authors":"Yasaman Sanaee, G. Dueck","doi":"10.1109/ISMVL.2010.58","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.58","url":null,"abstract":"In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work and generates a cascade of inverted-control-Toffoli gates from the ESOP representation of a multi-output function. The algorithm first generates a circuit with n + m lines, where n and m are the number of inputs and outputs, respectively. A set of gate transformations are applied to the circuits to remove some of the output lines. The improvements of this new algorithm are twofold: most NOT gates are eliminated and the number of lines is reduced. A significant reduction is the quantum cost of the resulting networks can be observed.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124060373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents one-color two-phase asynchronous communication links for a high-performance asynchronous system. The proposed communication links based on simple one-color encoding is effectively connected to processing cores. Since the communication is controlled by simultaneous handshaking, where a request and an acknowledge signals are overlapped, the number of communication steps is greatly reduced. Moreover, the use of multiple-valued current-mode circuit makes it possible to realize asynchronous communication with just two wires. The asynchronous transmission circuits based on the proposed encoding are implemented and evaluated using HSPICE simulation with 0.13 um CMOS technology. Throughput of the proposed 2-bit transmission attains 0.45Gbps/wire, which is three times faster than that of the conventional two-color two-phase transmission.
本文提出了一种高性能异步系统的单色两相异步通信链路。所提出的基于简单单色编码的通信链路有效地连接到处理核心。由于通信是由同时握手控制的，其中请求和确认信号重叠，因此大大减少了通信步骤的数量。此外，多值电流模式电路的使用使得仅用两根电线就可以实现异步通信。采用0.13 um CMOS技术实现了基于该编码的异步传输电路，并进行了HSPICE仿真。提出的2位传输吞吐量达到0.45Gbps/线，比传统的双色两相传输速度快3倍。
{"title":"One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control","authors":"Atsushi Matsumoto, N. Onizawa, T. Hanyu","doi":"10.1109/ISMVL.2010.47","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.47","url":null,"abstract":"This paper presents one-color two-phase asynchronous communication links for a high-performance asynchronous system. The proposed communication links based on simple one-color encoding is effectively connected to processing cores. Since the communication is controlled by simultaneous handshaking, where a request and an acknowledge signals are overlapped, the number of communication steps is greatly reduced. Moreover, the use of multiple-valued current-mode circuit makes it possible to realize asynchronous communication with just two wires. The asynchronous transmission circuits based on the proposed encoding are implemented and evaluated using HSPICE simulation with 0.13 um CMOS technology. Throughput of the proposed 2-bit transmission attains 0.45Gbps/wire, which is three times faster than that of the conventional two-color two-phase transmission.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130283024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We outline DL-Media, an ontology mediated multimedia information retrieval system, which combines logic-based retrieval with multimedia feature-based similarity retrieval. An ontology layer is used to define (in terms of a fuzzy description logic) the relevant abstract concepts and relations of the application domain, while a content-based multimedia retrieval system is used for feature-based retrieval.
{"title":"An Ontology Mediated Multimedia Information Retrieval System","authors":"U. Straccia","doi":"10.1109/ISMVL.2010.65","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.65","url":null,"abstract":"We outline DL-Media, an ontology mediated multimedia information retrieval system, which combines logic-based retrieval with multimedia feature-based similarity retrieval. An ontology layer is used to define (in terms of a fuzzy description logic) the relevant abstract concepts and relations of the application domain, while a content-based multimedia retrieval system is used for feature-based retrieval.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129669228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A static current-source control technique in a multiple-valued current-mode (MVCM) circuit is proposed for a low-energy pipelined system. A current-control block embedded in each pipeline stage generates current control signals, which minimizes the amount of current flows depending on a given condition. The use of this current-source control technique makes it possible to reduce the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a pipelined MVCM multiplier is confirmed by using HSPICE simulation under 0.13um CMOS technology. The MVCM circuit using the proposed technique achieves 65.1% power reduction compared with a conventional MVCM implementation at the operating frequency of 100MHz and 26.5% reduction at 500MHz with 6.88% area overhead.
{"title":"Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control","authors":"M. Natsui, T. Arimitsu, T. Hanyu","doi":"10.1109/ISMVL.2010.51","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.51","url":null,"abstract":"A static current-source control technique in a multiple-valued current-mode (MVCM) circuit is proposed for a low-energy pipelined system. A current-control block embedded in each pipeline stage generates current control signals, which minimizes the amount of current flows depending on a given condition. The use of this current-source control technique makes it possible to reduce the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a pipelined MVCM multiplier is confirmed by using HSPICE simulation under 0.13um CMOS technology. The MVCM circuit using the proposed technique achieves 65.1% power reduction compared with a conventional MVCM implementation at the operating frequency of 100MHz and 26.5% reduction at 500MHz with 6.88% area overhead.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121050904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Let A and B be integers such that A less than or equal to B. An n-variable interval function IN[n:A, B] is a mapping from{0,1}^n to {0,1}, where IN[n:A, B](X)=1 iff X is in the interval [A, B]. Such function is useful for packet classification in the internet, network intrusion detection system, etc. This paper considers the number of products to represent interval functions by sum-of-products expressions with two-valued and four-valued variables. It shows that to represent any interval function of n variables, an SOP with two-valued variables requires up to 2(n-2) products, while an SOP with four-valued variables requires at most n-1 products. These bounds are useful to estimate the size of a content addressable memory (CAM).
{"title":"On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.2010.59","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.59","url":null,"abstract":"Let A and B be integers such that A less than or equal to B. An n-variable interval function IN[n:A, B] is a mapping from{0,1}^n to {0,1}, where IN[n:A, B](X)=1 iff X is in the interval [A, B]. Such function is useful for packet classification in the internet, network intrusion detection system, etc. This paper considers the number of products to represent interval functions by sum-of-products expressions with two-valued and four-valued variables. It shows that to represent any interval function of n variables, an SOP with two-valued variables requires up to 2(n-2) products, while an SOP with four-valued variables requires at most n-1 products. These bounds are useful to estimate the size of a content addressable memory (CAM).","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115533928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reversible logic has become an active research area due to its various applications in emerging technologies, like quantum computing, low power design, optical computing, DNA computing, or nanotechnologies. As a result, complex reversible circuits containing thousands of gates can be efficiently synthesized, today. However, this also increases the probability of design errors. While for the detection of errors already a couple of simulation-based or formal verification techniques have been proposed for reversible logic. Research in the domain of debugging is still at the beginning. In this paper, we present an automatic debugging approach for reversible logic which is based on simulation. We show that a particular error in a gate always requires a counterexample leading to a concrete gate input pattern. By simulating all counterexamples and checking for these input patterns, irrelevant gates (i.e. gates that do not contain an error) can be excluded. Experiments show, that applying the proposed approach leads to speed-ups of up to five orders of magnitude. Furthermore, the number of error candidates can be reduced in comparison to previous work.
{"title":"Efficient Simulation-Based Debugging of Reversible Logic","authors":"Stefan Frehse, R. Wille, R. Drechsler","doi":"10.1109/ISMVL.2010.37","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.37","url":null,"abstract":"Reversible logic has become an active research area due to its various applications in emerging technologies, like quantum computing, low power design, optical computing, DNA computing, or nanotechnologies. As a result, complex reversible circuits containing thousands of gates can be efficiently synthesized, today. However, this also increases the probability of design errors. While for the detection of errors already a couple of simulation-based or formal verification techniques have been proposed for reversible logic. Research in the domain of debugging is still at the beginning. In this paper, we present an automatic debugging approach for reversible logic which is based on simulation. We show that a particular error in a gate always requires a counterexample leading to a concrete gate input pattern. By simulating all counterexamples and checking for these input patterns, irrelevant gates (i.e. gates that do not contain an error) can be excluded. Experiments show, that applying the proposed approach leads to speed-ups of up to five orders of magnitude. Furthermore, the number of error candidates can be reduced in comparison to previous work.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116277994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a theory of multiple-valued threshold functions over the field of complex numbers is further developed. k-valued threshold functions over the field of complex numbers can be learned using a single multi-valued neuron (MVN). We propose a new approach for the projection of a k-valued function, which is not a threshold one, to m-valued logic (m≫k), where this function becomes a partially defined m-valued threshold function and can be learned by a single MVN. To build this projection, a periodic activation function for the MVN is used. This new activation function and a modified learning algorithm make it possible to learn nonlinearly separable multiple-valued functions using a single MVN.
{"title":"Learning of the Non-threshold Functions of Multiple-Valued Logic by a Single Multi-valued Neuron with a Periodic Activation Function","authors":"I. Aizenberg","doi":"10.1109/ISMVL.2010.15","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.15","url":null,"abstract":"In this paper, a theory of multiple-valued threshold functions over the field of complex numbers is further developed. k-valued threshold functions over the field of complex numbers can be learned using a single multi-valued neuron (MVN). We propose a new approach for the projection of a k-valued function, which is not a threshold one, to m-valued logic (m≫k), where this function becomes a partially defined m-valued threshold function and can be learned by a single MVN. To build this projection, a periodic activation function for the MVN is used. This new activation function and a modified learning algorithm make it possible to learn nonlinearly separable multiple-valued functions using a single MVN.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130575998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work we introduce a particular kind of quantum operations called polynomial quantum operations that allow us to represent the basic operations of the standard Product MV -algebra. Consequently, these operations can be treated as quantum computational gates in the powerful model of quantum computation given by “quantum operations - density operators”.
{"title":"Representing Fuzzy Structures in Quantum Computation with Mixed States","authors":"H. Freytes, R. Giuntini, G. Sergioli, A. Aricò","doi":"10.1109/ISMVL.2010.38","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.38","url":null,"abstract":"In this work we introduce a particular kind of quantum operations called polynomial quantum operations that allow us to represent the basic operations of the standard Product MV -algebra. Consequently, these operations can be treated as quantum computational gates in the powerful model of quantum computation given by “quantum operations - density operators”.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123294589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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