The paper is a study of a querying approach to the integration of imperfect information, using the framework offered by the multivalued logics based on the algebraic concept of bilattice. In particular, the queries are seen as integrating rules built with operations provided by the connectives of bilattices. An important aspect arising in the context of query evaluation is its efficiency, therefore we equally tackle the problem of query equivalence, which traditionally constitutes one of the central problems in query optimization. The paper provides results that characterize the query containment and equivalence problems syntactically, which naturally lead to algorithms for testing for equivalence of queries integrating imperfect information in the context of bilattices. Finally we study the complexity of query equivalence and the data complexity of query evaluation.
{"title":"Queries with Multivalued Logic-Based Semantics for Imperfect Information Fusion","authors":"D. Stamate","doi":"10.1109/ISMVL.2010.62","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.62","url":null,"abstract":"The paper is a study of a querying approach to the integration of imperfect information, using the framework offered by the multivalued logics based on the algebraic concept of bilattice. In particular, the queries are seen as integrating rules built with operations provided by the connectives of bilattices. An important aspect arising in the context of query evaluation is its efficiency, therefore we equally tackle the problem of query equivalence, which traditionally constitutes one of the central problems in query optimization. The paper provides results that characterize the query containment and equivalence problems syntactically, which naturally lead to algorithms for testing for equivalence of queries integrating imperfect information in the context of bilattices. Finally we study the complexity of query equivalence and the data complexity of query evaluation.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115131888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A bit-serial multiple-valued reconfigurable VLSI using current-mode logic circuits has been proposed. A Differential-Pair Circuit (DPC) is used as a basic component of a cell, so that the static power is dissipated even in the nonactive cells. To solve the problem, autonomous ON/OFF control of the current sources is presented based on superposition of bit-serial data and current-source control signals. In the proposed switched current control technique, the static power dissipation can be greatly reduced because current sources in nonactive circuit blocks are turned off. The superposition of data and control signals in a single interconnection is effectively utilized to reduce complexity of switches and interconnections, and to eliminate skew between data and control signals. It is evaluated that the reduction of the power dissipation is remarkable, if the operating ratio is less than 75%.
{"title":"Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals","authors":"A. Ishikawa, N. Okada, M. Kameyama","doi":"10.1109/ISMVL.2010.41","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.41","url":null,"abstract":"A bit-serial multiple-valued reconfigurable VLSI using current-mode logic circuits has been proposed. A Differential-Pair Circuit (DPC) is used as a basic component of a cell, so that the static power is dissipated even in the nonactive cells. To solve the problem, autonomous ON/OFF control of the current sources is presented based on superposition of bit-serial data and current-source control signals. In the proposed switched current control technique, the static power dissipation can be greatly reduced because current sources in nonactive circuit blocks are turned off. The superposition of data and control signals in a single interconnection is effectively utilized to reduce complexity of switches and interconnections, and to eliminate skew between data and control signals. It is evaluated that the reduction of the power dissipation is remarkable, if the operating ratio is less than 75%.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123189014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we axiomatize the formulas that, in the infinite-valued (standard) Lukasiewicz algebra, always take a value above certain fixed number. This generalizes the approach considered in the infinite-valued Lukasiewicz logic, where the fixed number is the maximum.
{"title":"Infinite-Valued Lukasiewicz Logic Based on Principal Lattice Filters","authors":"Félix Bou","doi":"10.1109/ISMVL.2010.23","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.23","url":null,"abstract":"In this paper we axiomatize the formulas that, in the infinite-valued (standard) Lukasiewicz algebra, always take a value above certain fixed number. This generalizes the approach considered in the infinite-valued Lukasiewicz logic, where the fixed number is the maximum.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129626331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We investigate the automorphism group of finite Gödel algebras, the algebraic counterpart of Godel infinite-valued propositional logic with a finite number of variables. In logical terms, we look at the structure of substitution of terms that preserve logical equivalence in this logic. We obtain a characterisation of the arising automorphism groups in terms of semidirect and direct products of symmetric groups. Building on this, we establish an explicit closed formula for the cardinality of the automorphism group of the Lindenbaum algebra of Gödel logic over n propositional variables, for any integer n >= 1.
{"title":"The Automorphism Group of Finite Godel Algebras","authors":"S. Aguzzoli, B. Gerla, V. Marra","doi":"10.1109/ISMVL.2010.13","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.13","url":null,"abstract":"We investigate the automorphism group of finite Gödel algebras, the algebraic counterpart of Godel infinite-valued propositional logic with a finite number of variables. In logical terms, we look at the structure of substitution of terms that preserve logical equivalence in this logic. We obtain a characterisation of the arising automorphism groups in terms of semidirect and direct products of symmetric groups. Building on this, we establish an explicit closed formula for the cardinality of the automorphism group of the Lindenbaum algebra of Gödel logic over n propositional variables, for any integer n >= 1.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125626842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new algorithm MP(multiple pass) to synthesize large reversible binary circuits without ancilla bits. The MMD algorithm requires to store a truth table (or a Reed-Muller -RM transform) as a 2^n vector for a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with existing algorithms. In addition, our unique multipass approach where the circuit is synthesized with various, yet specific, minterm orders yields optimal solution. The algorithm returns a description of the optimal circuit with respect to gate count or quantum cost. Although the synthesis process is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less
{"title":"Synthesis of Reversible Circuits with No Ancilla Bits for Large Reversible Functions Specified with Bit Equations","authors":"Nouraddin Alhagi, M. Hawash, M. Perkowski","doi":"10.1109/ISMVL.2010.16","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.16","url":null,"abstract":"This paper presents a new algorithm MP(multiple pass) to synthesize large reversible binary circuits without ancilla bits. The MMD algorithm requires to store a truth table (or a Reed-Muller -RM transform) as a 2^n vector for a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with existing algorithms. In addition, our unique multipass approach where the circuit is synthesized with various, yet specific, minterm orders yields optimal solution. The algorithm returns a description of the optimal circuit with respect to gate count or quantum cost. Although the synthesis process is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127787254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Every probability on many-valued events (a state on a finitely-generated free MV-algebras) is uniquely represented by refining finitely-supported probabilities across all Schauder bases. This procedure enables reconstructing the state space as the inverse limit of an inverse system of finite-dimensional simplices.
{"title":"Note on Construction of Probabilities on Many-Valued Events via Schauder Bases and Inverse Limits","authors":"Tomáš Kroupa","doi":"10.1109/ISMVL.2010.42","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.42","url":null,"abstract":"Every probability on many-valued events (a state on a finitely-generated free MV-algebras) is uniquely represented by refining finitely-supported probabilities across all Schauder bases. This procedure enables reconstructing the state space as the inverse limit of an inverse system of finite-dimensional simplices.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stochastic iterative decoders are a recently introduced hardware-oriented class of message-passing algorithms for ultra-low complexity error-correcting decoders. We show that dynamic power consumption in stochastic decoders is exposed at the algorithmic level and can be evaluated from the values of messages passed on the code’s factor graph. This observation leads to a method for evaluating the relative dynamic power consumption of stochastic decoders as early as the code design stage. We propose a method based on density evolution that can be used to compare code ensembles in terms of their decoding energy per information bit. We note that despite using a stochastic signaling scheme, stochastic decoders converge to a codeword and stop consuming dynamic power. Results illustrate that significant differences in power consumption can be identified at the code design stage and tradeoffs can be exploited before designing a specific implementation.
{"title":"Switching Activity in Stochastic Decoders","authors":"V. Gaudet, W. Gross","doi":"10.1109/ISMVL.2010.39","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.39","url":null,"abstract":"Stochastic iterative decoders are a recently introduced hardware-oriented class of message-passing algorithms for ultra-low complexity error-correcting decoders. We show that dynamic power consumption in stochastic decoders is exposed at the algorithmic level and can be evaluated from the values of messages passed on the code’s factor graph. This observation leads to a method for evaluating the relative dynamic power consumption of stochastic decoders as early as the code design stage. We propose a method based on density evolution that can be used to compare code ensembles in terms of their decoding energy per information bit. We note that despite using a stochastic signaling scheme, stochastic decoders converge to a codeword and stop consuming dynamic power. Results illustrate that significant differences in power consumption can be identified at the code design stage and tradeoffs can be exploited before designing a specific implementation.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127483511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper compares 6 decision diagram machines (DDMs) with respect to area-time complexity, throughput, and compatibility to the existing memory. First, 6 types of decision diagrams (DDs): BDD, MDD, QRBDD, QRMDD, heterogeneous MDD (HMDD), and QRHMDD are introduced. Second, corresponding DDMs are developed. Third, memory sizes and average path length (APL) for these DDs are compared. As for area-time complexity, the QDDM is the best; as for throughput, the QRQDDM is the best; and as for compatibility to the existing memory, the HMDDM is the best.
{"title":"A Comparison of Architectures for Various Decision Diagram Machines","authors":"Hiroki Nakahara, Tsutomu Sasao, M. Matsuura","doi":"10.1109/ISMVL.2010.50","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.50","url":null,"abstract":"This paper compares 6 decision diagram machines (DDMs) with respect to area-time complexity, throughput, and compatibility to the existing memory. First, 6 types of decision diagrams (DDs): BDD, MDD, QRBDD, QRMDD, heterogeneous MDD (HMDD), and QRHMDD are introduced. Second, corresponding DDMs are developed. Third, memory sizes and average path length (APL) for these DDs are compared. As for area-time complexity, the QDDM is the best; as for throughput, the QRQDDM is the best; and as for compatibility to the existing memory, the HMDDM is the best.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131269554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Naoki Sugiyama, Hiroshi Noto, Yoshito Nishigami, R. Oda, T. Waho
A novel low-power 8-bit successive approximation (SA) ADC using multiple-valued approach is presented. In contrast to conventional 1bit/step SA ADCs, 2bit/step conversion is employed, and combined with the split capacitor array and dual sampling technique to reduce the power consumption. Transistor level simulation, assuming 0.18-µm standard CMOS technology, shows that the total power consumption decreases by about 20% compared with that obtained for a 1bit/step counterpart at a sampling frequency of 100 kHz. Since the digital part consumes more power than the analog part, the present approach is expected to be more attractive for ADCs using advanced process technology.
提出了一种基于多值方法的新型低功耗8位连续逼近ADC。与传统的1bit/step SA adc相比，采用2bit/step转换，并结合分裂电容阵列和双采样技术来降低功耗。采用0.18µm标准CMOS技术的晶体管级仿真表明，与采样频率为100 kHz的1比特/步长的等效电路相比，总功耗降低了约20%。由于数字部分比模拟部分消耗更多的功率，因此目前的方法预计对使用先进工艺技术的adc更具吸引力。
{"title":"A Low-Power Successive Approximation Analog-to-Digital Converter Based on 2-Bit/Step Comparison","authors":"Naoki Sugiyama, Hiroshi Noto, Yoshito Nishigami, R. Oda, T. Waho","doi":"10.1109/ISMVL.2010.66","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.66","url":null,"abstract":"A novel low-power 8-bit successive approximation (SA) ADC using multiple-valued approach is presented. In contrast to conventional 1bit/step SA ADCs, 2bit/step conversion is employed, and combined with the split capacitor array and dual sampling technique to reduce the power consumption. Transistor level simulation, assuming 0.18-µm standard CMOS technology, shows that the total power consumption decreases by about 20% compared with that obtained for a 1bit/step counterpart at a sampling frequency of 100 kHz. Since the digital part consumes more power than the analog part, the present approach is expected to be more attractive for ADCs using advanced process technology.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125758866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is based on Field Effect Transistors (FETs) that have different voltage threshold levels. The resulting logic cell library is sufficient to implement all possible quaternary switching functions. The logic circuits operate in voltage mode where different ranges of voltages encode the logic levels. Voltage mode circuitry is used to minimize overall power dissipation characteristics. Analysis of the resulting multiplication circuits indicates that power dissipation characteristics are advantageous when compared to equivalent word-sized binary voltage mode configurations with no decrease in performance.
{"title":"Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits","authors":"Satyendra R. Datla, M. Thornton","doi":"10.1109/ISMVL.2010.32","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.32","url":null,"abstract":"Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is based on Field Effect Transistors (FETs) that have different voltage threshold levels. The resulting logic cell library is sufficient to implement all possible quaternary switching functions. The logic circuits operate in voltage mode where different ranges of voltages encode the logic levels. Voltage mode circuitry is used to minimize overall power dissipation characteristics. Analysis of the resulting multiplication circuits indicates that power dissipation characteristics are advantageous when compared to equivalent word-sized binary voltage mode configurations with no decrease in performance.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124260726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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