Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194707
S. Maggioni, A. Veggetti, A. Bogliolo, L. Croce
We present a methodology for on-chip characterization of the pin-to-pin propagation delay of single standard cells. A periodic waveform is provided to an input pin of the standard cell under characterization, while keeping all other inputs at non-controlling logic values. Simultaneous random sampling is then applied to input and output periodic waveforms, and propagation delay measures are obtained from the joint signal probabilities of the samples. The proposed technique is suitable for on-chip implementation because it is simple and it doesn't require timing-accurate control signals. On the other hand, on-chip measurements can be applied to a large number of cells working in different operating conditions, providing valuable information for characterizing and validating timing models. A test chip has been realized in a 0.18 /spl mu/m embedded NVM CMOS technology, and used to monitor the sub-nanosecond timing behavior of a standard cell library during process development.
{"title":"Random sampling for on-chip characterization of standard-cell propagation delay","authors":"S. Maggioni, A. Veggetti, A. Bogliolo, L. Croce","doi":"10.1109/ISQED.2003.1194707","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194707","url":null,"abstract":"We present a methodology for on-chip characterization of the pin-to-pin propagation delay of single standard cells. A periodic waveform is provided to an input pin of the standard cell under characterization, while keeping all other inputs at non-controlling logic values. Simultaneous random sampling is then applied to input and output periodic waveforms, and propagation delay measures are obtained from the joint signal probabilities of the samples. The proposed technique is suitable for on-chip implementation because it is simple and it doesn't require timing-accurate control signals. On the other hand, on-chip measurements can be applied to a large number of cells working in different operating conditions, providing valuable information for characterizing and validating timing models. A test chip has been realized in a 0.18 /spl mu/m embedded NVM CMOS technology, and used to monitor the sub-nanosecond timing behavior of a standard cell library during process development.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123232160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194739
R. Goering, M. Casale-Rossi
In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible, in the attempt to cope with the challenges posed by multi-million gates and multi-GHz systems-on-a-chip (SOC). While offering a great deal of opportunities, ball-grid array (BGA) substrates, flip-chip and multi-stacked dies require an unprecedented level of integration between IC and package design and verification.
{"title":"IC & package co-design: challenge or dream?","authors":"R. Goering, M. Casale-Rossi","doi":"10.1109/ISQED.2003.1194739","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194739","url":null,"abstract":"In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible, in the attempt to cope with the challenges posed by multi-million gates and multi-GHz systems-on-a-chip (SOC). While offering a great deal of opportunities, ball-grid array (BGA) substrates, flip-chip and multi-stacked dies require an unprecedented level of integration between IC and package design and verification.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"23 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126011921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194741
M. Reinhardt
Although process technology has shrunk down to nanometer features over the last decade, the gap between ASIC design and full-custom IC design has widened. This gap includes significant differences in performance, price, and profit between the two design styles. It is also revealed by huge differences in quality between the two styles in speed, power distribution and consumption, yield, and reliability, in some cases as much as an order of magnitude. To fully utilize the latest process technologies, a full-custom design approach with the productivity of an ASIC flow is necessary. Michael Reinhardt will start with an analysis of how the gap between ASIC and full-custom design began, and discuss its long-term consequences on the whole industry. He will then show the positive effects on the quality of IC design, and on the chip industry’s economic situation, which can occur if this gap can be closed. He will illustrate possible strategies and solutions for achieving this closure, and how they can be implemented right now in practical ways.
{"title":"Closing the gap between ASIC and full custom: a path to quality design","authors":"M. Reinhardt","doi":"10.1109/ISQED.2003.1194741","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194741","url":null,"abstract":"Although process technology has shrunk down to nanometer features over the last decade, the gap between ASIC design and full-custom IC design has widened. This gap includes significant differences in performance, price, and profit between the two design styles. It is also revealed by huge differences in quality between the two styles in speed, power distribution and consumption, yield, and reliability, in some cases as much as an order of magnitude. To fully utilize the latest process technologies, a full-custom design approach with the productivity of an ASIC flow is necessary. Michael Reinhardt will start with an analysis of how the gap between ASIC and full-custom design began, and discuss its long-term consequences on the whole industry. He will then show the positive effects on the quality of IC design, and on the chip industry’s economic situation, which can occur if this gap can be closed. He will illustrate possible strategies and solutions for achieving this closure, and how they can be implemented right now in practical ways.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131093537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194742
S. Borkar
Microprocessor performance increased by five orders of magnitude in the last three decades. This was made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue to fulfill the microprocessor performance demand; however, with some adverse effects posing barriers. Therefore, performance at any cost will not be an option; significant improvements in efficiency of transistor utilization will be necessary. This paper will discuss potential solutions in all disciplines, such as microarchitecture, circuits, design technologies & methodologies, thermals, and power delivery to overcome these barriers in technologies beyond 100 nm.
{"title":"A VLSI system perspective for microprocessors beyond 90nm","authors":"S. Borkar","doi":"10.1109/ISQED.2003.1194742","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194742","url":null,"abstract":"Microprocessor performance increased by five orders of magnitude in the last three decades. This was made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue to fulfill the microprocessor performance demand; however, with some adverse effects posing barriers. Therefore, performance at any cost will not be an option; significant improvements in efficiency of transistor utilization will be necessary. This paper will discuss potential solutions in all disciplines, such as microarchitecture, circuits, design technologies & methodologies, thermals, and power delivery to overcome these barriers in technologies beyond 100 nm.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124046058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194719
F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh
High-density and high-performance single-port and dual-port SRAM increasingly occupy a majority of the chip area in system-on-chip product designs. Therefore, good yieldability and manufacturability of the SRAM are essential. At the same time there is tremendous competitive pressure to get the best SRAM density and performance. We have previously published and presented the industry's smallest and fastest embedded 6T SRAM bitcells in 0.18 /spl mu/m and 130 nm generation standard CMOS process. We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance. In this paper we discuss the design and use of SRAM-specific test structures that have enabled us to quickly evaluate process-design interactions and to fine-tune process and/or design for improving yields and manufacturability. We have designed test structures using our aggressive production bitcell as basis to probe for any possible weaknesses of the process or design in SRAM Results from these SRAM-specific test structures show good correlation to yield results and in-line SEM observations, and enable us to improve SRAM yields quickly. We have also designed SRAM-transistor test structures to characterize the SRAM cell devices in their real working environment. Results help to evaluate the circuit performance and provide us with guidelines for further design improvements. These data when used in the early stage of the development cycle are also useful for model validation.
{"title":"Design and use of memory-specific test structures to ensure SRAM yield and manufacturability","authors":"F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh","doi":"10.1109/ISQED.2003.1194719","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194719","url":null,"abstract":"High-density and high-performance single-port and dual-port SRAM increasingly occupy a majority of the chip area in system-on-chip product designs. Therefore, good yieldability and manufacturability of the SRAM are essential. At the same time there is tremendous competitive pressure to get the best SRAM density and performance. We have previously published and presented the industry's smallest and fastest embedded 6T SRAM bitcells in 0.18 /spl mu/m and 130 nm generation standard CMOS process. We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance. In this paper we discuss the design and use of SRAM-specific test structures that have enabled us to quickly evaluate process-design interactions and to fine-tune process and/or design for improving yields and manufacturability. We have designed test structures using our aggressive production bitcell as basis to probe for any possible weaknesses of the process or design in SRAM Results from these SRAM-specific test structures show good correlation to yield results and in-line SEM observations, and enable us to improve SRAM yields quickly. We have also designed SRAM-transistor test structures to characterize the SRAM cell devices in their real working environment. Results help to evaluate the circuit performance and provide us with guidelines for further design improvements. These data when used in the early stage of the development cycle are also useful for model validation.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133544118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194764
S. Wong, C. Yue, R. Chang, Soyoung Kim, B. Kleveland, F. O’Mahony
Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, the extraction of wire inductance is not just dependent on the immediate neighboring environment. This paper discusses the various difficulties of extracting inductance of randomly placed wires in a typical chip environment. With dedicated return path, the wire inductance can be controlled and benefit the design of high-speed circuits. Specific examples are illustrated.
{"title":"On-chip interconnect inductance - friend or foe","authors":"S. Wong, C. Yue, R. Chang, Soyoung Kim, B. Kleveland, F. O’Mahony","doi":"10.1109/ISQED.2003.1194764","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194764","url":null,"abstract":"Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, the extraction of wire inductance is not just dependent on the immediate neighboring environment. This paper discusses the various difficulties of extracting inductance of randomly placed wires in a typical chip environment. With dedicated return path, the wire inductance can be controlled and benefit the design of high-speed circuits. Specific examples are illustrated.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127674045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194726
N. Nagaraj, T. Bonifield, Abha Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara, C. Cantrell
Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Typically, researchers and designers have been using pre-defined set of structures to validate the accuracy of interconnect models and parasitic extraction tools. Unlike industry benchmarks on circuits such as MCNC benchmarks, no benchmarks exist for interconnect parasitics. This paper discusses the issues in accurate interconnect modeling for 130 nm and below copper/ultra low-k technologies. A set of benchmark structures that could be used to validate accuracy and compare parasitic extraction tools is proposed. Silicon results from 130 nm technology are presented to illustrate the usefulness of these benchmarks. Results of application of these benchmarks to compare parasitic extraction tools are presented to demonstrate systematic validation of resistance and capacitance extraction.
{"title":"Benchmarks for interconnect parasitic resistance and capacitance","authors":"N. Nagaraj, T. Bonifield, Abha Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara, C. Cantrell","doi":"10.1109/ISQED.2003.1194726","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194726","url":null,"abstract":"Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Typically, researchers and designers have been using pre-defined set of structures to validate the accuracy of interconnect models and parasitic extraction tools. Unlike industry benchmarks on circuits such as MCNC benchmarks, no benchmarks exist for interconnect parasitics. This paper discusses the issues in accurate interconnect modeling for 130 nm and below copper/ultra low-k technologies. A set of benchmark structures that could be used to validate accuracy and compare parasitic extraction tools is proposed. Silicon results from 130 nm technology are presented to illustrate the usefulness of these benchmarks. Results of application of these benchmarks to compare parasitic extraction tools are presented to demonstrate systematic validation of resistance and capacitance extraction.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114742739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194712
G. Feierbach, Vijay Gupta
There are a number of RTL coverage tools on the market today that essentially tells you only that a set of signals has been toggled by a particular diagnostic test. This is useful in showing what areas of the RTL design are definitely not covered by the diagnostic test but tells you very little about the set of signals that have been toggled. In an extreme case a diagnostic test may fail to fail when anyone of these signals are in error. The following is a strategy for examining the coverage indicated by a commercial coverage testing software package and obtaining a truer picture of a diagnostic test's real coverage. This concept is extended to a full regression test suite.
{"title":"True coverage: a goal of verification","authors":"G. Feierbach, Vijay Gupta","doi":"10.1109/ISQED.2003.1194712","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194712","url":null,"abstract":"There are a number of RTL coverage tools on the market today that essentially tells you only that a set of signals has been toggled by a particular diagnostic test. This is useful in showing what areas of the RTL design are definitely not covered by the diagnostic test but tells you very little about the set of signals that have been toggled. In an extreme case a diagnostic test may fail to fail when anyone of these signals are in error. The following is a strategy for examining the coverage indicated by a commercial coverage testing software package and obtaining a truer picture of a diagnostic test's real coverage. This concept is extended to a full regression test suite.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"369 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115967364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194757
Toshiyuki Shibuya, R. Murgai, T. Konno, Kazuhiro Emi, Kaoru Kawamura
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. It provides a common database for delay calculation, logic optimization, placement, and routing tools so that they can work and interact closely. We present results on industrial circuits showing the efficacy of this methodology.
{"title":"PDL: a new physical synthesis methodology","authors":"Toshiyuki Shibuya, R. Murgai, T. Konno, Kazuhiro Emi, Kaoru Kawamura","doi":"10.1109/ISQED.2003.1194757","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194757","url":null,"abstract":"In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. It provides a common database for delay calculation, logic optimization, placement, and routing tools so that they can work and interact closely. We present results on industrial circuits showing the efficacy of this methodology.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127112485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194701
B. Payne
Design reuse has become essential to cope with the ever-increasing design complexity. IP level reuse alone has proven insufficient. Platform based design allows the validation of a robust combination of IP blocks and provides a reference HW and SW baseline which can be supported with an integrated development environment. Several years ago we transitioned into the streaming data era with most systems serving as content generation appliances, content consumption appliances or content distribution equipment. Now we have entered the age of ambient intelligence where the streaming data is served up through wireless links. What will platform leadership look like in this new era? How will the SoC infrastructure change as we move to 90nm technology with more than 30M gate per square centimeter integration capacity? How are usage patterns changing and what represents the killer application that enhances the users quality of life by enabling more advanced interaction with the ambient intelligence? What is it going to take to make a step function improvement in system level design productivity? What happens when power optimization becomes the dominant design consideration? What about SoC affordability? What will the SoC design of the future look like? These are just some of the thought provoking issues that will be addressed in Bob Payne’s keynote.
{"title":"Platform leadership in the ambient intelligence era","authors":"B. Payne","doi":"10.1109/ISQED.2003.1194701","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194701","url":null,"abstract":"Design reuse has become essential to cope with the ever-increasing design complexity. IP level reuse alone has proven insufficient. Platform based design allows the validation of a robust combination of IP blocks and provides a reference HW and SW baseline which can be supported with an integrated development environment. Several years ago we transitioned into the streaming data era with most systems serving as content generation appliances, content consumption appliances or content distribution equipment. Now we have entered the age of ambient intelligence where the streaming data is served up through wireless links. What will platform leadership look like in this new era? How will the SoC infrastructure change as we move to 90nm technology with more than 30M gate per square centimeter integration capacity? How are usage patterns changing and what represents the killer application that enhances the users quality of life by enabling more advanced interaction with the ambient intelligence? What is it going to take to make a step function improvement in system level design productivity? What happens when power optimization becomes the dominant design consideration? What about SoC affordability? What will the SoC design of the future look like? These are just some of the thought provoking issues that will be addressed in Bob Payne’s keynote.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122912229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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