Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194750
Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim
This paper proposes a new clocking strategy for dynamic circuits. It provides faster performance and smaller area than conventional clocking schemes. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit carry look ahead adder (CLA) is designed and simulated using 0.25 /spl mu/m CMOS technology to demonstrate 32.7% faster speed than the conventional clocking scheme and 19.4% transistor counter reduction.
{"title":"A novel clocking strategy for dynamic circuits","authors":"Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim","doi":"10.1109/ISQED.2003.1194750","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194750","url":null,"abstract":"This paper proposes a new clocking strategy for dynamic circuits. It provides faster performance and smaller area than conventional clocking schemes. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit carry look ahead adder (CLA) is designed and simulated using 0.25 /spl mu/m CMOS technology to demonstrate 32.7% faster speed than the conventional clocking scheme and 19.4% transistor counter reduction.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132259200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194747
Dongwook Lee, Wesley Kwong, D. Blaauw, D. Sylvester
In this paper we develop a fast approach to analyze the total leakage power of a large circuit block, considering both gate leakage, I/sub gate/, and subthreshold leakage, I/sub sub/. The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies. We propose simple and accurate heuristics to quickly estimate the state-dependent total leakage current considering the interaction between I/sub sub/ and I/sub gate/. We apply this method to ISCAS benchmark circuits in a projected 100 nm technology and demonstrate excellent accuracy compared to SPICE simulation with a 20,000X speedup on average.
{"title":"Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design","authors":"Dongwook Lee, Wesley Kwong, D. Blaauw, D. Sylvester","doi":"10.1109/ISQED.2003.1194747","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194747","url":null,"abstract":"In this paper we develop a fast approach to analyze the total leakage power of a large circuit block, considering both gate leakage, I/sub gate/, and subthreshold leakage, I/sub sub/. The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies. We propose simple and accurate heuristics to quickly estimate the state-dependent total leakage current considering the interaction between I/sub sub/ and I/sub gate/. We apply this method to ISCAS benchmark circuits in a projected 100 nm technology and demonstrate excellent accuracy compared to SPICE simulation with a 20,000X speedup on average.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130494696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194704
T. Vucurevich
It is commonly agreed that sub-nanometer design is electronic design technology’s next big challenge. With the economic stakes higher than ever, the vendors of electronic design solutions must put themselves into their customers' shoes through comprehensive, high-quality programs. My understanding of the differences designers face at geometries below 100 nanometers has led to my discussion of some of the challenges the industry faces in the sub-nanometer realm. This includes the domination of wires in digital design, which requires the ability to design the best quality wires through continuous convergence, a wire-centric methodology. In the nanometer world, the front-end and back-end disappear, leaving the prototype as the chip. This includes detailed wiring, and a new full-chip iteration every day. Most sub-nanometer ICs and SoCs will be digital/mixed-signal. This leads to custom design issues, such as integrating sensitive circuits with massive digital and mixed-signal design, productivity and foundry interface. Nanometer SoC verification includes digital, analog and software, and a 70 percent silicon re-spin rate because of associated functional errors. At sub-nanometer levels, design-in becomes a major bottleneck, especially across a design chain, which can only be solved by silicon-package-board co-design.
{"title":"Quality challenges of the nanometer design realm","authors":"T. Vucurevich","doi":"10.1109/ISQED.2003.1194704","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194704","url":null,"abstract":"It is commonly agreed that sub-nanometer design is electronic design technology’s next big challenge. With the economic stakes higher than ever, the vendors of electronic design solutions must put themselves into their customers' shoes through comprehensive, high-quality programs. My understanding of the differences designers face at geometries below 100 nanometers has led to my discussion of some of the challenges the industry faces in the sub-nanometer realm. This includes the domination of wires in digital design, which requires the ability to design the best quality wires through continuous convergence, a wire-centric methodology. In the nanometer world, the front-end and back-end disappear, leaving the prototype as the chip. This includes detailed wiring, and a new full-chip iteration every day. Most sub-nanometer ICs and SoCs will be digital/mixed-signal. This leads to custom design issues, such as integrating sensitive circuits with massive digital and mixed-signal design, productivity and foundry interface. Nanometer SoC verification includes digital, analog and software, and a 70 percent silicon re-spin rate because of associated functional errors. At sub-nanometer levels, design-in becomes a major bottleneck, especially across a design chain, which can only be solved by silicon-package-board co-design.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124819065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194720
Q. Qian, S. Tan
The proliferation and acceptance of reticle enhancement technologies (RET) like optical proximity correction (OPC) and phase shift masking (PSM) have significantly increased the cost and complexity of sub-100 nm photomasks. The photomask layout is no longer an exact replica of the design layout. As a result, reliably verifying RET synthesis accuracy, structural integrity, and conformance to mask fabrication rules are crucial for the manufacture of nanometer regime VLSI designs. In this paper, we demonstrate a physical model based mask layout verification system. The new system consists of an efficient wafer-patterning simulator that is able to solve the process physical equations for optical imaging and resist development and hence can achieve high degree accuracy required by mask verification tasks. It is able to efficiently evaluate mask performance by simulating edge displacement errors between wafer image and the intended layout. We show the capabilities for hot spot detection, line width variation analysis, and process window prediction capabilities with a sample practical layout. We also discuss the potential of the new physical model simulator for improving circuit performance in physical layout synthesis.
{"title":"Advanced physical models for mask data verification and impacts on physical layout synthesis","authors":"Q. Qian, S. Tan","doi":"10.1109/ISQED.2003.1194720","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194720","url":null,"abstract":"The proliferation and acceptance of reticle enhancement technologies (RET) like optical proximity correction (OPC) and phase shift masking (PSM) have significantly increased the cost and complexity of sub-100 nm photomasks. The photomask layout is no longer an exact replica of the design layout. As a result, reliably verifying RET synthesis accuracy, structural integrity, and conformance to mask fabrication rules are crucial for the manufacture of nanometer regime VLSI designs. In this paper, we demonstrate a physical model based mask layout verification system. The new system consists of an efficient wafer-patterning simulator that is able to solve the process physical equations for optical imaging and resist development and hence can achieve high degree accuracy required by mask verification tasks. It is able to efficiently evaluate mask performance by simulating edge displacement errors between wafer image and the intended layout. We show the capabilities for hot spot detection, line width variation analysis, and process window prediction capabilities with a sample practical layout. We also discuss the potential of the new physical model simulator for improving circuit performance in physical layout synthesis.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194722
M. Scott, M. Peralta, J. Carothers
In this paper, we evaluate the dependencies between tools, data and environment in process design kits. and present a framework for systematically analyzing the quality of the design tools and libraries through the design flow. The framework consists of a regression engine which executes sets of tests in a distributed computing environment. These tests vary from simulations to validate models and simulators, to tests on layout versus schematics, parasitics extraction accuracy, and ultimately, tests to validate the extracted circuit integrity against the ideal. In particular, it is shown that test-chaining is required to obtain confidence in the simulation-to-silicon equivalence. A secondary objective is to identify and quantify the peak-error injection points. Finally, future work is outlined to extend the framework to automate entire design flows and provide capability for inter-tool constraint satisfaction and design optimization.
{"title":"System and framework for QA of process design kits","authors":"M. Scott, M. Peralta, J. Carothers","doi":"10.1109/ISQED.2003.1194722","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194722","url":null,"abstract":"In this paper, we evaluate the dependencies between tools, data and environment in process design kits. and present a framework for systematically analyzing the quality of the design tools and libraries through the design flow. The framework consists of a regression engine which executes sets of tests in a distributed computing environment. These tests vary from simulations to validate models and simulators, to tests on layout versus schematics, parasitics extraction accuracy, and ultimately, tests to validate the extracted circuit integrity against the ideal. In particular, it is shown that test-chaining is required to obtain confidence in the simulation-to-silicon equivalence. A secondary objective is to identify and quantify the peak-error injection points. Finally, future work is outlined to extend the framework to automate entire design flows and provide capability for inter-tool constraint satisfaction and design optimization.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121685388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194748
P. Heydari
This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter. It is shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.
{"title":"Design and analysis of low-voltage current-mode logic buffers","authors":"P. Heydari","doi":"10.1109/ISQED.2003.1194748","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194748","url":null,"abstract":"This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter. It is shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124081556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194740
R. Madhavan
Electronic design automation continues to attract a great deal of investment from the venture community, fostering the creation of startup companies focused on developing unique point-tool solutions. While many innovative new technologies come from this, industry must consider the increasingly critical need of IC designers and manufacturers: integrated design flows that enable the design and production of chips with fewer resources and in less time, without compromising the quality of results. Increasingly evident is the advantage of integrated design and the economies it brings while delivering the same quality of results as point-tool-based approaches. The future of EDA depends on the industry’s ability to deliver solutions that enable the IC industry’s integration of electronic design tools and processes as it relies on EDA to provide the means for producing the next generation of semiconductor products.
{"title":"Addressing the IC designer's needs: integrated design software for faster, more economical chip design","authors":"R. Madhavan","doi":"10.1109/ISQED.2003.1194740","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194740","url":null,"abstract":"Electronic design automation continues to attract a great deal of investment from the venture community, fostering the creation of startup companies focused on developing unique point-tool solutions. While many innovative new technologies come from this, industry must consider the increasingly critical need of IC designers and manufacturers: integrated design flows that enable the design and production of chips with fewer resources and in less time, without compromising the quality of results. Increasingly evident is the advantage of integrated design and the economies it brings while delivering the same quality of results as point-tool-based approaches. The future of EDA depends on the industry’s ability to deliver solutions that enable the IC industry’s integration of electronic design tools and processes as it relies on EDA to provide the means for producing the next generation of semiconductor products.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114230590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194718
C. Chen, K. George
A new approach to optimize a configurable two-dimensional (2-D) linear feedback shift registers (LFSR) for both embedded and random test pattern generation in built-in self-test (BIST) is proposed. This configurable 2-D LFSR based test pattern generator generates: 1) a deterministic sequence of test patterns for random-pattern-resistant faults, and then 2) random patterns for random-pattern-detectable faults. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock BIST for benchmark circuits show with the configurable scheme the number of flip-flops of 2-D LFSR is reduced by 79%. The average number of faults detected by configurable 2-D LFSR is 9.27% higher than the conventional LFSR. Experimental results of test-per-scan BIST for benchmark circuits demonstrate the effectiveness of the proposed technique in which high fault coverage can be achieved.
{"title":"Automated synthesis of configurable two-dimensional linear feedback shifter registers for random/embedded test patterns","authors":"C. Chen, K. George","doi":"10.1109/ISQED.2003.1194718","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194718","url":null,"abstract":"A new approach to optimize a configurable two-dimensional (2-D) linear feedback shift registers (LFSR) for both embedded and random test pattern generation in built-in self-test (BIST) is proposed. This configurable 2-D LFSR based test pattern generator generates: 1) a deterministic sequence of test patterns for random-pattern-resistant faults, and then 2) random patterns for random-pattern-detectable faults. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock BIST for benchmark circuits show with the configurable scheme the number of flip-flops of 2-D LFSR is reduced by 79%. The average number of faults detected by configurable 2-D LFSR is 9.27% higher than the conventional LFSR. Experimental results of test-per-scan BIST for benchmark circuits demonstrate the effectiveness of the proposed technique in which high fault coverage can be achieved.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126515215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194713
G. Callicó, A. Núñez, R. Llopis, R. Sethuraman
This paper addresses a low-cost and real-time solution for the implementation of super-resolution (SR) algorithms over SOC (System-On-Chip) platforms in order to achieve high-quality image improvements. Low-cost constraints are accomplished in the sense that SR is performed without developing a specific hardware, but re-using a video encoder IP block. This encoder can be used either in compression mode or in SR mode. This video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several SOC platforms are being developed. Furthermore, this work can be easily adapted to other video encoder platforms.
{"title":"Low-cost and real-time super-resolution over a video encoder IP","authors":"G. Callicó, A. Núñez, R. Llopis, R. Sethuraman","doi":"10.1109/ISQED.2003.1194713","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194713","url":null,"abstract":"This paper addresses a low-cost and real-time solution for the implementation of super-resolution (SR) algorithms over SOC (System-On-Chip) platforms in order to achieve high-quality image improvements. Low-cost constraints are accomplished in the sense that SR is performed without developing a specific hardware, but re-using a video encoder IP block. This encoder can be used either in compression mode or in SR mode. This video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several SOC platforms are being developed. Furthermore, this work can be easily adapted to other video encoder platforms.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123085872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194727
M. Becer, D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov, I. Hajj
Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several high performance designs.
{"title":"Post-route gate sizing for crosstalk noise reduction","authors":"M. Becer, D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov, I. Hajj","doi":"10.1109/ISQED.2003.1194727","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194727","url":null,"abstract":"Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several high performance designs.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133955410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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