Journal of Systems Architecture最新文献

In the resource-constrained federated edge learning (FEEL) systems, fragment-sharing is an efficient approach for multiple clients to cooperatively train a giant model with billions of parameters. Compared with the classical federated learning schemes where the local model is fully trained and exchanged by each client, the fragment-sharing only requires each client to optionally choose a parameter-fragment to train and share, according to its storage, computing, and networking abilities. However, when the full model is no longer delivered in fragment-sharing, the backdoor attacks hidden behind the fragments become harder to be detected, which introduces formidable challenge for the security of FEEL systems. In this paper, we firstly show that the existing fragment-sharing works suffer a lot from the backdoor attacks. Then, a Backdoor-Resilient approach, named BR-FEEL, is introduced to defend against the potential backdoor attacks. Specifically, a twin model is built by each benign client to integrate the parameter-fragments from others. A knowledge distillation process is designed on each client to transfer the clean knowledge from its twin model to local model. With the twin model and knowledge distillation process, our BR-FEEL approach makes sure that the local models of the benign clients will not be backdoored. Experiments on CIFAR-10 and GTSRB datasets with MobileNetV2 and ResNet-34 are conducted. The numerical results demonstrate the efficacy of BR-FEEL on reducing attack success rates by over 90% compared to other baselines under various attack methods.

In schedulability analysis, the timing of all tasks of a real-time system is verified by finding the worst-case behavior. Two well-studied methods in this field are the demand bound test and the real-time calculus. However, the former is only applicable to specific task models whereas the latter does not formalize concrete task models of complex job patterns. This work presents a new approach to formally describe and analyze the worst-case of any complex job pattern. The approach consists of a task model that reduces all kinds of job patterns to a vector space of jobs. Furthermore, the worst-case analysis searches for local maxima to find the worst-case of any job pattern by differentiating any cumulative function of the real-time calculus. Therefore, the analysis in this work implies an algorithm to compute request as well as demand bounds by construction. This formal approach allows the integration of mathematical results from real-time calculus into real-time scheduling theory. In fact, this is, to our knowledge, the first method to compute a demand bound function with arbitrary deadlines by a min-plus deconvolution in the real-time calculus. This now allows the analysis of complex task models as the generalized multiframe model in the real-time calculus.

Recently, transformer-based models have achieved remarkable success in various fields, such as computer vision, speech recognition, and natural language processing. However, transformer models require a substantially higher number of parameters and computational operations than conventional neural networks (e.g., recurrent neural networks, long-short-term memory, and convolutional neural networks). Transformer models are typically processed on graphics processing unit (GPU) platforms specialized for high-performance memory and parallel processing. However, the high power consumption of GPUs poses significant challenges for their deployment in edge device environments with limited battery capacity. To address these issues, research on using field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) to drive transformer models with low power consumption is underway. FPGAs offer a high level of flexibility, whereas ASICs are beneficial for optimizing throughput and power. Therefore, both platforms are highly suitable for efficiently optimizing matrix multiplication operations, constituting a significant portion of transformer models. In addition, FPGAs and ASICs consume less power than GPUs, making them ideal energy-efficient platforms. This study investigates and analyzes the model compression methods, various optimization techniques, and architectures of accelerators related to FPGA- and ASIC-based transformer designs. We expect this study to serve as a valuable guide for hardware research in the transformer field.

Approximate computing can significantly reduce the energy consumption of computing systems. Mixed-precision hardware architectures and precision-tuning tools for software provide the ability to introduce approximations, but when applied separately, they do not give complete control over the accuracy-energy trade-off. The co-optimization of approximations in hardware and software is a complex task, but it promises considerable benefits. We present a methodology for the fast design-time selection of mixed-precision hardware-software combinations that minimize the energy consumption and the area of the target FPGA-based softcore CPUs with configurable support for floating-point and fixed-point arithmetic. Our approach can evaluate configurations more than 2000 times faster than the alternative approach of using gate-level simulation. On benchmarks from the PolyBench suite the identified hardware-software configurations showed improvement of the energy-to-solution metric ranging from 20% to 95%.

Recently, Sahoo et al. introduced a three-factor authentication scheme for Wireless Sensor Networks (WSNs) based on an elliptic curve cryptosystem. Nonetheless, upon closer examination, we have identified critical vulnerabilities in their scheme, including susceptibility to user impersonation, gateway impersonation, sensor node impersonation attacks, and a breach in the three-factor security aspect. Further, the scheme fails to withstand offline sensor node identity guessing attacks, man-in-the-middle attacks, and known session-specific temporary information attacks. Intending to elevate both security and efficiency, we propose a novel three-factor authentication scheme that capitalizes on the strengths of a fuzzy extractor and a cryptographic one-way hash function. The proposed scheme’s security has been rigorously assessed using the SCYTHER tool, confirming its validity under the real-or-random (ROR) model. Moreover, a heuristic analysis exemplifies that the scheme effectively withstands various known cryptographic attacks. Consequently, the performance comparisons establish the superiority of our scheme over related approaches in terms of security and efficiency. Additionally, its suitability for WSNs is evident due to the minimal overhead on the sensor nodes, making it a highly promising solution for real-world implementation.

We introduce a novel mechanism for structured pruning on ConvNet blocks and channels. Our mechanism, Structured Segment Rescaling (SSR) down-samples a ConvNet’s dimensions using depth and width modifiers that respectively remove whole blocks and channels. SSR is a systematic approach for constructing ConvNets that can replace arbitrary design heuristics. The SSR modifiers rescale logical partitions (segments) of a ConvNet with grouped layers. Different modifiers on segments yield many different architectures with unique rescales for their blocks. This diversity of architectures is then systemically explored using a Gaussian Process (GP) that optimizes for modifiers that maintain accuracy and reduce parameters. We analyze SSR in the context of resource constrained environments using ResNets trained on the CIFAR datasets. An initial set of depth and width modifiers explore extreme rescales of ResNet segments, where we find up to 70% parameter reduction. The GP then generalizes on these initial rescales by being trained on them and then predicts the accuracy of other rescaled ConvNet given their segment modifiers. SSR produces over $10^5$ ConvNets that can be trained selectively based on their GP predicted accuracy. The GP enabled SSR pushes compression to over 80% with minimal accuracy impact. While both depth and width modifiers can reduce parameters, we show reducing blocks is better for reducing latency with up to 80% faster ConvNets. Using our mechanism, we can efficiently customize ConvNets using their parameter-accuracy trade-offs. SSR only requires $10^1$ GPU hours and modest engineering to yield efficient new ConvNets that can facilitate edge inference.

The rapid expansion of Mobile Edge Computing (MEC) is driven by the growing demand for resource-intensive applications within the Internet of Things. Computation offloading allows these applications to be executed at the network edge, but it leads to significant electricity expenses for network operators. To mitigate these costs, one promising solution is to power base stations (BSs) with a hybrid energy supply that combines unpredictable harvested energy with stable energy from the smart grid. This paper investigates joint computation scheduling for mobile devices (MDs) and resource allocation in a MEC network incorporating hybrid energy sources. Our objective is to maximize long-term time-averaged service utility by optimizing parameters such as BS battery supply, harvestable energy, CPU frequency, transmission power, task-partition factor, and MD-BS associations. To tackle this complex problem, we exploit the Lyapunov optimization framework to decompose it into deterministic subproblems for each time slot and propose an online network service utility maximization scheduling (NSUMS) algorithm. Experimental results show that our algorithm outperforms benchmark schemes in service utility and energy expenditure, improving the completion ratio by 32%, reducing the failure rate by 80%, and decreasing MD energy consumption by 28%.

With the evolution of 6G technology, the computing power network (CPN), a crucial infrastructure underpinning the future of digital transformation, is being tightly integrated with 6G to jointly foster significant enhancements in network performance. However, the openness of the network and the semi-trusted nature of cloud service providers pose risks to user data, including potential theft and tampering. To address these challenges, this paper introduces a novel scheme called the backdoor-resistant certificateless message-locked integrity audit (BRCLMIA). This scheme incorporates a cryptographic reverse firewall, offering an efficient and secure approach to auditing CPN data integrity. Our thorough analysis demonstrates that the BRCLMIA scheme effectively safeguards against existential forgery under adaptive message attacks, safeguards against algorithm replacement attacks, and ensures the integrity and authenticity of data transmitted within the CPN. Furthermore, the performance analysis reveals that the BRCLMIA scheme exhibits remarkable communication and computational efficiency while defending against various attacks.

Emerging communication technologies, such as 5G and beyond, have introduced diverse requirements that demand high performance and energy efficiency at all levels. Furthermore, the real-time requirements of different services vary significantly — increasing the baseband processor design complexity and demand for flexible hardware platforms. This paper identifies the key characteristics of hardware platforms for baseband processing and describes the existing processing limitations in traditional architectures. In this paper, Coarse-Grained Reconfigurable Architecture (CGRA) is examined as a prospective hardware platform and its characteristic features are highlighted as compared to traditionally employed architectures that make it a suitable candidate for incorporation as a domain-specific accelerator in baseband processing applications. We survey various CGRAs from the last two decades (2004-2023) and analyze their distinct architectural features which can serve as a reference while designing CGRAs for baseband processing applications. Moreover, we investigate the existing challenges toward developing CGRAs for baseband processing and explore their potential solutions. We also provide an overview of the emerging research directions for CGRA and how they can contribute toward the development of advanced baseband processors. Lastly, we highlight a conceptual RISC-V+CGRA framework that can serve as a potential direction toward integrating CGRA in future baseband processing systems.

Real-time virtualization is currently a hot topic, and there is much ongoing research on real-time Virtual Machines and hypervisors. However, most of the previous research focused either on reducing the latencies introduced by the virtualization stack (hypervisor, host Operating System, Virtual Machine scheduling, etc...) or analyzing the virtual CPU scheduling algorithms. Only a few works investigated the impact of the guest Operating System architecture on real-time performance or considered multiple performance metrics (latency, schedulability, startup times, resource consumption) at the same time. This paper compares various features of different virtualization technologies and guest Operating Systems, evaluating their suitability for serving real-time applications. The results indicate that solutions based on KVM (and an appropriate microvm) and the OSv unikernel can be considered viable alternatives to more traditional VMs or containers.