Journal of Systems Architecture最新文献

Emerging communication technologies, such as 5G and beyond, have introduced diverse requirements that demand high performance and energy efficiency at all levels. Furthermore, the real-time requirements of different services vary significantly — increasing the baseband processor design complexity and demand for flexible hardware platforms. This paper identifies the key characteristics of hardware platforms for baseband processing and describes the existing processing limitations in traditional architectures. In this paper, Coarse-Grained Reconfigurable Architecture (CGRA) is examined as a prospective hardware platform and its characteristic features are highlighted as compared to traditionally employed architectures that make it a suitable candidate for incorporation as a domain-specific accelerator in baseband processing applications. We survey various CGRAs from the last two decades (2004-2023) and analyze their distinct architectural features which can serve as a reference while designing CGRAs for baseband processing applications. Moreover, we investigate the existing challenges toward developing CGRAs for baseband processing and explore their potential solutions. We also provide an overview of the emerging research directions for CGRA and how they can contribute toward the development of advanced baseband processors. Lastly, we highlight a conceptual RISC-V+CGRA framework that can serve as a potential direction toward integrating CGRA in future baseband processing systems.

Real-time virtualization is currently a hot topic, and there is much ongoing research on real-time Virtual Machines and hypervisors. However, most of the previous research focused either on reducing the latencies introduced by the virtualization stack (hypervisor, host Operating System, Virtual Machine scheduling, etc...) or analyzing the virtual CPU scheduling algorithms. Only a few works investigated the impact of the guest Operating System architecture on real-time performance or considered multiple performance metrics (latency, schedulability, startup times, resource consumption) at the same time. This paper compares various features of different virtualization technologies and guest Operating Systems, evaluating their suitability for serving real-time applications. The results indicate that solutions based on KVM (and an appropriate microvm) and the OSv unikernel can be considered viable alternatives to more traditional VMs or containers.

As the deployment of artificial intelligence (AI) algorithms at edge devices becomes increasingly prevalent, enhancing the robustness and reliability of autonomous AI-based perception and decision systems is becoming as relevant as precision and performance, especially in applications areas considered safety-critical such as autonomous driving and aerospace. This paper delves into the robustness assessment in embedded Deep Neural Networks (DNNs), particularly focusing on the impact of parameter perturbations produced by single event upsets (SEUs) on convolutional neural networks (CNN) for image semantic segmentation. By scrutinizing the layer-by-layer and bit-by-bit sensitivity of various encoder–decoder models to soft errors, this study thoroughly investigates the vulnerability of segmentation DNNs to SEUs and evaluates the consequences of techniques like model pruning and parameter quantization on the robustness of compressed models aimed at embedded implementations. The findings offer valuable insights into the mechanisms underlying SEU-induced failures that allow for evaluating the robustness of DNNs once trained in advance. Moreover, based on the collected data, we propose a set of practical lightweight error mitigation techniques with no memory or computational cost suitable for resource-constrained deployments. The code used to perform the fault injection (FI) campaign is available at https://github.com/jonGuti13/TensorFI2, while the code to implement proposed techniques is available at https://github.com/jonGuti13/parameterProtection.

Heart rate variability (HRV) is a vital sign with the potential to predict stress and various diseases, including heart attack and arrhythmia. Typically, hospitals utilize electrocardiogram (ECG) devices to capture the heart’s bioelectrical signals, which are then used to calculate HRV values. However, this method is costly and inconvenient due to the requirement for stable connections to the body. In recent years, photoplethysmography (PPG) sensors, which collect reflective light signals, have gained attention as a cost-effective alternative for measuring heart health. However, accurately estimating HRV using PPG signals remains a challenging task due to the inherent sensitivity of PPG sensors. To address the challenges, this paper presents an on-device, low-cost machine learning-based system that aims to achieve high-accuracy HRV estimation in real-time. Firstly, we propose a novel unified performance and resource-aware neural network (UP-RaNN) search method that leverages grid search techniques to identify a neural network model that can deliver both high HRV accuracy and smooth operation on resource-limited devices. Secondly, we design a real-time HRV monitoring system using a resource-limited, ultra-low-power microcontroller unit (MCU). This system utilizes the neural network model obtained through the UP-RaNN to provide HRV readings from PPG data in real-time. Thirdly, we evaluate the proposed UP-RaNN method and the real-time HRV monitoring system by comparing its performance to state-of-the-art studies. Moreover, the system is enhanced with adaptive reconfiguration capability, enabling it to improve energy efficiency and adapt to varying demands during runtime. The results demonstrate that when deployed on an MSP430FR5994 development board running at 8 MHz, the trained deep neural network model obtained through our proposed UP-RaNN achieves HRV estimation in just 0.3 s per inference. Additionally, the model exhibits a better mean absolute percentage error ($\sim$ 5.8%) than the state-of-the-art HRV estimation methods using PPG, while significantly reducing model complexity and computational time.

Autonomous vehicles are increasingly utilized in safety-critical and time-sensitive settings like urban environments and competitive racing. Planning maneuvers ahead is pivotal in these scenarios, where the onboard compute platform determines the vehicle’s future actions. This paper introduces an optimized implementation of the Frenet Path Planner, a renowned path planning algorithm, accelerated through GPU processing. Unlike existing methods, our approach expedites the entire algorithm, encompassing path generation and collision avoidance. We gauge the execution time of our implementation, showcasing significant enhancements over the CPU baseline (up to 22x of speedup). Furthermore, we assess the influence of different precision types (double, float, half) on trajectory accuracy, probing the balance between completion speed and computational precision. Moreover, we analyzed the impact on the execution time caused by the use of Nvidia Unified Memory and by the interference caused by other processes running on the same system. We also evaluate our implementation using the F1tenth simulator and in a real race scenario. The results position our implementation as a strong candidate for the new state-of-the-art implementation for the Frenet Path Planner algorithm.

The security of embedded firmware has become a critical issue in light of the rapid development of the Internet of Things. Current security analysis approaches, such as dynamic analysis, still face bottlenecks and difficulties due to the wide variety of devices and systems. Recent dynamic analysis approaches for embedded firmware have attempted to provide a general solution but heavily rely on detailed device manuals. Meanwhile, approaches that do not rely on manuals have randomness in interrupt triggering, which weakens emulation fidelity and dynamic analysis efficiency. In this paper, we propose a redundant-check-based embedded firmware interrupt modeling and security analysis method that does not rely on commercial manuals. This method involves reverse engineering the control flow of firmware binary and accurately extracting the correct interrupt triggering rules to emulate embedded firmware. We have implemented functional prototypes on QEMU, called IEmu, and evaluated it with 26 firmware in different MCUs. Our results demonstrate significant advantages compared to the recent state-of-the-art approach. On average, IEmu has improved interrupt path exploration efficiency by 2.4 times and fuzz testing coverage by 19%. IEmu restored the interrupt triggering logic in the manual, and emulated three firmware where the state-of-the-art emulator have limitations and found vulnerabilities.

With the popularity of cloud computing, a large number of personal and corporate data are outsourced to the cloud. This centralized storage and processing mode not only improves the efficiency of data processing, but also brings challenges to data security and privacy. In view of the development of quantum computing, the traditional public key encryption may no longer be secure in the future. Therefore, it is particularly important to study the public key authenticated keyword searchable encryption (PEAKS) scheme which can resist quantum. This scheme can provide double guarantee for the data in cloud storage: one is to ensure the confidentiality of the data, so that the original content cannot be decrypted even within the cloud service provider; the other is to allow users to perform keyword searches on encrypted data without decrypting the data. This provides a balance of security and efficiency for data search and analysis in cloud computing environment. Recently, Genise et al. designed a Gadget-based iNTRU trapdoor, which has the advantages of small size and high efficiency. Therefore, we design an efficient and secure public key authentication keyword searchable encryption scheme based on iNTRU lattice. The overall running time of this scheme is only more than 300ms.

Preserving the confidentiality and integrity of data transmission is paramount in the Internet of Things (IoT)-based healthcare systems. Current encryption techniques that allow plaintext checks primarily serve a specific cryptosystem, lacking the adaptability to work with a diverse system incorporating various cryptographic methods. To address this, we present a unique online/offline heterogeneous signcryption scheme with plaintext checkable encryption (HOOSC-PCE). This approach enables the transition of signcrypted messages from an identity-based cryptosystem (IBC) to a public key infrastructure (PKI) system, improving information interoperability. A key aspect of our scheme is its capacity to allow cloud servers to perform plaintext queries, facilitating efficient data searches using plaintext keywords over encrypted data. Furthermore, the signcryption process is divided into online and offline phases. The online phase handles tasks that require fewer resources, while the offline phase carries out more resource-intensive preparatory tasks. We rigorously tested the HOOSC-PCE scheme’s security by proving it secure under the Random Oracle Model (ROM). Meanwhile, compared to similar work, it effectively reduces computation costs by 46.39%, 19.45%, 18.73%, and 13.25% across offline encryption, online encryption, decryption, and search algorithms. The results indicate that the HOOSC-PCE is secure and efficient, confirming its feasibility for IoT-based healthcare systems.

A continuing rise in DNN usage in distributed and embedded use cases has demanded more efficient hardware execution in the field. Low-precision GeMMs with optimized data formats have played a key role in more memory and computationally-efficient networks. Recently trending formats are block-scaled representations stemming from tight HW-SW co-optimization, that compress network size by sharing exponents per data block. Prior work mostly focuses on deploying such block-scaled GeMM operations on domain-specific accelerators for optimum efficiency at the cost of flexibility and ease of deployment. In this work, we exploit and optimize the deployment of block-scaled GeMMs on fully-programmable in-order vector processors using ARM SVE. We define a systematic methodology for performing design space exploration to optimally match the workload specifications with processor vector-lengths, different microkernels, block sizes and shapes. We introduce efficient intrinsics-based microkernels with effective loop unrollings, and data-transfer efficient fused requantization strategies to maximize kernel performance, while also ensuring several deployment configurations. We enable generalized block-scaled kernel deployments through tunable block sizes and shapes, which helps in accommodating different accuracy-speed trade-off requirements. Utilizing 2D activation blocks instead of conventional 1D blocks, the static and dynamic BS-INT8 configurations yielded on average 3.8x and 2.9x faster speedups over FP32 models respectively, at no accuracy loss for CNN classification tasks on CIFAR10/100 datasets.

Hard real-time systems, characterized by stringent timeliness requirements, occur in an increasing variety of industrial sectors. Some such domains carry important safety-critical concerns, notably avionics, space, and automotive. One common design trend across those domains seeks to reduce the number of computing devices embedded in them by integrating software applications of different criticality levels into one and the same onboard computer. A safety-savvy design approach however requires isolation among components of different criticality, to prevent unintended reciprocal interference across them. Isolation is traditionally achieved through partitioning. Partitioning, however, incurs low resource utilization as cautionary margins are used to inflate partition budgets over their anticipated needs. This situation has prompted research into alternative ways to integration that can safely afford higher levels of utilization. The Mixed-Criticality (MC) approach, which concentrates on the CPU scheduling problem, has yielded a large body of research results that show considerable gains in sustained utilization, but it has yet to meet all of the isolation requirements of safety-critical systems. This work presents a solution to augment a state-of-the-art MC solution with efficient and effective spatial isolation capabilities. Experimental results show that our solution provides adequate guarantees of temporal and spatial isolation with very small runtime overhead.