Journal of Systems Architecture最新文献

After more than ten years of development, the application of blockchain has expanded beyond the financial field to include other sectors such as E-government and the medical field. One of the most renowned blockchain platforms is Hyperledger Fabric, which is widely adopted by existing works for managing digital evidences ($DE$s). However, these works overlook the distinct differences between $DE$s and token-transfer transactions and often adopt the full implementation of Hyperledger Fabric, leveraging chaincode to manage the hash of $DE$s while keeping the original data off-chain to conserve storage resources. This approach poses challenges such as off-chain data loss, reduced data verification efficiency, and increased resource consumption. In this paper, we introduce a lightweight storage mechanism called Blockchain $Zhengju$ Keeper (BZK) that addresses these issues. In BZK, we subtract Hyperledger Fabric by (1) modifying the endorsement policy to reduce the risk of off-chain data loss, (2) simplifying the $DE$ upload-onchain process while keeping the parallel execution, and (3) abandoning chaincode for $DE$ verification to reduce latency. Comprehensive simulation experiments demonstrate the practicality of the proposed mechanism. Furthermore, compared to Hyperledger Fabric, BZK can reduce storage resource consumption by 68% and lower verification latency by 97%.

Edge computing has been emerging as a popular scenario for model inference. However, the inference performance on edge devices (e.g., Multi-Core DSP, FGPA, etc.) suffers from inefficiency due to the lack of highly optimized inference frameworks. Previous model inference frameworks are mainly developed in an operator-centric way, which provides insufficient acceleration to edge-based inference. Besides, the operator-centric framework incurs significant costs for continuous development and maintenance.

Targeting the existing drawbacks of operator-centric frameworks, we design Xenos, which can automatically conduct dataflow-centric optimization of the computation graph and accelerate inference in two dimensions. Vertically, Xenos develops operator linking technique to improve data locality by restructuring the inter-operator dataflow. Horizontally, Xenos develops DSP-aware operator split technique to enable higher parallelism across multiple DSP units. Our evaluation demonstrates the effectiveness of vertical and horizontal dataflow optimization, which reduce the inference time by 15.0%–84.9% and 17.9%–89.9% , respectively. Besides, Xenos also outperforms the widely-used TVM by 1.1$\times$–1.9$\times$. Moreover, we extend Xenos to a distributed solution, which we call d-Xenos. d-Xenos employs multiple edge devices to jointly conduct the inference task and achieves a speedup of 3.68$\times$–3.78$\times$ compared with the single device.

Long Short-Term Memory Networks (LSTMs) are pivotal in on-device time series analysis for embedded systems, particularly for managing sensor data streams. Yet, their deployment on resource-constrained embedded devices presents notable challenges. In response, we introduce a novel parameterized architecture for LSTM accelerators designed explicitly for embedded Field-Programmable Gate Arrays (FPGAs). Our approach involves strategic design choices, such as employing computationally efficient activation functions and optimizing clock frequency with a pipelined Arithmetic Logic Unit (ALU). These decisions drive our architecture towards enhanced energy efficiency while maintaining adaptability across diverse application scenarios. A key feature of our architecture is its configurable parameters, which allow for tailored optimization through the optional use of Digital Signal Processor Slices for ALUs and the selective implementation of activation functions. Our empirical evaluations conducted on the Spartan-7 XC7S15 FPGA demonstrate the robustness of our methodology, achieving a 2.33$\times$ improvement in energy efficiency over previous solutions. Furthermore, our study examines the correlation between memory resource types and energy efficiency across various LSTM model sizes. Impressively, even with a 9$\times$ increase in the hidden size of the LSTM cell, our accelerator maintains an energy efficiency of 10.03 GOP/s/W, with only a minor decrease of 14.65%. However, it is critical to note that our current design is not yet optimized for larger FPGA models such as the Spartan-7 XC7S25 and XC7S50. For these models, timing constraints, rather than resource limitations, pose challenges to scaling, highlighting a potential area for future optimization.

Non-functional requirements related to safety, security, and timeliness have made cyber–physical systems (CPS) initially reluctant to their integration with blockchain technology. Despite the multiple advantages of blockchain like improved data security and traceability, the main reasons that have slowed down its adoption in CPS still remain. Examples of these are the inherent overhead of accessing the distributed ledger and the security incidents that a number of blockchain networks have suffered since its inception. This paper presents VelogCPS, a novel middleware that guarantees that logic and data managed by blockchain networks of cyber–physical systems are verified and generated by legitimate sources. Thus, VelogCPS avoids a kind of security incidents that impact the authenticity and integrity of the logic and data managed in blockchain networks. By authenticity we refer to provenance authenticity of the involved smart contracts, i.e., the perfect matching between the advertised source-code and the version deployed to the network. Our framework provides a safe blockchain network as it ensures that the entities that participate to a CPS use solely authentic logic. We do this by leveraging block verifier services and enforcing them through the operation workflow. As a result, the middleware guarantees that the participating entities use and share authentic logic. The proposed framework is validated through its implementation on a real blockchain network, employing actual smart contract verifier logic, and through the exhaustive analysis of the temporal behaviour and overhead of the major operations; the obtained results ensure its utility for time-sensitive sytems like CPS and IoT.

The emergence of the Internet of Medical Things (IoMT) has presented numerous opportunities for the healthcare industry. It is anticipated to enhance the quality and efficiency of medical services, thus enhancing people’s overall quality of life. However, frequently occurring medical data leakage makes the protection of medical data and privacy in IoMT become a critical issue. Among the solutions, attribute-based encryption (ABE) has been a very promising solution due to its flexible and fine-grained access control to encrypted data. However, the majority of current ABE schemes are based on bilinear pairing and are vulnerable to quantum attacks. The available of multi-authority ABE schemes over lattice only support a single policy such as threshold or AND gate, and lack the ability to implement user or attribute revocation in a flexible manner. For the special algebra structure of the lattice based scheme, how to overcome them is still a challenge at present. Aiming at the above, we propose a novel multi-authority key-policy attribute based encryption (RM-KP-ABE) based on the Ring Learning With Errors (RLWE) assumption. It supports multi-valued attributes and $\{0,1\}$-LSSS access policy. This scheme allows multiple authorities to participate in key distribution and enables attribute revocation when dynamic users change their situation. $\{0,1\}$-LSSS access policy makes the proposal get highly expressive which supports any monotonic boolean formula. Security analysis and performance evaluations demonstrate that our scheme is secure and efficient.

Recently, Gong et al. proposed a Certificateless Aggregate Signature (CLAS) scheme (shorted by PCAS) with conditional privacy-preserving without bilinear pairing for Vehicular Ad-hoc Networks (VANETs). Unfortunately, after analyzing security, the PCAS scheme fails to satisfy the necessary unlinkability in VANETs and is vulnerable to the public key replacement forgery attack of the Type-I adversary. Subsequently, this article analyzes the causes of these two security issues in detail and proposes an improved CLAS scheme for VANETs (called IPCAS). Through security analysis, this article proves that the IPCAS is existentially unforgeable under the adaptive chosen message attacks against Type-I and Type-II adversaries in the random oracle model, and satisfies the necessary security and privacy requirements in VANETs, including unlinkability. Finally, the performance analysis results show that compared to PCAS for single message and $n$ aggregate messages $(n=1000)$, the computational overhead of IPCAS is reduced by 20.01% and 49.08% respectively, and the communication overhead is reduced by 18.75% and 28.14% respectively. Therefore, IPCAS not only makes up for the security vulnerabilities of PCAS but also has better performance.

Hybrid memory systems integrate a variety of memory technologies, effectively expanding the main memory capacity to meet the demands of emerging big data applications. Hybrid memory systems exhibit disparities in their heterogeneous memory components’ access speeds. Dynamic page scheduling to ensure memory access predominantly occurs in the faster memory components is essential for optimizing the performance of hybrid memory systems. Traditional history schedulers are unable to predict irregular memory accesses. Therefore, recent works attempt to optimize page scheduling by predicting their hotness using neural network models. However, they face two crucial challenges: one is the page explosion problem caused by the massive number of pages and the other is the new pages problem due to shifting memory access regions over time. To address these two challenges, we propose PatternS, an intelligent hybrid memory scheduler driven by page pattern recognition. Based on the insight into the similarities between memory access patterns, we proposed a Page Pattern Recognizer to identify pages with similar patterns and manage them as groups. PatternS is also capable of categorizing new pages into pre-identified patterns using short-term access information, enabling them to be predicted by the trained model. Experimental results demonstrate that our approach outperforms state-of-the-art intelligent schedulers regarding effectiveness and cost.

Smart grid is an efficient and reliable technical framework for controlling computers and automation equipment, and how to ensure the communication security in smart grid is an important issue. Cryptographic authentication scheme is a feasible solution, and the existing authentication schemes for smart grid seek to ensure better performance. Some existing authentication schemes lack comprehensive security considerations and have security or privacy vulnerabilities, which makes them vulnerable to specific attacks. The paper reviews a recent scheme ISG-SLAS (Yu and Park, 2022) and analyzes its potential insecure aspects in detail, including unable to resist ESL attack, cannot provide un-traceability and etc. To this end, the paper designs an improved authentication scheme for smart grid based on symmetric cryptography. Through informal security analyses and formal security analyses with real-or-random (ROR) model and Scyther platform, the security of the proposed scheme is demonstrated. From the perspective of performance, the proposed scheme is compared with ten advanced authentication schemes for smart grid, and the results show that the proposed scheme excels other recent schemes in computational overhead, communication overhead and storage overhead, reduced by 10.1%, 30.8% and 36.1% of ISG-SLAS and 58.9%, 64.1% and 24.3% of the average value of all alternatives respectively.

Emerging hybrid memory technologies composed of non-volatile memories (NVM) and DRAMs exhibit significant access speeds and capacity improvement. High application performance is feasible by dynamic migration (or relocation) of pages (data) between the memory types. While NVM is used for its density during memory allocation, moving write-intensive pages from NVM to DRAM helps to improve the execution and response time of applications. Existing techniques propose solutions to dynamically identify the pages that need to be moved immediately or in regular intervals. Such an immediate or interval-based rigid migration regime may hamper the service of the regular memory requests, which in turn affects the memory service rate.

To alleviate the impact on service rate and improve the quality-of-service (QoS) of the device, this paper proposes a scheduling method to identify the instant at which to migrate the eligible page. Along with regular memory requests, these eligible migration candidate pages are given reserved time slots by taking into account the current memory request rate. Our proposed methods aim to optimize the migration overheads by avoiding unnecessary migrations and at the same time guaranteeing future accesses to the migrated pages. This results in improved execution time and memory response time for the applications.

Silicon nanophotonics, with its high-speed, low-loss optical interconnects, and high computation capabilities, is seen as one of the promising technologies that can easily enable the transition from low data computation systems to high data computation systems. By providing faster and more energy-efficient communication, silicon nanophotonics is helping to drive the development of more powerful and efficient computing systems that can handle larger amounts of data.

These advantages of silicon nanophotonics have been leveraged by academia and industry to design the alternative for electrical interconnects, i.e., Optical Network-on-Chip (ONoC). The ONoCs offer higher bandwidth and lower power consumption communication framework as compared to the electrical interconnects. It is expected that the electrical interconnects will continue to be replaced by optical interconnects as the demand for higher bandwidth and faster communication continues to grow. However, there are some challenges in the design of optical interconnects, some of which are attributed to the intrinsic nature of silicon nanophotonic devices such as fabrication challenges and some are associated solely with the ONoCs such as high static power consumption. The research community has been actively involved in handling these challenges in order to fully realize the silicon nanophotonics for communication and computation.

In this research article, we present a comprehensive survey of the current state-of-the-art ONoCs, including their design, fabrication, and performance. We also provide an overview of the significant challenges and limitations associated with ONoCs and discuss potential solutions. The goal of this survey is to provide a comprehensive overview of the field and to inform future research directions in the area of ONoCs.