Pub Date : 2023-01-01DOI: 10.1587/elex.20.20230249
Qinghua Liu, L. Kang, Xinwei Duan, Yangbo Liu, Zhi Zhang
{"title":"Efficient model predictive current control for the grid-connected quasi-Z-source T-type inverter","authors":"Qinghua Liu, L. Kang, Xinwei Duan, Yangbo Liu, Zhi Zhang","doi":"10.1587/elex.20.20230249","DOIUrl":"https://doi.org/10.1587/elex.20.20230249","url":null,"abstract":"","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"1 1","pages":"20230249"},"PeriodicalIF":0.8,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67302693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/elex.20.20230268
Shoki Asami, N. Yokota, W. Kobayashi, T. Shindo, H. Yasaka
{"title":"Numerical analysis of negative chirp operation in hybrid modulation semiconductor lasers","authors":"Shoki Asami, N. Yokota, W. Kobayashi, T. Shindo, H. Yasaka","doi":"10.1587/elex.20.20230268","DOIUrl":"https://doi.org/10.1587/elex.20.20230268","url":null,"abstract":"","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"60 1","pages":"20230268"},"PeriodicalIF":0.8,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67302757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/elex.20.20230321
W. Ge, Xiaotong Wang, Yi Xie
{"title":"Analysis of strong magnetic environment interference of inspection rotary wing UAV","authors":"W. Ge, Xiaotong Wang, Yi Xie","doi":"10.1587/elex.20.20230321","DOIUrl":"https://doi.org/10.1587/elex.20.20230321","url":null,"abstract":"","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"1 1","pages":"20230321"},"PeriodicalIF":0.8,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67302796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/elex.20.20230450
Xuewen Yan, Chen Cheng, Juan Hu, Yuanyuan Bai, Wenwen Zhang
This study focuses on the improvement of the performance of high-frequency current transformer (HFCT) for Partial Discharge Measurement and thus reveals a new design method of HFCT. An annular nickel-zinc ferrite is used as the magnetic core of the HFCT, and the parameters such as the number of winding turns and the diameter of the enameled wire are optimized. To test the HFCT, an experimental test platform is built according to the technical specifications of high-frequency partial discharge charged detection equipment. The test contents of the HFCT include transmission impedance, sensitivity, anti-interference characteristics, etc. The test results show that the new HFCT has a good response performance from 1MHz to 25MHz, the maximum transmission impedance value can reach 16.4mV/mA, the apparent charge of 5pC can be measured and signal-to-noise ratio is greater than 2:1. In addition, the designed HFCT also has good anti-interference and stability. With the self-designed low-power portable high-voltage cable insulation tester (mainly including signal conditioning circuit and data acquisition circuit), in the high-voltage laboratory, built a simulated discharge experimental circuit on the plate-pin, ball-ball two discharge models for high-voltage testing, the use of the developed HFCT to detect the partial discharge of the insulating polyethylene medium. The test results show that the HFCT can detect the partial discharge pulse signals before breakdown, with accurate data and reliable performance.
{"title":"Design and Implementation of A novel High-frequency Current Transformer for Partial Discharge Measurements","authors":"Xuewen Yan, Chen Cheng, Juan Hu, Yuanyuan Bai, Wenwen Zhang","doi":"10.1587/elex.20.20230450","DOIUrl":"https://doi.org/10.1587/elex.20.20230450","url":null,"abstract":"This study focuses on the improvement of the performance of high-frequency current transformer (HFCT) for Partial Discharge Measurement and thus reveals a new design method of HFCT. An annular nickel-zinc ferrite is used as the magnetic core of the HFCT, and the parameters such as the number of winding turns and the diameter of the enameled wire are optimized. To test the HFCT, an experimental test platform is built according to the technical specifications of high-frequency partial discharge charged detection equipment. The test contents of the HFCT include transmission impedance, sensitivity, anti-interference characteristics, etc. The test results show that the new HFCT has a good response performance from 1MHz to 25MHz, the maximum transmission impedance value can reach 16.4mV/mA, the apparent charge of 5pC can be measured and signal-to-noise ratio is greater than 2:1. In addition, the designed HFCT also has good anti-interference and stability. With the self-designed low-power portable high-voltage cable insulation tester (mainly including signal conditioning circuit and data acquisition circuit), in the high-voltage laboratory, built a simulated discharge experimental circuit on the plate-pin, ball-ball two discharge models for high-voltage testing, the use of the developed HFCT to detect the partial discharge of the insulating polyethylene medium. The test results show that the HFCT can detect the partial discharge pulse signals before breakdown, with accurate data and reliable performance.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135158806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A capacitor-coupled stacked-based sense amplifier (CC-STSA) is proposed to compensate the input-referred offset voltage (VOS), which dictates the minimum required bitline swing for a reliable read operation of static random access memory (SRAM). The data-aware coupled capacitors are employed to dynamically tune the driving ability of sensing transistors according to the data supposed to be read, thus improving the offset tolerance of sense amplifier (SA). Compared with the conventional current latch-type SA (CLSA), the simulation results in 55-nm CMOS technology show that the proposed scheme achieves more than 4.17X of the standard deviation of VOS (σOS) reduction across the range of supply voltage from 0.6V to 1.2V and reduce the read energy consumption and read delay to 54.9% and 45.5% respectively. Furthermore, the proposed scheme reduces the σOS by 2.19X compared to DIBBSA on average.
{"title":"A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM","authors":"Pengyuan Zhao, Huidong Zhao, Jialu Yin, Zhi Li, Shushan Qiao","doi":"10.1587/elex.20.20230484","DOIUrl":"https://doi.org/10.1587/elex.20.20230484","url":null,"abstract":"A capacitor-coupled stacked-based sense amplifier (CC-STSA) is proposed to compensate the input-referred offset voltage (VOS), which dictates the minimum required bitline swing for a reliable read operation of static random access memory (SRAM). The data-aware coupled capacitors are employed to dynamically tune the driving ability of sensing transistors according to the data supposed to be read, thus improving the offset tolerance of sense amplifier (SA). Compared with the conventional current latch-type SA (CLSA), the simulation results in 55-nm CMOS technology show that the proposed scheme achieves more than 4.17X of the standard deviation of VOS (σOS) reduction across the range of supply voltage from 0.6V to 1.2V and reduce the read energy consumption and read delay to 54.9% and 45.5% respectively. Furthermore, the proposed scheme reduces the σOS by 2.19X compared to DIBBSA on average.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135710802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/elex.20.20230428
Meng Guan, Mingyu Sun, Aixin Chen
This paper presents a dual-band (DB) high efficiency power amplifier (PA) with two adjustable transmission zeros (TZs). The parallel Two Section Transmission Line (TSTL) is introduced in the impedance matching network (IMN), generating adjustable TZs and compensating for the resulting unrelated difference of admittance at DB fundamentals, which enables the DB IMN exhibits adjustable TZs out-of-band. The matching bandwidth of the DB IMN is further analyzed to seek the target impedance for broadband DB matching. The series TSTL is employed to modulate the target impedance to the impedance of the drain at DB fundamentals while satisfying the high efficiency operating conditions at DB harmonics. For validation, a DB PA is designed and fabricated with a Cree CGH40010F GaN transistor. The fabricated DB PA features the saturated output power of 42.6 dBm and 42.0 dBm with the Power-Added Efficiency (PAE) of 66.1% and 67.8% at 0.9 GHz and 2.4 GHz, respectively. Specially, the bandwidth of the DB PA is 150 MHz, and two adjustable TZs are shown out-of-band.
{"title":"Dual band power amplifier with adjustable transmission zeros based on the parallel and series two section transmission line","authors":"Meng Guan, Mingyu Sun, Aixin Chen","doi":"10.1587/elex.20.20230428","DOIUrl":"https://doi.org/10.1587/elex.20.20230428","url":null,"abstract":"This paper presents a dual-band (DB) high efficiency power amplifier (PA) with two adjustable transmission zeros (TZs). The parallel Two Section Transmission Line (TSTL) is introduced in the impedance matching network (IMN), generating adjustable TZs and compensating for the resulting unrelated difference of admittance at DB fundamentals, which enables the DB IMN exhibits adjustable TZs out-of-band. The matching bandwidth of the DB IMN is further analyzed to seek the target impedance for broadband DB matching. The series TSTL is employed to modulate the target impedance to the impedance of the drain at DB fundamentals while satisfying the high efficiency operating conditions at DB harmonics. For validation, a DB PA is designed and fabricated with a Cree CGH40010F GaN transistor. The fabricated DB PA features the saturated output power of 42.6 dBm and 42.0 dBm with the Power-Added Efficiency (PAE) of 66.1% and 67.8% at 0.9 GHz and 2.4 GHz, respectively. Specially, the bandwidth of the DB PA is 150 MHz, and two adjustable TZs are shown out-of-band.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135953558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/elex.20.20230444
Bulai Wang, Jingheng Zhu, Zixin Li, Yecheng Li
To improve the operational performance of Permanent Magnet Synchronous Motors (PMSM), a new voltage optimization algorithm is proposed. This algorithm is based on Particle Swarm Optimization (PSO) and incorporates two improvements: online optimization and secondary optimization. The improved PSO (IPSO) algorithm is applied to Dual-Vector Model Predictive Control (DVMPCC) for simulation and experimental research. The results show that, compared to DVMPCC, with similar speed response, the current ripple is reduced by 16.22% and the steady-state speed fluctuation is reduced by 65.14%. This indicates that the proposed algorithm is feasible and effectively improves the operational performance of the system.
{"title":"An optimization algorithm used in PMSM model predictive control","authors":"Bulai Wang, Jingheng Zhu, Zixin Li, Yecheng Li","doi":"10.1587/elex.20.20230444","DOIUrl":"https://doi.org/10.1587/elex.20.20230444","url":null,"abstract":"To improve the operational performance of Permanent Magnet Synchronous Motors (PMSM), a new voltage optimization algorithm is proposed. This algorithm is based on Particle Swarm Optimization (PSO) and incorporates two improvements: online optimization and secondary optimization. The improved PSO (IPSO) algorithm is applied to Dual-Vector Model Predictive Control (DVMPCC) for simulation and experimental research. The results show that, compared to DVMPCC, with similar speed response, the current ripple is reduced by 16.22% and the steady-state speed fluctuation is reduced by 65.14%. This indicates that the proposed algorithm is feasible and effectively improves the operational performance of the system.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135008116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/elex.20.20230446
Ang Yuan, Huidong Zhao, Zhi Li, Shushan Qiao
This paper proposes a novel sense-amplifier-based flip-flop (SAFF) applied in low-power, high-speed operation. With the employment of the pre-charge control technique and shut-off transistor, the power and delay of the proposed SAFF are significantly reduced. Furthermore, the proposed SAFF can provide low-voltage operation. Post-layout simulation results based on the SMIC 55 nm CMOS process show that the proposed SAFF achieves a 28.9% reduction in the CLK-to-Q delay and a 53.2% decrease in power (25% input data switching activity) and the power-delay-product of the proposed SAFF shows 3.0× improvement compared with the conventional SAFF.
{"title":"A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application","authors":"Ang Yuan, Huidong Zhao, Zhi Li, Shushan Qiao","doi":"10.1587/elex.20.20230446","DOIUrl":"https://doi.org/10.1587/elex.20.20230446","url":null,"abstract":"This paper proposes a novel sense-amplifier-based flip-flop (SAFF) applied in low-power, high-speed operation. With the employment of the pre-charge control technique and shut-off transistor, the power and delay of the proposed SAFF are significantly reduced. Furthermore, the proposed SAFF can provide low-voltage operation. Post-layout simulation results based on the SMIC 55 nm CMOS process show that the proposed SAFF achieves a 28.9% reduction in the CLK-to-Q delay and a 53.2% decrease in power (25% input data switching activity) and the power-delay-product of the proposed SAFF shows 3.0× improvement compared with the conventional SAFF.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135052515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, a 30MHz-3GHz 10W single pole double throw (SPDT) switch with 3.3V low supply voltage fabricated in 0.5um GaAs pHEMT technology process is presented. A feedforward capacitor pair is introduced in each stacked FET, which makes full use of the advantages of high breakdown voltage (VBDG) of GaAs process under low supply voltage and enhances the power handling of each FET unit. Under specific power level, switch with reduced number of stacked FETs and low insertion loss are achieved. Meanwhile, uniform-partial-voltage stacked FET units with different gate width is applied to the switch design, which solves the problem of non-uniform partial voltage caused by parasitic capacitance(Cpd) between stacked FETs. As a result, the power handling of the switch is higher than 40dBm under continuous wave. Besides, the switch designed in this letter achieves 0.5dB insertion loss at 1.5GHz and the input and output return loss is less than -18dB at the whole frequency band. The test results verify the accuracy of the theoretical analysis.
{"title":"A low-supply-voltage high-power-handling stacked SPDT switch based on feedforward capacitors","authors":"Jiyang Shen, Li Li, Chen Jin, Qingping Song, Kaijiang Xu, Chao Luo, Fuhai Zhao, Zhiyu Wang, Faxin Yu, Hua Chen","doi":"10.1587/elex.20.20230360","DOIUrl":"https://doi.org/10.1587/elex.20.20230360","url":null,"abstract":"In this letter, a 30MHz-3GHz 10W single pole double throw (SPDT) switch with 3.3V low supply voltage fabricated in 0.5um GaAs pHEMT technology process is presented. A feedforward capacitor pair is introduced in each stacked FET, which makes full use of the advantages of high breakdown voltage (VBDG) of GaAs process under low supply voltage and enhances the power handling of each FET unit. Under specific power level, switch with reduced number of stacked FETs and low insertion loss are achieved. Meanwhile, uniform-partial-voltage stacked FET units with different gate width is applied to the switch design, which solves the problem of non-uniform partial voltage caused by parasitic capacitance(Cpd) between stacked FETs. As a result, the power handling of the switch is higher than 40dBm under continuous wave. Besides, the switch designed in this letter achieves 0.5dB insertion loss at 1.5GHz and the input and output return loss is less than -18dB at the whole frequency band. The test results verify the accuracy of the theoretical analysis.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135955406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：