Pub Date : 2021-01-27DOI: 10.1007/s10617-021-09245-x
Mostafa Rizk, Amer Baghdadi, Michel Jezequel, Yasser Mohanna, Youssef Atat
The emerging flexibility need in designing application-specific processors dedicated for modules of digital receiver imposes a new design metric, which is added to the requirements of efficiency and productivity. In order to cope with the emerging flexibility requirement combined with the best performance efficiency, many application-specific processor design approaches have been proposed and investigated. In general, available design approaches that adopt dynamic scheduling of instructions add an overhead due to the instruction decoding. To minimize this overhead, several approaches have been introduced, which opt static scheduling. In this context, No-Instruction-Set-Computer (NISC) concept has been introduced to design application-specific processors without an instruction set. NISC concept proposes that there is no need to first design and then use an instruction set when the hardware is programmed by its designers rather than its users. NISC designing approach offers a good compromise between flexibility, productivity, and quality for the design of a digital system. In our work, NISC approach is explored through the design of flexible and efficient architectures dedicated for digital communication applications which fulfill the requirements imposed by multiple emergent communication standards. This paper introduces briefly the NISC concept and the corresponding design methodology. Also, it provides an overview of the related design approach. In addition, the relevance of NISC in realizing flexible and efficient implementation in the domain of digital communication is demonstrated through two case studies on MIMO turbo detection and universal turbo demapping. Both designed NISC-based architectures have been compared to state-of-the-art ASIP-based architectures using similar computational resources and supporting same flexibility parameters. The obtained results show that the proposed NISC-based architectures provide a significant improvement in execution performance while having reduced implementation costs. The results also illustrates how the control memory requirements depend on the application and the devised architecture choices. In the detector module, the adopted re-usability of allocated resources imposes separate controlling of each component; hence, additional control signals are implied. Whereas for the demapper module, implemented hardware components are considered to perform specific operations and to deal with the same type of data; hence, the number of control signals can be reduced significantly.
{"title":"No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping","authors":"Mostafa Rizk, Amer Baghdadi, Michel Jezequel, Yasser Mohanna, Youssef Atat","doi":"10.1007/s10617-021-09245-x","DOIUrl":"https://doi.org/10.1007/s10617-021-09245-x","url":null,"abstract":"<p>The emerging flexibility need in designing application-specific processors dedicated for modules of digital receiver imposes a new design metric, which is added to the requirements of efficiency and productivity. In order to cope with the emerging flexibility requirement combined with the best performance efficiency, many application-specific processor design approaches have been proposed and investigated. In general, available design approaches that adopt dynamic scheduling of instructions add an overhead due to the instruction decoding. To minimize this overhead, several approaches have been introduced, which opt static scheduling. In this context, No-Instruction-Set-Computer (NISC) concept has been introduced to design application-specific processors without an instruction set. NISC concept proposes that there is no need to first design and then use an instruction set when the hardware is programmed by its designers rather than its users. NISC designing approach offers a good compromise between flexibility, productivity, and quality for the design of a digital system. In our work, NISC approach is explored through the design of flexible and efficient architectures dedicated for digital communication applications which fulfill the requirements imposed by multiple emergent communication standards. This paper introduces briefly the NISC concept and the corresponding design methodology. Also, it provides an overview of the related design approach. In addition, the relevance of NISC in realizing flexible and efficient implementation in the domain of digital communication is demonstrated through two case studies on MIMO turbo detection and universal turbo demapping. Both designed NISC-based architectures have been compared to state-of-the-art ASIP-based architectures using similar computational resources and supporting same flexibility parameters. The obtained results show that the proposed NISC-based architectures provide a significant improvement in execution performance while having reduced implementation costs. The results also illustrates how the control memory requirements depend on the application and the devised architecture choices. In the detector module, the adopted re-usability of allocated resources imposes separate controlling of each component; hence, additional control signals are implied. Whereas for the demapper module, implemented hardware components are considered to perform specific operations and to deal with the same type of data; hence, the number of control signals can be reduced significantly.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"51 5","pages":""},"PeriodicalIF":1.4,"publicationDate":"2021-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-16DOI: 10.1007/s10617-020-09244-4
Saman Payvar, Maxime Pelcat, Timo D. Hämäläinen
Efficient usage of heterogeneous computing architectures requires distribution of the workload on available processing elements. Traditionally, the mapping is based on information acquired from application profiling and utilized in architecture exploration. To reduce the amount of manual work required, statistical application modeling and architecture modeling can be combined with exploration heuristics. While the application modeling side of the problem has been studied extensively, architecture modeling has received less attention. Linear System Level Architecture (LSLA) is a Model of Architecture that aims at separating the architectural concerns from algorithmic ones when predicting performance. This work builds on the LSLA model and introduces non-linear semantics, specifically to support GPU performance and power modeling, by modeling also the degree of parallelism. The model is evaluated with three signal processing applications with various workload distributions on a desktop GPU and mobile GPU. The measured average fidelity of the new model is 93% for performance, and 84% for power, which can fit design space exploration purposes.
{"title":"A model of architecture for estimating GPU processing performance and power","authors":"Saman Payvar, Maxime Pelcat, Timo D. Hämäläinen","doi":"10.1007/s10617-020-09244-4","DOIUrl":"https://doi.org/10.1007/s10617-020-09244-4","url":null,"abstract":"<p>Efficient usage of heterogeneous computing architectures requires distribution of the workload on available processing elements. Traditionally, the mapping is based on information acquired from application profiling and utilized in architecture exploration. To reduce the amount of manual work required, statistical application modeling and architecture modeling can be combined with exploration heuristics. While the application modeling side of the problem has been studied extensively, architecture modeling has received less attention. Linear System Level Architecture (LSLA) is a Model of Architecture that aims at separating the architectural concerns from algorithmic ones when predicting performance. This work builds on the LSLA model and introduces non-linear semantics, specifically to support GPU performance and power modeling, by modeling also the degree of parallelism. The model is evaluated with three signal processing applications with various workload distributions on a desktop GPU and mobile GPU. The measured average fidelity of the new model is 93% for performance, and 84% for power, which can fit design space exploration purposes.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"37 4","pages":""},"PeriodicalIF":1.4,"publicationDate":"2021-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-04DOI: 10.1007/s10617-020-09243-5
Janaina Schwarzrock, M. Jordan, Guilherme Korol, C. C. D. Oliveira, A. Lorenzon, Mateus Beck Rutzig, Antonio Carlos S. Beck
{"title":"Dynamic concurrency throttling on NUMA systems and data migration impacts","authors":"Janaina Schwarzrock, M. Jordan, Guilherme Korol, C. C. D. Oliveira, A. Lorenzon, Mateus Beck Rutzig, Antonio Carlos S. Beck","doi":"10.1007/s10617-020-09243-5","DOIUrl":"https://doi.org/10.1007/s10617-020-09243-5","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"25 1","pages":"135 - 160"},"PeriodicalIF":1.4,"publicationDate":"2020-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-020-09243-5","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52170640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
License plates are the primary source of vehicle identification data used in a wide range of applications including law enforcement, electronic tolling, and access control amongst others. License plate detection (LPD) is a critical process in automatic license plate recognition (ALPR) that reduces complexity by delimiting the search space for subsequent ALPR stages. It is complicated by unfavourable factors including environmental conditions, occlusion, and license plate variation. As such, it requires training models on substantial volumes of relevant images per use case. In 2018, the new Mercosur standard came in to effect in four South American countries. Access to large volumes of actual Mercosur license plates with sufficient presentation variety is a significant challenge for training supervised models for LPD, thereby adversely impacting the efficacy of ALPR in Mercosur countries. This paper presents a novel license plate embedding methodology for generating large volumes of accurate Mercosur license plate images sufficient for training supervised LPD. We validate this methodology with a deep learning-based ALPR using a convolutional neural network trained exclusively with synthetic data and tested with real parking lot and traffic camera images. Experiment results achieve detection accuracy of 95% and an average running time of 40 ms.
{"title":"Synthetic image generation for training deep learning-based automated license plate recognition systems on the Brazilian Mercosur standard","authors":"Gilles Silvano, Vinícius Ribeiro, Vitor Greati, Aguinaldo Bezerra, Ivanovitch Silva, Patricia Takako Endo, Theo Lynn","doi":"10.1007/s10617-020-09241-7","DOIUrl":"https://doi.org/10.1007/s10617-020-09241-7","url":null,"abstract":"<p>License plates are the primary source of vehicle identification data used in a wide range of applications including law enforcement, electronic tolling, and access control amongst others. License plate detection (LPD) is a critical process in automatic license plate recognition (ALPR) that reduces complexity by delimiting the search space for subsequent ALPR stages. It is complicated by unfavourable factors including environmental conditions, occlusion, and license plate variation. As such, it requires training models on substantial volumes of relevant images per use case. In 2018, the new Mercosur standard came in to effect in four South American countries. Access to large volumes of actual Mercosur license plates with sufficient presentation variety is a significant challenge for training supervised models for LPD, thereby adversely impacting the efficacy of ALPR in Mercosur countries. This paper presents a novel license plate embedding methodology for generating large volumes of accurate Mercosur license plate images sufficient for training supervised LPD. We validate this methodology with a deep learning-based ALPR using a convolutional neural network trained exclusively with synthetic data and tested with real parking lot and traffic camera images. Experiment results achieve detection accuracy of 95% and an average running time of 40 ms.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"40 3","pages":""},"PeriodicalIF":1.4,"publicationDate":"2020-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-07DOI: 10.1007/s10617-020-09240-8
Mateus Martínez de Lucena, R. Scheffel, A. A. Fröhlich
{"title":"An analysis of the Gateway Integrity Checking Protocol from the perspective of Intrusion Detection Systems","authors":"Mateus Martínez de Lucena, R. Scheffel, A. A. Fröhlich","doi":"10.1007/s10617-020-09240-8","DOIUrl":"https://doi.org/10.1007/s10617-020-09240-8","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"25 1","pages":"89 - 111"},"PeriodicalIF":1.4,"publicationDate":"2020-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-020-09240-8","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46455093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-03DOI: 10.1007/s10617-020-09238-2
S. H. Mozafari, B. Meyer
{"title":"Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors","authors":"S. H. Mozafari, B. Meyer","doi":"10.1007/s10617-020-09238-2","DOIUrl":"https://doi.org/10.1007/s10617-020-09238-2","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"24 1","pages":"249 - 266"},"PeriodicalIF":1.4,"publicationDate":"2020-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-020-09238-2","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52170620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The maglev train has been successful in practice as a new type of ground transportation. Owing to the inherent nonlinearity and open-loop instability of the electromagnetic suspension (EMS) system, an analogue or a digital controller is used to control the maglev trains’ stability. With the rapid development of embedded systems and artificial intelligence, intelligent digital control has begun to replace the conventional analogue control technology creating a new approach to the EMS control system. This paper proposes a hardware module for an embedded levitation controller based on digital signal processor and field programmable gate array, hence producing an open loop mathematical model of the embedded maglev control system. The deep learning controller is then developed based on a deep belief network (DBN) algorithm and a proportional integral derivative feedback controller. The simulations are conducted in the MATLAB environment after training the DBN. Simulation results are compared with those obtained from the conventional controller. Finally, experiments are implemented to examine the feasibility in practice of the application of the DBN into a maglev embedded control system. The system, with the proposed controller, can accurately track the target airgap of 8 mm. The maximum tracking error of sinusoidal trajectory is 0.17 mm and the maximum tracking error of step trajectory is 0.98 mm. Both simulation and experimental results are included in this paper to show that the proposed deep learning controller can be more robust and less complicated to implement in maglev control applications.
{"title":"Deep learning controller design of embedded control system for maglev train via deep belief network algorithm","authors":"Ding-gang Gao, You-gang Sun, Shi-hui Luo, Guo-bin Lin, Lai-sheng Tong","doi":"10.1007/s10617-020-09237-3","DOIUrl":"https://doi.org/10.1007/s10617-020-09237-3","url":null,"abstract":"<p>The maglev train has been successful in practice as a new type of ground transportation. Owing to the inherent nonlinearity and open-loop instability of the electromagnetic suspension (EMS) system, an analogue or a digital controller is used to control the maglev trains’ stability. With the rapid development of embedded systems and artificial intelligence, intelligent digital control has begun to replace the conventional analogue control technology creating a new approach to the EMS control system. This paper proposes a hardware module for an embedded levitation controller based on digital signal processor and field programmable gate array, hence producing an open loop mathematical model of the embedded maglev control system. The deep learning controller is then developed based on a deep belief network (DBN) algorithm and a proportional integral derivative feedback controller. The simulations are conducted in the MATLAB environment after training the DBN. Simulation results are compared with those obtained from the conventional controller. Finally, experiments are implemented to examine the feasibility in practice of the application of the DBN into a maglev embedded control system. The system, with the proposed controller, can accurately track the target airgap of 8 mm. The maximum tracking error of sinusoidal trajectory is 0.17 mm and the maximum tracking error of step trajectory is 0.98 mm. Both simulation and experimental results are included in this paper to show that the proposed deep learning controller can be more robust and less complicated to implement in maglev control applications.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"48 11","pages":""},"PeriodicalIF":1.4,"publicationDate":"2020-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-21DOI: 10.1007/s10617-020-09236-4
Nicolás Gammarano, Javier Schandy, Leonardo Steinfeld
{"title":"Reducing neighbor discovery time in sensor networks with directional antennas using dynamic contention resolution","authors":"Nicolás Gammarano, Javier Schandy, Leonardo Steinfeld","doi":"10.1007/s10617-020-09236-4","DOIUrl":"https://doi.org/10.1007/s10617-020-09236-4","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"1 1","pages":"223 - 247"},"PeriodicalIF":1.4,"publicationDate":"2020-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-020-09236-4","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52170592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}