Pub Date : 2022-09-14DOI: 10.1007/s10617-022-09265-1
Mostafa Khamis, Sameh El-Ashry, Mohamed Abdelsalam, M. El-Kharashi, A. Shalaby
{"title":"Emulation and verification framework for MPSoC based on NoC and RISC-V","authors":"Mostafa Khamis, Sameh El-Ashry, Mohamed Abdelsalam, M. El-Kharashi, A. Shalaby","doi":"10.1007/s10617-022-09265-1","DOIUrl":"https://doi.org/10.1007/s10617-022-09265-1","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"26 1","pages":"133 - 159"},"PeriodicalIF":1.4,"publicationDate":"2022-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42105549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1007/s10617-022-09259-z
I. Garcia-Vargas, Raouf Senhadji-Navarro
{"title":"Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing","authors":"I. Garcia-Vargas, Raouf Senhadji-Navarro","doi":"10.1007/s10617-022-09259-z","DOIUrl":"https://doi.org/10.1007/s10617-022-09259-z","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"26 1","pages":"83 - 103"},"PeriodicalIF":1.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46428563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-29DOI: 10.1007/s10617-022-09264-2
Sumanth Gudaparthi, R. Shrestha
{"title":"Selective register-file cache: an energy saving technique for embedded processor architecture","authors":"Sumanth Gudaparthi, R. Shrestha","doi":"10.1007/s10617-022-09264-2","DOIUrl":"https://doi.org/10.1007/s10617-022-09264-2","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"26 1","pages":"105 - 124"},"PeriodicalIF":1.4,"publicationDate":"2022-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43842123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-09DOI: 10.1007/s10617-022-09261-5
Lokesh Sivanandam, Uma Maheswari Oorkavalan, S. Periyasamy
{"title":"Retraction Note to: Test data compression for digital circuits using tetrad state skip scheme","authors":"Lokesh Sivanandam, Uma Maheswari Oorkavalan, S. Periyasamy","doi":"10.1007/s10617-022-09261-5","DOIUrl":"https://doi.org/10.1007/s10617-022-09261-5","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"26 1","pages":"127 - 127"},"PeriodicalIF":1.4,"publicationDate":"2022-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42907110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-09DOI: 10.1007/s10617-022-09260-6
K. Mathan, P. Kumar, Parthasarathy Panchatcharam, Gunasekaran Manogaran, R. Varadharajan
{"title":"Retraction Note to: A novel Gini index decision tree data mining method with neural network classifiers for prediction of heart disease","authors":"K. Mathan, P. Kumar, Parthasarathy Panchatcharam, Gunasekaran Manogaran, R. Varadharajan","doi":"10.1007/s10617-022-09260-6","DOIUrl":"https://doi.org/10.1007/s10617-022-09260-6","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"26 1","pages":"125 - 125"},"PeriodicalIF":1.4,"publicationDate":"2022-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48495438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-09DOI: 10.1007/s10617-022-09262-4
T. Murugeswari, S. Rathi
{"title":"Retraction Note to: QOS distributed routing protocol for mobile ad-hoc wireless networks using intelligent packet carrying systems","authors":"T. Murugeswari, S. Rathi","doi":"10.1007/s10617-022-09262-4","DOIUrl":"https://doi.org/10.1007/s10617-022-09262-4","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"26 1","pages":"129 - 129"},"PeriodicalIF":1.4,"publicationDate":"2022-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52170476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-04DOI: 10.1007/s10617-023-09272-w
S. Badri, Mukesh Saini, N. Goel
{"title":"Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems","authors":"S. Badri, Mukesh Saini, N. Goel","doi":"10.1007/s10617-023-09272-w","DOIUrl":"https://doi.org/10.1007/s10617-023-09272-w","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"1 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2022-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44474483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-23DOI: 10.1007/s10617-021-09257-7
M. Najam-ul-Islam, F. Zahra, A. Jafri, Roman Shah, Masood Ul Hassan, Muhammad Rashid
{"title":"Auto implementation of parallel hardware architecture for Aho-Corasick algorithm","authors":"M. Najam-ul-Islam, F. Zahra, A. Jafri, Roman Shah, Masood Ul Hassan, Muhammad Rashid","doi":"10.1007/s10617-021-09257-7","DOIUrl":"https://doi.org/10.1007/s10617-021-09257-7","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"24 3","pages":"29 - 53"},"PeriodicalIF":1.4,"publicationDate":"2022-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41331266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-14DOI: 10.1007/s10617-021-09258-6
Tiago Knorst, Julio Vicenzi, Michael G. Jordan, Jonathan H. de Almeida, Guilherme Korol, Antonio C. S. Beck, Mateus B. Rutzig
Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as such devices have severe time-to-market, binary compatibility should be maintained to avoid recurrent engineering, which is not considered in current embedded processors. This work visited a set of embedded applications showing the need for concurrent ILP and DLP exploitation. For that, we propose a Hybrid Multi-Target Binary Translator (HMTBT) to transparently exploit ILP and DLP by using a CGRA and ARM NEON engine as targeted accelerators. Results show that HMTBT transparently achieves 24% performance improvements and 54% energy savings over an OoO superscalar processor coupled to an ARM NEON engine. The proposed approach improves performance and energy in 10%, 24% over decoupled binary translators using the same accelerator with the same ILP and DLP capabilities.
{"title":"An energy efficient multi-target binary translator for instruction and data level parallelism exploitation","authors":"Tiago Knorst, Julio Vicenzi, Michael G. Jordan, Jonathan H. de Almeida, Guilherme Korol, Antonio C. S. Beck, Mateus B. Rutzig","doi":"10.1007/s10617-021-09258-6","DOIUrl":"https://doi.org/10.1007/s10617-021-09258-6","url":null,"abstract":"<p>Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as such devices have severe time-to-market, binary compatibility should be maintained to avoid recurrent engineering, which is not considered in current embedded processors. This work visited a set of embedded applications showing the need for concurrent ILP and DLP exploitation. For that, we propose a Hybrid Multi-Target Binary Translator (HMTBT) to transparently exploit ILP and DLP by using a CGRA and ARM NEON engine as targeted accelerators. Results show that HMTBT transparently achieves 24% performance improvements and 54% energy savings over an OoO superscalar processor coupled to an ARM NEON engine. The proposed approach improves performance and energy in 10%, 24% over decoupled binary translators using the same accelerator with the same ILP and DLP capabilities.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"06 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2022-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rapid development of Artificial Intelligence, Internet of Things, 5G, and other technologies, a number of emerging intelligent applications represented by image recognition, voice recognition, autonomous driving, and intelligent manufacturing have appeared. These applications require efficient and intelligent processing systems for massive data calculations, so it is urgent to apply better DNN in a faster way. Although, compared with GPU, FPGA has a higher energy efficiency ratio, and shorter development cycle and better flexibility than ASIC. However, FPGA is not a perfect hardware platform either for computational intelligence. This paper provides a survey of the latest acceleration work related to the familiar DNNs and proposes three new directions to break the bottleneck of the DNN implementation. So as to improve calculating speed and energy efficiency of edge devices, intelligent embedded approaches including model compression and optimized data movement of the entire system are most commonly used. With the gradual slowdown of Moore’s Law, the traditional Von Neumann Architecture generates a “Memory Wall” problem, resulting in more power-consuming. In-memory computation will be the right medicine in the post-Moore law era. More complete software/hardware co-design environment will direct researchers’ attention to explore deep learning algorithms and run the algorithm on the hardware level in a faster way. These new directions start a relatively new paradigm in computational intelligence, which have attracted substantial attention from the research community and demonstrated greater potential over traditional techniques.
{"title":"New paradigm of FPGA-based computational intelligence from surveying the implementation of DNN accelerators","authors":"Yang You, Yinghui Chang, Weikang Wu, Bingrui Guo, Hongyin Luo, Xiaojie Liu, Bijing Liu, Kairong Zhao, Shan He, Lin Li, Donghui Guo","doi":"10.1007/s10617-021-09256-8","DOIUrl":"https://doi.org/10.1007/s10617-021-09256-8","url":null,"abstract":"<p>With the rapid development of Artificial Intelligence, Internet of Things, 5G, and other technologies, a number of emerging intelligent applications represented by image recognition, voice recognition, autonomous driving, and intelligent manufacturing have appeared. These applications require efficient and intelligent processing systems for massive data calculations, so it is urgent to apply better DNN in a faster way. Although, compared with GPU, FPGA has a higher energy efficiency ratio, and shorter development cycle and better flexibility than ASIC. However, FPGA is not a perfect hardware platform either for computational intelligence. This paper provides a survey of the latest acceleration work related to the familiar DNNs and proposes three new directions to break the bottleneck of the DNN implementation. So as to improve calculating speed and energy efficiency of edge devices, intelligent embedded approaches including model compression and optimized data movement of the entire system are most commonly used. With the gradual slowdown of Moore’s Law, the traditional Von Neumann Architecture generates a “Memory Wall” problem, resulting in more power-consuming. In-memory computation will be the right medicine in the post-Moore law era. More complete software/hardware co-design environment will direct researchers’ attention to explore deep learning algorithms and run the algorithm on the hardware level in a faster way. These new directions start a relatively new paradigm in computational intelligence, which have attracted substantial attention from the research community and demonstrated greater potential over traditional techniques.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"15 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2022-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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