Pub Date : 2026-03-01Epub Date: 2026-01-17DOI: 10.1016/j.compeleceng.2026.110966
Lal Said , Muhammad Amin
Autonomous and remotely operated systems rely on image data for critical decision-making, yet these images are often sent over insecure channels, making them vulnerable to interception or tampering. This paper presents a lightweight image encryption scheme that uses Substitution–Permutation Network architecture with modular arithmetic-based block permutation and dynamically generated chaos-driven substitution boxes. The scheme employs dual key-dependent substitution and exclusive OR operations, ensuring that even a single-bit key change produce a completely different encrypted output. Security analysis shows a large key space, strong resistance to brute force attacks, high entropy, and desirable statistical properties. The proposed method achieves higher throughput than conventional ciphers while preserving salient image content even under pixel loss. These results demonstrate that the scheme provides secure and efficient image protection for resource-constrained environments.
{"title":"Design of lightweight image encryption scheme for saliency protection in autonomous control systems","authors":"Lal Said , Muhammad Amin","doi":"10.1016/j.compeleceng.2026.110966","DOIUrl":"10.1016/j.compeleceng.2026.110966","url":null,"abstract":"<div><div>Autonomous and remotely operated systems rely on image data for critical decision-making, yet these images are often sent over insecure channels, making them vulnerable to interception or tampering. This paper presents a lightweight image encryption scheme that uses Substitution–Permutation Network architecture with modular arithmetic-based block permutation and dynamically generated chaos-driven substitution boxes. The scheme employs dual key-dependent substitution and exclusive OR operations, ensuring that even a single-bit key change produce a completely different encrypted output. Security analysis shows a large key space, strong resistance to brute force attacks, high entropy, and desirable statistical properties. The proposed method achieves higher throughput than conventional ciphers while preserving salient image content even under pixel loss. These results demonstrate that the scheme provides secure and efficient image protection for resource-constrained environments.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110966"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2025-12-26DOI: 10.1016/j.compeleceng.2025.110920
Akash Kumar Deep , G. Lloyds Raja , Gagan Deep Meena
Communication delays severely impair frequency regulation in cyber–physical power systems under false-data-injection attacks by inducing abrupt frequency oscillations that threaten grid stability. Existing mitigation strategies are largely scenario-specific, limiting their scalability and robustness. This paper proposes a robust Direct Synthesis-based Proportional–Integral–Derivative with Filter (DS-PIDF) controller that aligns desired and actual closed-loop dynamics. The single tuning parameter of DS-PIDF controller and the setpoint weighting factor are jointly optimized using a Hybrid Crayfish Optimization Algorithm with Differential Evolution (HCFOADE) to minimize the Integral Time-weighted Absolute Error (ITAE). The proposed approach is validated under communication delay, load perturbations, hybrid cyberattacks, nonlinearities, renewable penetration and hybrid energy storage integration. The HCFOADE-tuned DS-PIDF achieves up to 52.11% and 52.02% faster settling in Areas 1 and 2, respectively, compared to the Proportional–Integral–Double-Derivative (PIDD2) controller, and 8.66–16.30% faster than the Indirect-Internal-Model-Control Proportional–Integral–Derivative (IIMC-PID). Robustness analysis confirms stable operation under ±30% parameter variations.
{"title":"Robust single-parameter frequency controller tuned with Artificial Intelligence-driven hybrid optimization for modern power systems amid cyber threats and latency","authors":"Akash Kumar Deep , G. Lloyds Raja , Gagan Deep Meena","doi":"10.1016/j.compeleceng.2025.110920","DOIUrl":"10.1016/j.compeleceng.2025.110920","url":null,"abstract":"<div><div>Communication delays severely impair frequency regulation in cyber–physical power systems under false-data-injection attacks by inducing abrupt frequency oscillations that threaten grid stability. Existing mitigation strategies are largely scenario-specific, limiting their scalability and robustness. This paper proposes a robust Direct Synthesis-based Proportional–Integral–Derivative with Filter (DS-PIDF) controller that aligns desired and actual closed-loop dynamics. The single tuning parameter of DS-PIDF controller and the setpoint weighting factor are jointly optimized using a Hybrid Crayfish Optimization Algorithm with Differential Evolution (HCFOADE) to minimize the Integral Time-weighted Absolute Error (ITAE). The proposed approach is validated under communication delay, load perturbations, hybrid cyberattacks, nonlinearities, renewable penetration and hybrid energy storage integration. The HCFOADE-tuned DS-PIDF achieves up to 52.11% and 52.02% faster settling in Areas 1 and 2, respectively, compared to the Proportional–Integral–Double-Derivative (PIDD2) controller, and 8.66–16.30% faster than the Indirect-Internal-Model-Control Proportional–Integral–Derivative (IIMC-PID). Robustness analysis confirms stable operation under ±30% parameter variations.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110920"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145842707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-03-01Epub Date: 2025-12-22DOI: 10.1016/j.compeleceng.2025.110917
G.Y. Sree Varshini , S. Latha , G.Y. Rajaa Vikhram , Sanjeevikumar Padmanaban
A modern interconnected power grid known as a cyber-physical power system (CPPS) integrates traditional power systems with information and communication technology. The primary purpose of a CPPS is to enhance the efficiency and security of the power grid via real-time monitoring, control, and data-informed decision-making. To attain its objective of self-healing, the CPPS must autonomously detect faults, respond to them, reorganize, and restore power delivery during disturbances or outages. Therefore, anomaly detection is essential for system recovery. This research examines the effects of physical and cyber disturbances through time-domain and frequency-domain simulations in MATLAB/SIMULINK. Different disturbance scenarios namely physical disturbances, and cyber disturbances such as data integrity attack (DIA), data availability attack (DAA) and coordinated attack are considered and detected using four data-driven methods such as support vector machine (SVM), random forest(RF), K-nearest neighbour(KNN) and convolutional neural network(CNN). The WSCC 3-machine 9-bus system demonstrates the effectiveness of several classifiers for attack detection.
{"title":"Detection of coordinated attack using data driven approach in cyber physical power system (CPPS)","authors":"G.Y. Sree Varshini , S. Latha , G.Y. Rajaa Vikhram , Sanjeevikumar Padmanaban","doi":"10.1016/j.compeleceng.2025.110917","DOIUrl":"10.1016/j.compeleceng.2025.110917","url":null,"abstract":"<div><div>A modern interconnected power grid known as a cyber-physical power system (CPPS) integrates traditional power systems with information and communication technology. The primary purpose of a CPPS is to enhance the efficiency and security of the power grid via real-time monitoring, control, and data-informed decision-making. To attain its objective of self-healing, the CPPS must autonomously detect faults, respond to them, reorganize, and restore power delivery during disturbances or outages. Therefore, anomaly detection is essential for system recovery. This research examines the effects of physical and cyber disturbances through time-domain and frequency-domain simulations in MATLAB/SIMULINK. Different disturbance scenarios namely physical disturbances, and cyber disturbances such as data integrity attack (DIA), data availability attack (DAA) and coordinated attack are considered and detected using four data-driven methods such as support vector machine (SVM), random forest(RF), K-nearest neighbour(KNN) and convolutional neural network(CNN). The WSCC 3-machine 9-bus system demonstrates the effectiveness of several classifiers for attack detection.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110917"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145801921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Depression is a pervasive mental health state that impacts millions worldwide, exemplified by the constant loss of interest, sadness, and several physical and emotional indicators. Even with its widespread occurrence, many individuals fail to receive a timely diagnosis or adequate treatment. Nevertheless, developing an automated scheme capable of detecting depression signs accurately from the text remains a complex task. This article proposes a new approach termed Hierarchical Dense Forward Harmonic Network (H-Dense FHNet) for depression detection in text sentences.
Methodology
The input text sentence is fetched using the selected dataset. Consequently, tokenization is implemented to split the sentence into tokens with the help of Bidirectional Encoder Representations from Transformers (BERT). Further, feature extraction is accomplished, and features like verb vectors, capitalized words, elongated units, count vectors of categories, adjective vectors, length of text, degree adverbs vectors, and punctuation vectors are mined. Ultimately, depression detection is accomplished by the presented H-Dense FHNet, a unified framework of Hierarchical Attention Network (HAN), DenseNet, and harmonic analysis.
Result
The evaluation of the presented H-Dense FHNet shows that it obtained maximal F1-score, recall, and precision of 92.996 %, 93.655 %, and 92.766 % correspondingly.
{"title":"H-Dense FHNet: Hierarchical dense forward harmonic network for depression detection","authors":"Amol Vishwanath Dhumane , Nihar M. Ranjan , Mubin Tamboli , Jayashree Rajesh Prasad , Rajesh Shardanand Prasad","doi":"10.1016/j.compeleceng.2025.110865","DOIUrl":"10.1016/j.compeleceng.2025.110865","url":null,"abstract":"<div><h3>Objective</h3><div>Depression is a pervasive mental health state that impacts millions worldwide, exemplified by the constant loss of interest, sadness, and several physical and emotional indicators. Even with its widespread occurrence, many individuals fail to receive a timely diagnosis or adequate treatment. Nevertheless, developing an automated scheme capable of detecting depression signs accurately from the text remains a complex task. This article proposes a new approach termed Hierarchical Dense Forward Harmonic Network (H-Dense FH<img>Net) for depression detection in text sentences.</div></div><div><h3>Methodology</h3><div>The input text sentence is fetched using the selected dataset. Consequently, tokenization is implemented to split the sentence into tokens with the help of Bidirectional Encoder Representations from Transformers (BERT). Further, feature extraction is accomplished, and features like verb vectors, capitalized words, elongated units, count vectors of categories, adjective vectors, length of text, degree adverbs vectors, and punctuation vectors are mined. Ultimately, depression detection is accomplished by the presented H-Dense FH<img>Net, a unified framework of Hierarchical Attention Network (HAN), DenseNet, and harmonic analysis.</div></div><div><h3>Result</h3><div>The evaluation of the presented H-Dense FH<img>Net shows that it obtained maximal F1-score, recall, and precision of 92.996 %, 93.655 %, and 92.766 % correspondingly.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"130 ","pages":"Article 110865"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145685506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-01DOI: 10.1016/j.compeleceng.2025.110864
Ahmed R. Hasouna, Sabry A. Mahmoud, Awad E. El-Sabbe, Dina S.M. Osheba
This article presents single source Switched Capacitor Multilevel Inverter (SC-MLI) capable of generating 13 voltage levels with either sixfold or threefold voltage gain. The voltage gain is selected based on the adopted switching pattern without any need to change the MLI connections. It utilizes 9 unidirectional switches, one bidirectional switch, three diodes, and three capacitors charged using a charging inductor. Owing to its inherent feature of voltage boosting, the MLI is suitable for low voltage DC sources such as fuel cell and Photovoltaic (PV) applications. The simple phase disposition sinusoidal pulse width modulation (PD-SPWM) strategy is adopted to achieve voltage balance of the utilized capacitors. The topology power losses and efficiency are investigated at different power levels using PSIM. The topology achieves 92.5% efficiency at output power. The simulation is conducted using PLECS and a laboratory prototype is built to validate the simulation results. The proposed inverter performance is assessed under multiple loading conditions, modulation indices, and step-change situations. The proposed topology shows an overall advantage in terms of the cost function and hardware requirements through a comparative study implemented with similar topologies in literature.
{"title":"A 6X–3X voltage gain thirteen level switched capacitor based inverter with reduced switches count for low voltage sources","authors":"Ahmed R. Hasouna, Sabry A. Mahmoud, Awad E. El-Sabbe, Dina S.M. Osheba","doi":"10.1016/j.compeleceng.2025.110864","DOIUrl":"10.1016/j.compeleceng.2025.110864","url":null,"abstract":"<div><div>This article presents single source Switched Capacitor Multilevel Inverter (SC-MLI) capable of generating 13 voltage levels with either sixfold or threefold voltage gain. The voltage gain is selected based on the adopted switching pattern without any need to change the MLI connections. It utilizes 9 unidirectional switches, one bidirectional switch, three diodes, and three capacitors charged using a charging inductor. Owing to its inherent feature of voltage boosting, the MLI is suitable for low voltage DC sources such as fuel cell and Photovoltaic (PV) applications. The simple phase disposition sinusoidal pulse width modulation (PD-SPWM) strategy is adopted to achieve voltage balance of the utilized capacitors. The topology power losses and efficiency are investigated at different power levels using PSIM. The topology achieves 92.5% efficiency at <span><math><mrow><mn>450</mn><mspace></mspace><mi>W</mi></mrow></math></span> output power. The simulation is conducted using PLECS and a laboratory prototype is built to validate the simulation results. The proposed inverter performance is assessed under multiple loading conditions, modulation indices, and step-change situations. The proposed topology shows an overall advantage in terms of the cost function and hardware requirements through a comparative study implemented with similar topologies in literature.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"130 ","pages":"Article 110864"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145685501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-05DOI: 10.1016/j.compeleceng.2025.110886
Saravanakrishnan B., G.R. Jeshnu Skandan, B. Naresh Kumar Reddy
Energy consumption minimization is one of the essential requirements in scheduling tasks in heterogeneous multicore embedded systems in which Dynamic Voltage and Frequency Scaling (DVFS) plays a significant role. Using techniques like DVFS helps to achieve better task scheduling, but the problem of task scheduling becomes an NP-Hard problem. To address these problems, our work proposes a novel approach to assigning frequencies to each task and allocating tasks to various cores in a multicore processor. Our method introduces a less complex yet energy-efficient frequency assignment and task allocation strategy. The Frequency Assignment (FA) algorithm uses the binary search for frequency selection, which reduces the computational complexity to , where is the number of tasks and represents the frequency levels. This guarantees that the frequency is allocated to each task optimally and consumes less energy. For task allocation, we proposed a Task Assignment (TA) algorithm based on Rank and Earliest Finish Time (EFT), which ensures that the tasks are assigned to available processor cores to minimize the overall execution time of the processor. This strategy minimizes energy consumption, distributes the workload evenly, and efficiently uses the available processing power. We compare our solution with other energy-efficient algorithms to evaluate performance in various applications like Gaussian Elimination (GE) and random task graph. Our numerical results demonstrate that the proposed scheduling algorithms perform significantly higher than the existing energy-efficient algorithms in terms of energy savings, task execution efficiency, and reduced computation complexity. The proposed work is implemented in Verilog on the Zynq Ultrascale＋ MPSoC ZCU106 Evaluation Kit FPGA platform, and its performance has been validated.
{"title":"Advanced task scheduling algorithm for enhanced energy efficiency on multi-core embedded platforms","authors":"Saravanakrishnan B., G.R. Jeshnu Skandan, B. Naresh Kumar Reddy","doi":"10.1016/j.compeleceng.2025.110886","DOIUrl":"10.1016/j.compeleceng.2025.110886","url":null,"abstract":"<div><div>Energy consumption minimization is one of the essential requirements in scheduling tasks in heterogeneous multicore embedded systems in which Dynamic Voltage and Frequency Scaling (DVFS) plays a significant role. Using techniques like DVFS helps to achieve better task scheduling, but the problem of task scheduling becomes an NP-Hard problem. To address these problems, our work proposes a novel approach to assigning frequencies to each task and allocating tasks to various cores in a multicore processor. Our method introduces a less complex yet energy-efficient frequency assignment and task allocation strategy. The Frequency Assignment (FA) algorithm uses the binary search for frequency selection, which reduces the computational complexity to <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mi>N</mi><mi>⋅</mi><mo>log</mo><mi>L</mi><mo>)</mo></mrow></mrow></math></span>, where <span><math><mi>N</mi></math></span> is the number of tasks and <span><math><mi>L</mi></math></span> represents the frequency levels. This guarantees that the frequency is allocated to each task optimally and consumes less energy. For task allocation, we proposed a Task Assignment (TA) algorithm based on Rank and Earliest Finish Time (EFT), which ensures that the tasks are assigned to available processor cores to minimize the overall execution time of the processor. This strategy minimizes energy consumption, distributes the workload evenly, and efficiently uses the available processing power. We compare our solution with other energy-efficient algorithms to evaluate performance in various applications like Gaussian Elimination (GE) and random task graph. Our numerical results demonstrate that the proposed scheduling algorithms perform significantly higher than the existing energy-efficient algorithms in terms of energy savings, task execution efficiency, and reduced computation complexity. The proposed work is implemented in Verilog on the Zynq Ultrascale＋ MPSoC ZCU106 Evaluation Kit FPGA platform, and its performance has been validated.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"130 ","pages":"Article 110886"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145685504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-02DOI: 10.1016/j.compeleceng.2025.110884
Shamal Kashid , Lalit K. Awasthi , Krishan Berwal
Video summarization (VS) is the process of condensing lengthy videos into a concise and informative summary, thus improving the accessibility of the content and user experience. This paper presents a novel static video summarization approach that leverages deep feature extraction using a dual-convolutional neural network (Dual-CNN) architecture. The proposed method extracts frame-level features from benchmark datasets, incorporating user-annotated summaries as ground truth. To further enhance summarization performance, we integrate Self-Organizing Map (SOM) clustering into the Dual-CNN pipeline, facilitating effective identification and selection of representative keyframes and resulting in the SOM-based video summarization (SOMVS) framework. Experimental results in four publicly available datasets, SumMe, TVSum, Open Video Project and YouTube, demonstrate that SOMVS consistently outperforms existing methods, achieving average F measures of 52.7%, 60.9%, 80.9% and 82.8%, respectively. These results highlight effectiveness of the proposed approach across diverse video content.
视频摘要（Video summarization， VS）是将冗长的视频压缩成简洁、信息丰富的摘要，从而提高内容的可访问性和用户体验的过程。本文提出了一种新的静态视频摘要方法，该方法利用双卷积神经网络（Dual-CNN）架构进行深度特征提取。该方法从基准数据集中提取帧级特征，并将用户注释摘要作为基础事实。为了进一步提高摘要性能，我们将自组织映射（SOM）聚类集成到Dual-CNN管道中，促进了代表性关键帧的有效识别和选择，并产生了基于SOM的视频摘要（SOMVS）框架。在SumMe、TVSum、Open Video Project和YouTube四个公开数据集上的实验结果表明，SOMVS始终优于现有方法，平均F值分别达到52.7%、60.9%、80.9%和82.8%。这些结果突出了所提出的方法在不同视频内容中的有效性。
{"title":"SOMVS: A dual-convolutional neural network and self-organizing map-based approach for high-quality video summarization","authors":"Shamal Kashid , Lalit K. Awasthi , Krishan Berwal","doi":"10.1016/j.compeleceng.2025.110884","DOIUrl":"10.1016/j.compeleceng.2025.110884","url":null,"abstract":"<div><div>Video summarization (VS) is the process of condensing lengthy videos into a concise and informative summary, thus improving the accessibility of the content and user experience. This paper presents a novel static video summarization approach that leverages deep feature extraction using a dual-convolutional neural network (Dual-CNN) architecture. The proposed method extracts frame-level features from benchmark datasets, incorporating user-annotated summaries as ground truth. To further enhance summarization performance, we integrate Self-Organizing Map (SOM) clustering into the Dual-CNN pipeline, facilitating effective identification and selection of representative keyframes and resulting in the SOM-based video summarization (SOMVS) framework. Experimental results in four publicly available datasets, SumMe, TVSum, Open Video Project and YouTube, demonstrate that SOMVS consistently outperforms existing methods, achieving average F measures of 52.7%, 60.9%, 80.9% and 82.8%, respectively. These results highlight effectiveness of the proposed approach across diverse video content.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"130 ","pages":"Article 110884"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-08DOI: 10.1016/j.compeleceng.2025.110898
Mohsin Shah , Muhammad Nawaz Khan , Sokjoon Lee , Byoung Koo Kim , Inam Ullah
Reversible data hiding (RDH) is a prominent information hiding method that enables the lossless embedding of additional data within digital multimedia cover files. RDH guarantees perfect reversibility, enabling the receiver to reconstruct the original cover media following data extraction. RDH in 3D meshes has gained increasing attention due to its widespread applications. A critical challenge in RDH for 3D meshes is to accurately predict vertex positions to minimize distortion during data embedding using prediction error expansion (PEE). In this paper, we propose a novel multilayer perceptron based predictor (MLPP) by dividing the vertices of a 3D mesh model into two sets and using one set (reference set) to predict the other set (embedding set) for data embedding. The 1-ring neighbor vertices of the reference set are arranged into a fixed dimension feature vector to train a lightweight and computationally efficient multilayer perceptron network. The proposed network learns from the local geometric structure of 3D meshes to predict embedding vertices and produces sharp prediction errors histogram centered at zero. Furthermore, the small prediction errors are expanded for data embedding, leading to higher capacity and lower distortion. Experimental results demonstrate that the proposed MLPP attains better performance in terms of prediction accuracy, embedding capacity and embedding distortion.
{"title":"Learning based vertex prediction for high capacity reversible data hiding in 3D meshes","authors":"Mohsin Shah , Muhammad Nawaz Khan , Sokjoon Lee , Byoung Koo Kim , Inam Ullah","doi":"10.1016/j.compeleceng.2025.110898","DOIUrl":"10.1016/j.compeleceng.2025.110898","url":null,"abstract":"<div><div>Reversible data hiding (RDH) is a prominent information hiding method that enables the lossless embedding of additional data within digital multimedia cover files. RDH guarantees perfect reversibility, enabling the receiver to reconstruct the original cover media following data extraction. RDH in 3D meshes has gained increasing attention due to its widespread applications. A critical challenge in RDH for 3D meshes is to accurately predict vertex positions to minimize distortion during data embedding using prediction error expansion (PEE). In this paper, we propose a novel multilayer perceptron based predictor (MLPP) by dividing the vertices of a 3D mesh model into two sets and using one set (reference set) to predict the other set (embedding set) for data embedding. The 1-ring neighbor vertices of the reference set are arranged into a fixed dimension feature vector to train a lightweight and computationally efficient multilayer perceptron network. The proposed network learns from the local geometric structure of 3D meshes to predict embedding vertices and produces sharp prediction errors histogram centered at zero. Furthermore, the small prediction errors are expanded for data embedding, leading to higher capacity and lower distortion. Experimental results demonstrate that the proposed MLPP attains better performance in terms of prediction accuracy, embedding capacity and embedding distortion.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"130 ","pages":"Article 110898"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-10DOI: 10.1016/j.compeleceng.2025.110901
Furqan Zahoor
Hardware-based security primitives like True Random Number Generators (TRNG) have become a crucial part in protecting data over communication channels. Compact and reliable ON-chip TRNGs are inevitable for generating secure cryptographic keys in resource constrained mobile Internet-of-Things (IoT) devices. On the other hand, the inherently dense structure and low power characteristics of emerging nanoelectronic technologies such as resistive random access memory (RRAM) make them suitable elements in designing hardware security modules integrated in CMOS ICs. Further research focuses on mitigating the negative consequences of RRAM integrations primarily for in-memory computing applications, which include oscillations in switching resistances, sneak path current, and random telegraph noise (RTN). However, these characteristics make them a suitable choice for design of hardware security primitives such as TRNGs. This paper provides a brief background on the basics of TRNG, and then presents in detail the functionality, and methodologies proposed for implementing TRNGs based on RRAM and also provides a comparative analysis of the state-of-the-art RRAM based TRNG designs. Finally, general challenges for design of TRNGs based on RRAM and the discussion on future outlook is also discussed.
{"title":"A comprehensive study on resistive random access memory based true random number generators","authors":"Furqan Zahoor","doi":"10.1016/j.compeleceng.2025.110901","DOIUrl":"10.1016/j.compeleceng.2025.110901","url":null,"abstract":"<div><div>Hardware-based security primitives like True Random Number Generators (TRNG) have become a crucial part in protecting data over communication channels. Compact and reliable ON-chip TRNGs are inevitable for generating secure cryptographic keys in resource constrained mobile Internet-of-Things (IoT) devices. On the other hand, the inherently dense structure and low power characteristics of emerging nanoelectronic technologies such as resistive random access memory (RRAM) make them suitable elements in designing hardware security modules integrated in CMOS ICs. Further research focuses on mitigating the negative consequences of RRAM integrations primarily for in-memory computing applications, which include oscillations in switching resistances, sneak path current, and random telegraph noise (RTN). However, these characteristics make them a suitable choice for design of hardware security primitives such as TRNGs. This paper provides a brief background on the basics of TRNG, and then presents in detail the functionality, and methodologies proposed for implementing TRNGs based on RRAM and also provides a comparative analysis of the state-of-the-art RRAM based TRNG designs. Finally, general challenges for design of TRNGs based on RRAM and the discussion on future outlook is also discussed.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"130 ","pages":"Article 110901"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
These days, gastrointestinal disorders are a major health concern, and serious consequences can be avoided with early detection. An effective tool for the examiner to make an accurate diagnosis of the disease is a computer-aided diagnosis (CAD) system. However, the developed artificial intelligence (AI) algorithm determines the power consumption and latency of the CAD system. The AI algorithm needs to be optimized for edge devices for real-time implementation. In the proposed LDFGastro-Net, we have developed a lightweight hybrid convolutional neural network (CNN) model for the classification of gastrointestinal disorders. The initial layer is derived from the MobileNet-V2 pre-trained model for the extraction of low-level features, as the proposed model is intended for Field Programmable Gate Array (FPGA) deployment and must be lightweight. Next, a dense structure of depth-wise separable layers forms the middle section of the proposed framework. The dense connection has the advantage of feature reuse with the extraction of essential spatial features along with low-level features. The depthwise separable and feature fusion, which help in class-specific features and preservation of low level features, are included in the final layers. The proposed model’s performance has been demonstrated through Grad-CAM visualizations, highlighting its ability to classify gastrointestinal disorders better. With an accuracy of 98.2%, the proposed model outperforms the existing custom CNN model and several state-of-the-art pretrained architectures.
{"title":"LDFGastro-Net: Lite-DenseFuse Network for gastrointestinal disorders classification towards hardware deployment","authors":"Debaraj Rana , Bunil Kumar Balabantaray , Rajashree Nayak , Rangababu Peesapati","doi":"10.1016/j.compeleceng.2025.110852","DOIUrl":"10.1016/j.compeleceng.2025.110852","url":null,"abstract":"<div><div>These days, gastrointestinal disorders are a major health concern, and serious consequences can be avoided with early detection. An effective tool for the examiner to make an accurate diagnosis of the disease is a computer-aided diagnosis (CAD) system. However, the developed artificial intelligence (AI) algorithm determines the power consumption and latency of the CAD system. The AI algorithm needs to be optimized for edge devices for real-time implementation. In the proposed LDFGastro-Net, we have developed a lightweight hybrid convolutional neural network (CNN) model for the classification of gastrointestinal disorders. The initial layer is derived from the MobileNet-V2 pre-trained model for the extraction of low-level features, as the proposed model is intended for Field Programmable Gate Array (FPGA) deployment and must be lightweight. Next, a dense structure of depth-wise separable layers forms the middle section of the proposed framework. The dense connection has the advantage of feature reuse with the extraction of essential spatial features along with low-level features. The depthwise separable and feature fusion, which help in class-specific features and preservation of low level features, are included in the final layers. The proposed model’s performance has been demonstrated through Grad-CAM visualizations, highlighting its ability to classify gastrointestinal disorders better. With an accuracy of 98.2%, the proposed model outperforms the existing custom CNN model and several state-of-the-art pretrained architectures.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"130 ","pages":"Article 110852"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145572090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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