Ivan Hotový, Johann Zehetner, V. Rehacek, Miroslav Mikolasek, Ivan Kostic, S. Serečunová, Dana Seyringer, Fadi Dohnal
This study presents different approaches to increase the sensing area of NiO based semiconducting metal oxide gas sensors. Micro- and nanopatterned laser induced periodic surface structures (LIPSS) are generated on silicon and Si/SiO2 substrates. The surface morphologies of the fabricated samples are examined by FE SEM. We select the silicon samples with an intermediate Si3N4 layer due to its superior isolation quality over the thermal oxide for evaluating the hydrogen and acetone sensitivity of a NiO based test sensor.
本研究介绍了增加基于氧化镍的半导体金属氧化物气体传感器传感面积的不同方法。在硅和硅/二氧化硅基底上生成了微图案和纳米图案的激光诱导周期性表面结构 (LIPSS)。利用 FE SEM 扫描电子显微镜检查了制作样品的表面形态。我们选择了带有中间 Si3N4 层的硅样品，因为它的隔离质量优于热氧化物，可用于评估基于氧化镍的测试传感器的氢气和丙酮灵敏度。
{"title":"Preparation of laser induced periodic surface structures for gas sensing thin films and gas sensing verification of a NiO based sensor structure","authors":"Ivan Hotový, Johann Zehetner, V. Rehacek, Miroslav Mikolasek, Ivan Kostic, S. Serečunová, Dana Seyringer, Fadi Dohnal","doi":"10.2478/jee-2024-0004","DOIUrl":"https://doi.org/10.2478/jee-2024-0004","url":null,"abstract":"\u0000 This study presents different approaches to increase the sensing area of NiO based semiconducting metal oxide gas sensors. Micro- and nanopatterned laser induced periodic surface structures (LIPSS) are generated on silicon and Si/SiO2 substrates. The surface morphologies of the fabricated samples are examined by FE SEM. We select the silicon samples with an intermediate Si3N4 layer due to its superior isolation quality over the thermal oxide for evaluating the hydrogen and acetone sensitivity of a NiO based test sensor.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"257 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139823641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. M. Giang, Le Ho Manh Thang, Le Dang Manh, Tran Thi Thu Huong
In this paper, a novel design method for quad-band Wilkinson power dividers is proposed. The design method is based on using a quad-band microstrip line. In comparison with other design methods, the proposed method has the advantages of simplicity and low insertion loss. To validate the proposed method, an equal quad-band power divider operating at four bands of 0.7, 1.2, 1.78, and 2.28 GHz was simulated and measured. Good agreement between measured results and simulated ones is obtained. The measured results show that the developed quad-band power divider features low insertion loss of less than 0.75 dB, isolation greater than 20.92 dB, and return loss better than 18 dB at four operating bands.
{"title":"A simple design of low-loss quad-band Wilkinson power dividers","authors":"N. M. Giang, Le Ho Manh Thang, Le Dang Manh, Tran Thi Thu Huong","doi":"10.2478/jee-2024-0009","DOIUrl":"https://doi.org/10.2478/jee-2024-0009","url":null,"abstract":"\u0000 In this paper, a novel design method for quad-band Wilkinson power dividers is proposed. The design method is based on using a quad-band microstrip line. In comparison with other design methods, the proposed method has the advantages of simplicity and low insertion loss. To validate the proposed method, an equal quad-band power divider operating at four bands of 0.7, 1.2, 1.78, and 2.28 GHz was simulated and measured. Good agreement between measured results and simulated ones is obtained. The measured results show that the developed quad-band power divider features low insertion loss of less than 0.75 dB, isolation greater than 20.92 dB, and return loss better than 18 dB at four operating bands.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"342 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139824170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Human activity recognition (HAR) by deep learning is a challenging and interesting topic. Although there are robust models, there is also a bunch of parameters and variables, which affect the performance such as the number of layers, pooling type. This study presents a new deep learning architecture that is obtained by fine-tuning of the conventional CNN-LSTM model, namely, CNN (+3)-LSTM. Three changes are made to the conventional model to increase the accuracy. Firstly, kernel size is set to 1×1 to extract more information. Secondly, three convolutional layers are added to the model. Lastly, average pooling is used instead of max-pooling. Performance analysis of the proposed model is conducted on the KTH dataset and implemented on Keras. In addition to the overall accuracy of the proposed model, the contribution of each change is observed individually. Results show that adding layers made the highest contribution followed by kernel size and pooling, respectively. The proposed model is compared with state-of-art and outperformed some of the recent studies with a 94.1% recognition rate.
{"title":"Human activity recognition with fine-tuned CNN-LSTM","authors":"Erdal Genc, M. E. Yıldırım, Y. B. Salman","doi":"10.2478/jee-2024-0002","DOIUrl":"https://doi.org/10.2478/jee-2024-0002","url":null,"abstract":"\u0000 Human activity recognition (HAR) by deep learning is a challenging and interesting topic. Although there are robust models, there is also a bunch of parameters and variables, which affect the performance such as the number of layers, pooling type. This study presents a new deep learning architecture that is obtained by fine-tuning of the conventional CNN-LSTM model, namely, CNN (+3)-LSTM. Three changes are made to the conventional model to increase the accuracy. Firstly, kernel size is set to 1×1 to extract more information. Secondly, three convolutional layers are added to the model. Lastly, average pooling is used instead of max-pooling. Performance analysis of the proposed model is conducted on the KTH dataset and implemented on Keras. In addition to the overall accuracy of the proposed model, the contribution of each change is observed individually. Results show that adding layers made the highest contribution followed by kernel size and pooling, respectively. The proposed model is compared with state-of-art and outperformed some of the recent studies with a 94.1% recognition rate.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"210 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139828338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. M. Giang, Le Ho Manh Thang, Le Dang Manh, Tran Thi Thu Huong
In this paper, a novel design method for quad-band Wilkinson power dividers is proposed. The design method is based on using a quad-band microstrip line. In comparison with other design methods, the proposed method has the advantages of simplicity and low insertion loss. To validate the proposed method, an equal quad-band power divider operating at four bands of 0.7, 1.2, 1.78, and 2.28 GHz was simulated and measured. Good agreement between measured results and simulated ones is obtained. The measured results show that the developed quad-band power divider features low insertion loss of less than 0.75 dB, isolation greater than 20.92 dB, and return loss better than 18 dB at four operating bands.
{"title":"A simple design of low-loss quad-band Wilkinson power dividers","authors":"N. M. Giang, Le Ho Manh Thang, Le Dang Manh, Tran Thi Thu Huong","doi":"10.2478/jee-2024-0009","DOIUrl":"https://doi.org/10.2478/jee-2024-0009","url":null,"abstract":"\u0000 In this paper, a novel design method for quad-band Wilkinson power dividers is proposed. The design method is based on using a quad-band microstrip line. In comparison with other design methods, the proposed method has the advantages of simplicity and low insertion loss. To validate the proposed method, an equal quad-band power divider operating at four bands of 0.7, 1.2, 1.78, and 2.28 GHz was simulated and measured. Good agreement between measured results and simulated ones is obtained. The measured results show that the developed quad-band power divider features low insertion loss of less than 0.75 dB, isolation greater than 20.92 dB, and return loss better than 18 dB at four operating bands.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"21 4","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139883928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Bhardwaj, Ravuri Narayana, Dheeraj Kalra, Mayank Srivastava
The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.
{"title":"Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension","authors":"K. Bhardwaj, Ravuri Narayana, Dheeraj Kalra, Mayank Srivastava","doi":"10.2478/jee-2024-0001","DOIUrl":"https://doi.org/10.2478/jee-2024-0001","url":null,"abstract":"\u0000 The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"262 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139820331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The primary application of codes with locality and availability in distributed storage is for data recovery in case that data are lost on some damaged servers. Locality enables the recovery of lost data by contacting only a restricted number of remaining servers. Availability means that more than one subset of servers providing locality is available for data recovery for each server. The secondary application of these codes in distributed storage is to allow access to hot data in times of high demand. In this paper it is shown that the binary linear [14, 4, 7] code has locality 2 and availability 6 and it can be interpreted as a three-dimensional graph obtained from a [7, 3, 4] Simplex code. It is achieving upper bounds on basic parameters for codes with all-symbols locality and availability. This code can be a building element of more complex codes with scalability inspired by three-dimensional structures. The availability spectrum is introduced as a tool for analyzing codes with locality and availability.
{"title":"Linear block code with locality and availability inspired by tetrahedron","authors":"Peter Farkaš","doi":"10.2478/jee-2024-0010","DOIUrl":"https://doi.org/10.2478/jee-2024-0010","url":null,"abstract":"\u0000 The primary application of codes with locality and availability in distributed storage is for data recovery in case that data are lost on some damaged servers. Locality enables the recovery of lost data by contacting only a restricted number of remaining servers. Availability means that more than one subset of servers providing locality is available for data recovery for each server. The secondary application of these codes in distributed storage is to allow access to hot data in times of high demand. In this paper it is shown that the binary linear [14, 4, 7] code has locality 2 and availability 6 and it can be interpreted as a three-dimensional graph obtained from a [7, 3, 4] Simplex code. It is achieving upper bounds on basic parameters for codes with all-symbols locality and availability. This code can be a building element of more complex codes with scalability inspired by three-dimensional structures. The availability spectrum is introduced as a tool for analyzing codes with locality and availability.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"352 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139830875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The all-optical switching phenomena in the non-linear directional coupler using cross-phase modulation (XPM) effect have been proposed. It is designed to generate an all-optical XOR functionality, considering the XOR logic gates as a basic module the design and analysis of an efficient all-optical 4-bit binary to gray code converter and 4-bit even parity checker circuit is proposed. The design methodology includes the switching of a weak continuous-wave (CW) signal, which is controlled by the combination of two controlled pump signals. In this paper, mathematical analysis of the coupled mode theory associated with optical directional couplers has been discussed. The switching characteristics of XPM effect based All-optical directional couplers have been examined for appropriate values of the controlled pump signals. Appropriate values of extinction ratio and corresponding controlled pump signal levels are investigated for an efficient generation of XOR logic gates. Further, the detailed analysis of layout generation and design aspects of All-optical 4-bit binary to gray code converter and 4-bit even parity checker circuits have been carried out. The proposed methodology is verified by the appropriate simulation results, which include the transmittivity, extinction ratio (Xratio) curve variation and dynamic time domain plot associated with proposed units.
{"title":"Harnessing XPM effects in non-linear directional couplers for 4-bit gray code conversion and even parity verification","authors":"Ajay Yadav, Ajay Kumar, Amit Prakash","doi":"10.2478/jee-2024-0003","DOIUrl":"https://doi.org/10.2478/jee-2024-0003","url":null,"abstract":"\u0000 The all-optical switching phenomena in the non-linear directional coupler using cross-phase modulation (XPM) effect have been proposed. It is designed to generate an all-optical XOR functionality, considering the XOR logic gates as a basic module the design and analysis of an efficient all-optical 4-bit binary to gray code converter and 4-bit even parity checker circuit is proposed. The design methodology includes the switching of a weak continuous-wave (CW) signal, which is controlled by the combination of two controlled pump signals. In this paper, mathematical analysis of the coupled mode theory associated with optical directional couplers has been discussed. The switching characteristics of XPM effect based All-optical directional couplers have been examined for appropriate values of the controlled pump signals. Appropriate values of extinction ratio and corresponding controlled pump signal levels are investigated for an efficient generation of XOR logic gates. Further, the detailed analysis of layout generation and design aspects of All-optical 4-bit binary to gray code converter and 4-bit even parity checker circuits have been carried out. The proposed methodology is verified by the appropriate simulation results, which include the transmittivity, extinction ratio (Xratio) curve variation and dynamic time domain plot associated with proposed units.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"343 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139831828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Home battery has become more and more popular in which the AC battery is a trending product along with the AC-coupled system. The energy conversion of an AC battery commonly consists of a two-stage power converter to flexibly connect to the wide-range input battery voltage and different grid or load types. This study specifically concentrates on the DC/DC stage which plays an important role in transferring power with the battery. In addressing the need for isolation, bidirectional power flow, and limited battery current ripple, the Current-fed Dual Active Bridge (CFDAB) structure is chosen for this stage. This paper presents a comprehensive design for the CFDAB converter for an AC battery application, especially a technical solution focusing on zero voltage switching is applied to increase the efficiency of the converter. Finally, an experimental prototype is carried out to validate the performance of the CFDAB converter in both two modes of the power flow.
{"title":"Design and implementation of a current-fed dual active bridge converter for an AC battery","authors":"Tuan Anh Do, Quang Dich Nguyen, Phuong Vu","doi":"10.2478/jee-2024-0007","DOIUrl":"https://doi.org/10.2478/jee-2024-0007","url":null,"abstract":"\u0000 Home battery has become more and more popular in which the AC battery is a trending product along with the AC-coupled system. The energy conversion of an AC battery commonly consists of a two-stage power converter to flexibly connect to the wide-range input battery voltage and different grid or load types. This study specifically concentrates on the DC/DC stage which plays an important role in transferring power with the battery. In addressing the need for isolation, bidirectional power flow, and limited battery current ripple, the Current-fed Dual Active Bridge (CFDAB) structure is chosen for this stage. This paper presents a comprehensive design for the CFDAB converter for an AC battery application, especially a technical solution focusing on zero voltage switching is applied to increase the efficiency of the converter. Finally, an experimental prototype is carried out to validate the performance of the CFDAB converter in both two modes of the power flow.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"31 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139877995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ambuli B. R. Etemesi, T. Megahed, Haruichi Kanaya, D. Mansour
Existing distribution networks were not designed with large-scale electric vehicle (EV) charging infrastructure in mind. Integrating EV charging stations with the distribution grid might lead to power quality (PQ) issues at the point of common coupling (PCC). This work proposes a two-mode, unit template-based synchronous reference frame hysteresis current-controlled (SRF-HCC) three-phase Level 2 EV charger. Mode one focuses on charging the EV battery from the grid (G2V) and utilizes current and voltage control techniques to enhance battery life and performance. Whereas mode two enables the EV’s stored energy to be discharged to the grid (V2G) by the EV user, allowing the sale of power to support the transient effect of the grid voltage and frequency and enhancing the grid’s PQ. The HCC generates switching pulses for both the AC-DC and buck-boost converters. The SRF-based unit template-based control (SRF-UTC) method ensures system stability, voltage, and frequency regulation for power exchange with the grid by combining its efficiency with that of the HCC. The EV charger proposal comprises three primary components: a 3-phase bidirectional AC-DC converter, a bidirectional buck-boost converter, and a filter circuit. The proposed system was modeled using MATLAB/Simulink and evaluated in two case studies to assess its performance.
{"title":"Design of a bidirectional EV charger using unit template-based current-controlled synchronous reference frame hysteresis","authors":"Ambuli B. R. Etemesi, T. Megahed, Haruichi Kanaya, D. Mansour","doi":"10.2478/jee-2024-0005","DOIUrl":"https://doi.org/10.2478/jee-2024-0005","url":null,"abstract":"\u0000 Existing distribution networks were not designed with large-scale electric vehicle (EV) charging infrastructure in mind. Integrating EV charging stations with the distribution grid might lead to power quality (PQ) issues at the point of common coupling (PCC). This work proposes a two-mode, unit template-based synchronous reference frame hysteresis current-controlled (SRF-HCC) three-phase Level 2 EV charger. Mode one focuses on charging the EV battery from the grid (G2V) and utilizes current and voltage control techniques to enhance battery life and performance. Whereas mode two enables the EV’s stored energy to be discharged to the grid (V2G) by the EV user, allowing the sale of power to support the transient effect of the grid voltage and frequency and enhancing the grid’s PQ. The HCC generates switching pulses for both the AC-DC and buck-boost converters. The SRF-based unit template-based control (SRF-UTC) method ensures system stability, voltage, and frequency regulation for power exchange with the grid by combining its efficiency with that of the HCC. The EV charger proposal comprises three primary components: a 3-phase bidirectional AC-DC converter, a bidirectional buck-boost converter, and a filter circuit. The proposed system was modeled using MATLAB/Simulink and evaluated in two case studies to assess its performance.","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"30 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139882120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article proposes an adaptive Kernel-Hebbian least mean square (KHLMS) controller for a dual voltage source inverter (VSI). The recommended topology consists of a distributed energy resource (DER) supported VSI called main VSI (MVSI) and split capacitor supported VSI termed as auxiliary VSI (AVSI). Both the MVSI and AVSI are used to serve the shunt compensation when DER is not integrated with MVSI. The DER scenario is considered to suppress the active power flow shortage in the utility grid. Here, optimal active power flow control (OAPFC) is managed by MVSI and shunt compensation is achieved by AVSI during DER operated mode. Hence, a dual VSI based distribution static compensator (DSTATCOM) facilitates the configuration merits such as reduction in system downtime cost, filter rating switching stress etc. Supremacy of both the neural network (NN) based controller and topology is presented by comparing VSI (called AVSI) in the context of harmonic reduction in source side, voltage balancing, power factor (PF) enhancement, better voltage regulation and OAPFC. The experimental results are obtained through field programmable gate array (FPGA) based hardware units which exhibit radical improvement in the power quality (PQ) conferring as per the international standard grid code (IEEE-519-2017).
本文为双电压源逆变器（VSI）提出了一种自适应核-赫比最小均方（KHLMS）控制器。推荐的拓扑结构包括一个由分布式能源资源（DER）支持的 VSI，称为主 VSI（MVSI），以及由分路电容器支持的 VSI，称为辅助 VSI（AVSI）。当 DER 未与 MVSI 集成时，MVSI 和 AVSI 均用于并联补偿。DER 方案用于抑制公用电网的有功功率流短缺。在此，有功功率流控制（OAPFC）由 MVSI 管理，而并联补偿则由 AVSI 在 DER 运行模式下实现。因此，基于双 VSI 的配电静态补偿器（DSTATCOM）具有配置便利的优点，如降低系统停机成本、滤波器额定开关压力等。通过比较 VSI（称为 AVSI）在减少源侧谐波、电压平衡、提高功率因数 (PF)、改善电压调节和 OAPFC 方面的优势，介绍了基于神经网络 (NN) 的控制器和拓扑结构的优越性。实验结果是通过基于现场可编程门阵列（FPGA）的硬件单元获得的，这些单元按照国际标准电网规范（IEEE-519-2017）对电能质量（PQ）进行了彻底改善。
{"title":"Experimental test performance for a comparative evaluation of a voltage source inverter: Dual voltage source inverter","authors":"M. Mangaraj, Jogeswara Sabat, Ajit Kumar Barisal","doi":"10.2478/jee-2024-0008","DOIUrl":"https://doi.org/10.2478/jee-2024-0008","url":null,"abstract":"\u0000 This article proposes an adaptive Kernel-Hebbian least mean square (KHLMS) controller for a dual voltage source inverter (VSI). The recommended topology consists of a distributed energy resource (DER) supported VSI called main VSI (MVSI) and split capacitor supported VSI termed as auxiliary VSI (AVSI). Both the MVSI and AVSI are used to serve the shunt compensation when DER is not integrated with MVSI. The DER scenario is considered to suppress the active power flow shortage in the utility grid. Here, optimal active power flow control (OAPFC) is managed by MVSI and shunt compensation is achieved by AVSI during DER operated mode. Hence, a dual VSI based distribution static compensator (DSTATCOM) facilitates the configuration merits such as reduction in system downtime cost, filter rating switching stress etc. Supremacy of both the neural network (NN) based controller and topology is presented by comparing VSI (called AVSI) in the context of harmonic reduction in source side, voltage balancing, power factor (PF) enhancement, better voltage regulation and OAPFC. The experimental results are obtained through field programmable gate array (FPGA) based hardware units which exhibit radical improvement in the power quality (PQ) conferring as per the international standard grid code (IEEE-519-2017).","PeriodicalId":508697,"journal":{"name":"Journal of Electrical Engineering","volume":"7 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139882335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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