L. Deng, Bryan R. Winter, J. H. Shiau, Henry Horng-Shing Lu, Nirman Kumar, Ching-Chi Yang
{"title":"Parallelizable efficient large order multiple recursive generators","authors":"L. Deng, Bryan R. Winter, J. H. Shiau, Henry Horng-Shing Lu, Nirman Kumar, Ching-Chi Yang","doi":"10.2139/ssrn.4344139","DOIUrl":"https://doi.org/10.2139/ssrn.4344139","url":null,"abstract":"","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"78 1","pages":"103036"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73726981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01DOI: 10.1016/j.parco.2023.103042
Ignacio Laguna , Anh Tran , Ganesh Gopalakrishnan
Testing code for floating-point exceptions is crucial as exceptions can quickly propagate and produce unreliable numerical answers. The state-of-the-art to test for floating-point exceptions in heterogeneous systems is quite limited and solutions require the application’s source code, which precludes their use in accelerated libraries where the source is not publicly available. We present an approach to find inputs that trigger floating-point exceptions in black-box CPU or GPU functions, i.e., functions where the source code and information about input bounds are unavailable. Our approach is the first to use Bayesian optimization (BO) to identify such inputs and uses novel strategies to overcome the challenges that arise in applying BO to this problem. We implement our approach in the Xscope framework and demonstrate it on 58 functions from the CUDA Math Library and 81 functions from the Intel Math Library. Xscope is able to identify inputs that trigger exceptions in about 73% of the tested functions.
{"title":"Finding inputs that trigger floating-point exceptions in heterogeneous computing via Bayesian optimization","authors":"Ignacio Laguna , Anh Tran , Ganesh Gopalakrishnan","doi":"10.1016/j.parco.2023.103042","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103042","url":null,"abstract":"<div><p><span><span>Testing code for floating-point exceptions is crucial as exceptions can quickly propagate and produce unreliable numerical answers. The state-of-the-art to test for floating-point exceptions in heterogeneous systems<span> is quite limited and solutions require the application’s source code, which precludes their use in accelerated libraries where the source is not publicly available. We present an approach to find inputs that trigger floating-point exceptions in black-box CPU or </span></span>GPU functions, i.e., functions where the source code and information about input bounds are unavailable. Our approach is the first to use Bayesian optimization (BO) to identify such inputs and uses novel strategies to overcome the challenges that arise in applying BO to this problem. We implement our approach in the </span><span><span>Xscope</span></span> framework and demonstrate it on 58 functions from the CUDA Math Library and 81 functions from the Intel Math Library. <span><span>Xscope</span></span> is able to identify inputs that trigger exceptions in about 73% of the tested functions.</p></div>","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103042"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01DOI: 10.1016/j.parco.2023.103036
Lih-Yuan Deng , Bryan R. Winter , Jyh-Jen Horng Shiau , Henry Horng-Shing Lu , Nirman Kumar , Ching-Chi Yang
The general multiple recursive generator (MRG) of maximum period has been thought of as an excellent source of pseudo random numbers. Based on a th order linear recurrence modulo , this generator produces the next pseudo random number based on a linear combination of the previous numbers. General maximum period MRGs of order have excellent empirical performance, and their strong mathematical foundations have been studied extensively.
For computing efficiency, it is common to consider special MRGs with some simple structure with few non-zero terms which requires fewer costly multiplications. However, such MRGs will not have a good “spectral test” property when compared with general MRGs with many non-zero terms. On the other hand, there are two potential problems of using general MRGs with many non-zero terms: (1) its efficient implementation (2) its efficient scheme for its parallelization. Efficient implementation of general MRGs of larger order can be difficult because the th order linear recurrence requires many costly multiplications to produce the next number. For its parallelization scheme, for a large , the traditional scheme like “jump-ahead parallelization method” for general MRGs becomes highly computationally inefficient. We proposed implementing maximum period MRGs with many nonzero terms efficiently and in parallel by using a MCG constructed from the MRG. In particular, we propose a special class of large order MRGs with many nonzero terms that also have an efficient and parallel implementation.
{"title":"Parallelizable efficient large order multiple recursive generators","authors":"Lih-Yuan Deng , Bryan R. Winter , Jyh-Jen Horng Shiau , Henry Horng-Shing Lu , Nirman Kumar , Ching-Chi Yang","doi":"10.1016/j.parco.2023.103036","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103036","url":null,"abstract":"<div><p>The general multiple recursive generator (MRG) of maximum period has been thought of as an excellent source of pseudo random numbers. Based on a <span><math><mi>k</mi></math></span>th order linear recurrence modulo <span><math><mi>p</mi></math></span><span>, this generator produces the next pseudo random number based on a linear combination of the previous </span><span><math><mi>k</mi></math></span> numbers. General maximum period MRGs of order <span><math><mi>k</mi></math></span> have excellent empirical performance, and their strong mathematical foundations have been studied extensively.</p><p><span>For computing efficiency, it is common to consider special MRGs with some simple structure with few non-zero terms which requires fewer costly multiplications. However, such MRGs will not have a good “spectral test” property when compared with general MRGs with many non-zero terms. On the other hand, there are two potential problems of using general MRGs with many non-zero terms: (1) its efficient implementation (2) its efficient scheme for its parallelization. Efficient implementation of general MRGs of larger order </span><span><math><mi>k</mi></math></span> can be difficult because the <span><math><mi>k</mi></math></span>th order linear recurrence requires many costly multiplications to produce the next number. For its parallelization scheme, for a large <span><math><mi>k</mi></math></span>, the traditional scheme like “jump-ahead parallelization method” for general MRGs becomes highly computationally inefficient. We proposed implementing maximum period MRGs with many nonzero terms efficiently and in parallel by using a MCG constructed from the MRG. In particular, we propose a special class of large order MRGs with many nonzero terms that also have an efficient and parallel implementation.</p></div>","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103036"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01DOI: 10.1016/j.parco.2023.103041
Ou Wu , Shanshan Li , He Zhang , Liwen Liu , Haoming Li , Yanze Wang , Ziyi Zhang
As the most popular consortium blockchain platform, Hyperledger Fabric (Fabric for short) has released multiple versions that support different consensus protocols to address the risks faced in current and future network transactions. For example, Fabric v1.4 and v2.0 use Kafka and Raft mechanisms to complete consensus and ensure that the system can withstand failures such as crashes, network partitions, or network shutdowns. In a multi-channel Fabric network architecture, the system structure cannot guarantee the behavior of malicious nodes. Complex cooperation between peer groups on different channels can greatly affect the security and efficiency of the entire network architecture, which is challenging to estimate and optimize.
To address this challenge, we designed a Drift Plus Penalty Algorithm (DPPA) and a Transaction Worst-case Delay Algorithm (TWDA) based on peer node random scheduling using the Lyapunov optimization framework. The DPPA ensures the stability of the system and provides the maximum transaction processing rate under the minimum safety probability. The numerical results show that this algorithm can achieve a good balance between system security probability and queue accumulation. The TWDA considers discarding transactions with excessively long delay time by setting a worst-case transaction delay threshold. When considering both the security probability and queue accumulation of the Fabric system, the optimal scheduling of peer nodes is given. Numerical simulations were conducted on two types of algorithms, and the results showed that the security of the TWDA was slightly worse than that of the DPPA, but the system queue accumulation was significantly smaller. Therefore, the simulation results not only validate the effectiveness of the two types of algorithms but also provide operators with operational strategies that consider different factors.
{"title":"An optimal scheduling algorithm considering the transactions worst-case delay for multi-channel hyperledger fabric network","authors":"Ou Wu , Shanshan Li , He Zhang , Liwen Liu , Haoming Li , Yanze Wang , Ziyi Zhang","doi":"10.1016/j.parco.2023.103041","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103041","url":null,"abstract":"<div><p><span><span>As the most popular consortium blockchain platform, Hyperledger Fabric (Fabric for short) has released multiple versions that support different consensus protocols to address the risks faced in current and future network transactions. For example, Fabric v1.4 and v2.0 use Kafka and Raft mechanisms to complete consensus and ensure that the system can withstand failures such as crashes, </span>network partitions, or network shutdowns. In a multi-channel Fabric </span>network architecture, the system structure cannot guarantee the behavior of malicious nodes. Complex cooperation between peer groups on different channels can greatly affect the security and efficiency of the entire network architecture, which is challenging to estimate and optimize.</p><p><span><span>To address this challenge, we designed a Drift Plus Penalty Algorithm (DPPA) and a Transaction Worst-case Delay Algorithm (TWDA) based on peer node random scheduling using the Lyapunov optimization framework. The DPPA ensures the stability of the system and provides the maximum </span>transaction processing rate under the minimum safety probability. The numerical results show that this algorithm can achieve a good balance between system security probability and queue accumulation. The TWDA considers discarding transactions with excessively long </span>delay time by setting a worst-case transaction delay threshold. When considering both the security probability and queue accumulation of the Fabric system, the optimal scheduling of peer nodes is given. Numerical simulations were conducted on two types of algorithms, and the results showed that the security of the TWDA was slightly worse than that of the DPPA, but the system queue accumulation was significantly smaller. Therefore, the simulation results not only validate the effectiveness of the two types of algorithms but also provide operators with operational strategies that consider different factors.</p></div>","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103041"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In computational biology, biological database search has been playing a very important role. Since the COVID-19 outbreak, it has provided significant help in identifying common characteristics of viruses and developing vaccines and drugs. Sequence alignment, a method finding similarity, homology and other information between gene/protein sequences, is the usual tool in the database search. With the explosive growth of biological databases, the search process has become extremely time-consuming. However, existing parallel sequence alignment algorithms cannot deliver efficient database search due to low utilization of the resources such as cache memory and performance issues such as load imbalance and high communication overhead. In this paper, we propose an efficient sequence alignment algorithm on Sunway TaihuLight, called ESA, for biological database search. ESA adopts a novel hybrid alignment algorithm combining local and global alignments, which has higher accuracy than other sequence alignment algorithms. Further, ESA has several optimizations including cache-aware sequence alignment, capacity-aware load balancing and bandwidth-aware data transfer. They are implemented in a heterogeneous processor SW26010 adopted in the world’s 6th fastest supercomputer, Sunway TaihuLight. The implementation of ESA is evaluated with the Swiss-Prot database on Sunway TaihuLight and other platforms. Our experimental results show that ESA has a speedup of 34.5 on a single core group (with 65 cores) of Sunway TaihuLight. The strong and weak scalabilities of ESA are tested with 1 to 1024 core groups of Sunway TaihuLight. The results show that ESA has linear weak scalability and very impressive strong scalability. For strong scalability, ESA achieves a speedup of 338.04 with 1024 core groups compared with a single core group. We also show that our proposed optimizations are also applicable to GPU, Intel multicore processors, and heterogeneous computing platforms.
{"title":"ESA: An efficient sequence alignment algorithm for biological database search on Sunway TaihuLight","authors":"Hao Zhang , Zhiyi Huang , Yawen Chen , Jianguo Liang , Xiran Gao","doi":"10.1016/j.parco.2023.103043","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103043","url":null,"abstract":"<div><p>In computational biology, biological database search has been playing a very important role. Since the COVID-19 outbreak, it has provided significant help in identifying common characteristics of viruses and developing vaccines and drugs. Sequence alignment<span><span>, a method finding similarity, </span>homology<span> and other information between gene/protein sequences, is the usual tool in the database search. With the explosive growth of biological databases, the search process has become extremely time-consuming. However, existing parallel sequence alignment algorithms cannot deliver efficient database search due to low utilization of the resources such as cache memory and performance issues such as load imbalance and high communication overhead<span><span>. In this paper, we propose an efficient sequence alignment algorithm on Sunway TaihuLight, called ESA, for biological database search. ESA adopts a novel hybrid alignment algorithm combining local and global alignments, which has higher accuracy than other sequence alignment algorithms. Further, ESA has several optimizations including cache-aware sequence alignment, capacity-aware load balancing and bandwidth-aware data transfer. They are implemented in a heterogeneous processor SW26010 adopted in the world’s 6th fastest supercomputer<span><span>, Sunway TaihuLight. The implementation of ESA is evaluated with the Swiss-Prot database on Sunway TaihuLight and other platforms. Our experimental results show that ESA has a speedup of 34.5 on a single core group (with 65 cores) of Sunway TaihuLight. The strong and weak scalabilities of ESA are tested with 1 to 1024 core groups of Sunway TaihuLight. The results show that ESA has linear weak scalability and very impressive strong scalability. For strong scalability, ESA achieves a speedup of 338.04 with 1024 core groups compared with a single core group. We also show that our proposed optimizations are also applicable to GPU, Intel </span>multicore processors, and </span></span>heterogeneous computing platforms.</span></span></span></p></div>","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103043"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Finite element methods require the composition of the global stiffness matrix from local finite element contributions. The composition process combines the computation of element stiffness matrices and their assembly into the global stiffness matrix, which is commonly sparse. In this paper we focus on the assembly process of the global stiffness matrix and explore different algorithms and their efficiency on shared memory systems using C++. A key aspect of our investigation is the use of atomic synchronization primitives for the derivation of data-race free algorithms and data structures. Furthermore, we propose a new flexible storage format for sparse matrices and compare its performance with the compressed row storage format using abstract benchmarks based on common characteristics of finite element problems.
{"title":"A flexible sparse matrix data format and parallel algorithms for the assembly of finite element matrices on shared memory systems","authors":"Adam Sky , César Polindara , Ingo Muench , Carolin Birk","doi":"10.1016/j.parco.2023.103039","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103039","url":null,"abstract":"<div><p><span>Finite element methods<span><span> require the composition of the global stiffness matrix from local finite element contributions. The composition process combines the computation of </span>element stiffness matrices<span> and their assembly into the global stiffness matrix, which is commonly sparse. In this paper we focus on the assembly process of the global stiffness matrix and explore different algorithms and their efficiency on shared memory systems using C</span></span></span><span>++</span><span>. A key aspect of our investigation is the use of atomic synchronization primitives for the derivation of data-race free algorithms and data structures. Furthermore, we propose a new flexible storage format for sparse matrices and compare its performance with the compressed row storage format using abstract benchmarks based on common characteristics of finite element problems.</span></p></div>","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103039"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01DOI: 10.1016/j.parco.2023.103038
Jinliang Shi , Dewu Chen , Jiabi Liang , Lin Li , Yue Lin , Jianjiang Li
As one of the most widely used cluster scheduling frameworks, Hadoop YARN only supported CPU and memory scheduling in the past. Furthermore, due to the widespread use of AI, the demand for GPU is also increasing. So Hadoop YARN V3.0 adds GPU scheduling, but the granularity is on the whole card yet, rather than finer-grained graphics memory scheduling. However, during daily training, although the graphics memory required by tasks may be much smaller than the whole GPU card, they will occupy the whole card, which results in wasted resources. To address this issue, Tensorflow provides the API for graphics memory control. Therefore, we propose to introduce this feature into Hadoop YARN so that it can support the heterogeneous scheduling: CPU, memory and graphics memory. Then we take HadoopV2.7 source code as the underlying architecture and design a new scheduler GSHARE. Compared with previous scheduling strategies, with 3 nodes, 3 GPU cards per node, and 12G graphics memory per card, GSHARE improves efficiency by up to 74% for Tensorflow tasks with 2G of graphics memory. Meanwhile, it minimizes the problem of wasted graphics memory caused by the inability to control graphics memory proportionally by the API of Tensorflow for multiple-card.
{"title":"New YARN sharing GPU based on graphics memory granularity scheduling","authors":"Jinliang Shi , Dewu Chen , Jiabi Liang , Lin Li , Yue Lin , Jianjiang Li","doi":"10.1016/j.parco.2023.103038","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103038","url":null,"abstract":"<div><p>As one of the most widely used cluster scheduling frameworks, Hadoop<span> YARN only supported CPU and memory scheduling in the past. Furthermore, due to the widespread use of AI<span>, the demand for GPU<span> is also increasing. So Hadoop YARN V3.0 adds GPU scheduling, but the granularity<span> is on the whole card yet, rather than finer-grained graphics memory scheduling. However, during daily training, although the graphics memory required by tasks may be much smaller than the whole GPU card, they will occupy the whole card, which results in wasted resources. To address this issue, Tensorflow provides the API for graphics memory control. Therefore, we propose to introduce this feature into Hadoop YARN so that it can support the heterogeneous scheduling: CPU, memory and graphics memory. Then we take HadoopV2.7 source code as the underlying architecture and design a new scheduler GSHARE. Compared with previous scheduling strategies, with 3 nodes, 3 GPU cards per node, and 12G graphics memory per card, GSHARE improves efficiency by up to 74% for Tensorflow tasks with 2G of graphics memory. Meanwhile, it minimizes the problem of wasted graphics memory caused by the inability to control graphics memory proportionally by the API of Tensorflow for multiple-card.</span></span></span></span></p></div>","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103038"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01DOI: 10.1016/j.parco.2023.103033
Rene Halver , Christoph Junghans , Godehard Sutmann
The Kokkos based library Cabana, which has been developed in the Co-design Center for Particle Applications (CoPA), is used for the implementation of Multi-Particle Collision Dynamics (MPCD), a particle-based description of hydrodynamic interactions. Cabana allows for a function portable implementation, which has been used to study the interplay between CPU and GPU usage on a multi-node system as well as analysis of said interplay with performance analysis tools. As a result, we see most advantages in a homogeneous GPU usage, but we also discuss the extent to which heterogeneous applications might be more performant, using both CPU and GPU concurrently.
{"title":"Using heterogeneous GPU nodes with a Cabana-based implementation of MPCD","authors":"Rene Halver , Christoph Junghans , Godehard Sutmann","doi":"10.1016/j.parco.2023.103033","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103033","url":null,"abstract":"<div><p><span>The Kokkos based library Cabana, which has been developed in the Co-design Center for Particle Applications (CoPA), is used for the implementation of Multi-Particle Collision Dynamics<span> (MPCD), a particle-based description of hydrodynamic interactions. Cabana allows for a function portable implementation, which has been used to study the </span></span>interplay<span> between CPU<span> and GPU usage on a multi-node system as well as analysis of said interplay with performance analysis tools. As a result, we see most advantages in a homogeneous GPU usage, but we also discuss the extent to which heterogeneous applications might be more performant, using both CPU and GPU concurrently.</span></span></p></div>","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103033"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01DOI: 10.1016/j.parco.2023.103037
Ami Marowka , Przemysław Stpiczyński
{"title":"Editorial on Advances in High Performance Programming","authors":"Ami Marowka , Przemysław Stpiczyński","doi":"10.1016/j.parco.2023.103037","DOIUrl":"https://doi.org/10.1016/j.parco.2023.103037","url":null,"abstract":"","PeriodicalId":54642,"journal":{"name":"Parallel Computing","volume":"117 ","pages":"Article 103037"},"PeriodicalIF":1.4,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49877858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}