Pub Date : 2023-12-11DOI: 10.1080/00207217.2023.2289483
Swetha Siliveri, N. S. S. Reddy
{"title":"Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic","authors":"Swetha Siliveri, N. S. S. Reddy","doi":"10.1080/00207217.2023.2289483","DOIUrl":"https://doi.org/10.1080/00207217.2023.2289483","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"15 28","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138980947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-11DOI: 10.1080/00207217.2023.2289482
Sharareh Bashirazami, Mohammad Reza Amini, E. Adib, M. Delshad
{"title":"A novel non-isolated step-down converter with low switch voltage stress","authors":"Sharareh Bashirazami, Mohammad Reza Amini, E. Adib, M. Delshad","doi":"10.1080/00207217.2023.2289482","DOIUrl":"https://doi.org/10.1080/00207217.2023.2289482","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"31 22","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139010509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-02DOI: 10.1080/00207217.2022.2145502
M. Bilim
ABSTRACT In this study, the performance analysis of dual-hop power line communication (PLC)/ and PLC/ L-branch systems by using the decode-and-forward (DF) protocol is presented in detail. The introduced work provides novel closed-form expressions of the probability density function (PDF) of the instantaneous signal-to-noise ratio (SNR) of the considered systems. Taking the proposed PDFs into account, we also derive closed-form expressions of the error rate and channel capacity (CC) performance for the dual-hop PLC/ and PLC/ L-branch DF systems. Furthermore, an exhaustive comparative study of different modulation types such as non-coherent M-ary frequency-shift keying, square quadrature amplitude modulation (SQAM), and cross quadrature amplitude modulation (×QAM) is presented by using the proposed closed-form error rate expressions. Also, the exact expressions for the CC with channel inversion with a fixed-rate (CIFR) transmission policy are proposed. Finally, all the theoretical findings are confirmed through numerical results obtained by using the exact expressions.
{"title":"Dual-hop communications over PLC/η-μ and PLC/λ-μ fading channels","authors":"M. Bilim","doi":"10.1080/00207217.2022.2145502","DOIUrl":"https://doi.org/10.1080/00207217.2022.2145502","url":null,"abstract":"ABSTRACT In this study, the performance analysis of dual-hop power line communication (PLC)/ and PLC/ L-branch systems by using the decode-and-forward (DF) protocol is presented in detail. The introduced work provides novel closed-form expressions of the probability density function (PDF) of the instantaneous signal-to-noise ratio (SNR) of the considered systems. Taking the proposed PDFs into account, we also derive closed-form expressions of the error rate and channel capacity (CC) performance for the dual-hop PLC/ and PLC/ L-branch DF systems. Furthermore, an exhaustive comparative study of different modulation types such as non-coherent M-ary frequency-shift keying, square quadrature amplitude modulation (SQAM), and cross quadrature amplitude modulation (×QAM) is presented by using the proposed closed-form error rate expressions. Also, the exact expressions for the CC with channel inversion with a fixed-rate (CIFR) transmission policy are proposed. Finally, all the theoretical findings are confirmed through numerical results obtained by using the exact expressions.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"84 15","pages":"2317 - 2339"},"PeriodicalIF":1.3,"publicationDate":"2023-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138606308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-02DOI: 10.1080/00207217.2022.2145501
Guowei Lei, Wenqing Ni, Wenliang Liao, Sunqing Su
ABSTRACT Power-domain NOMA can enlarge the spectrum efficiency and capacity via serving multiple users in the same time slot. Up to now, there are still some issues to be addressed in the NOMA system with multiple users: how many users the NOMA system can accommodate with limited power, how to mitigate the interference among the users, what’s the achievable bound of capacity with limited power at the base station, and how to tackle with two or more users having similar distances to the base station. In the paper, the approximated CPM capacity in the NOMA system over Rayleigh channel is derived. Then, an adaptive user-clustering is proposed in downlink NOMA system, such that the achievable sum-rate will get high enough. Moreover, the optimal allocation of power for each user in each cluster is derived and evaluated. In the end, the performances such as outage probability, capacity, peak-to-average power ratio (PAPR), and bit error ratio (BER) are simulated as comparison.
{"title":"Adaptive clustering with continuous phase modulation in NOMA systems","authors":"Guowei Lei, Wenqing Ni, Wenliang Liao, Sunqing Su","doi":"10.1080/00207217.2022.2145501","DOIUrl":"https://doi.org/10.1080/00207217.2022.2145501","url":null,"abstract":"ABSTRACT Power-domain NOMA can enlarge the spectrum efficiency and capacity via serving multiple users in the same time slot. Up to now, there are still some issues to be addressed in the NOMA system with multiple users: how many users the NOMA system can accommodate with limited power, how to mitigate the interference among the users, what’s the achievable bound of capacity with limited power at the base station, and how to tackle with two or more users having similar distances to the base station. In the paper, the approximated CPM capacity in the NOMA system over Rayleigh channel is derived. Then, an adaptive user-clustering is proposed in downlink NOMA system, such that the achievable sum-rate will get high enough. Moreover, the optimal allocation of power for each user in each cluster is derived and evaluated. In the end, the performances such as outage probability, capacity, peak-to-average power ratio (PAPR), and bit error ratio (BER) are simulated as comparison.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"112 40","pages":"2301 - 2316"},"PeriodicalIF":1.3,"publicationDate":"2023-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138607502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-15DOI: 10.1080/00207217.2023.2278436
Reza Khajeh MohammadLou, Tohid Aribi, Tohid Sedghi, Bal S. Virdee
This paper presents a novel multi-layer beamforming antenna array based on Fabry-Perot resonator that is excited by a high-performance compact 4 × 4 Butler matrix using substrate integrated wavegui...
{"title":"A multi-beam circularly polarised Fabry-Perot resonator antenna array using SIW for X-Band applications","authors":"Reza Khajeh MohammadLou, Tohid Aribi, Tohid Sedghi, Bal S. Virdee","doi":"10.1080/00207217.2023.2278436","DOIUrl":"https://doi.org/10.1080/00207217.2023.2278436","url":null,"abstract":"This paper presents a novel multi-layer beamforming antenna array based on Fabry-Perot resonator that is excited by a high-performance compact 4 × 4 Butler matrix using substrate integrated wavegui...","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"61 2-3","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138525734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-08DOI: 10.1080/00207217.2023.2278439
Vijay Kumar Magraiya, Tarun Kumar Gupta, Rajesh Verma, Amit Kumar Pandey, Shiv Prasad Kori
ABSTRACTA novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique.KEYWORDS: DominoFinFETLECTORpull-uppull-downONOFICTemperatureDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Conflict of InterestThe authors declare that there is no conflict of interest regarding the publication of this paper.Author ContributionAll authors have made substantial contributions to the conception and design, or acquisition of data, or analysis and interpretation of data; have been involved in drafting the manuscript or revising it critically for important intellectual content; and have given final approval of the version to be published. Each author has participated sufficiently in the work to take public responsibility for appropriate portions of the content. All authors read and approved the final manuscript.The data and material are available within the manuscript.Compliance with ethical standardsThe authors declare that all procedures followed were in accordance with the ethical standards.Consent to participateAll the authors declare their consent to participate in this research article.Consent for PublicationAll the authors declare their consent for publication of the article on acceptance.Additional informationFundingThe author(s) reported there is no funding associated with the work featured in this article.
{"title":"Evaluation of dual-ONOFIC method for subthreshold leakage Reduction in domino circuit","authors":"Vijay Kumar Magraiya, Tarun Kumar Gupta, Rajesh Verma, Amit Kumar Pandey, Shiv Prasad Kori","doi":"10.1080/00207217.2023.2278439","DOIUrl":"https://doi.org/10.1080/00207217.2023.2278439","url":null,"abstract":"ABSTRACTA novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique.KEYWORDS: DominoFinFETLECTORpull-uppull-downONOFICTemperatureDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Conflict of InterestThe authors declare that there is no conflict of interest regarding the publication of this paper.Author ContributionAll authors have made substantial contributions to the conception and design, or acquisition of data, or analysis and interpretation of data; have been involved in drafting the manuscript or revising it critically for important intellectual content; and have given final approval of the version to be published. Each author has participated sufficiently in the work to take public responsibility for appropriate portions of the content. All authors read and approved the final manuscript.The data and material are available within the manuscript.Compliance with ethical standardsThe authors declare that all procedures followed were in accordance with the ethical standards.Consent to participateAll the authors declare their consent to participate in this research article.Consent for PublicationAll the authors declare their consent for publication of the article on acceptance.Additional informationFundingThe author(s) reported there is no funding associated with the work featured in this article.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"45 S213","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135343504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-07DOI: 10.1080/00207217.2023.2278437
Saurabh Kumar, Yatendra Kumar Singh
ABSTRACTThis paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of -77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves -59.7 dBc. It measures the 1.2 μs settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 μs settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is -105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.KEYWORDS: Phase-locked loop (PLL)cascaded PLLgate-diffusion input (GDI)Voltage-controlled oscillator (VCO)pulse width amplifier (PWA)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier","authors":"Saurabh Kumar, Yatendra Kumar Singh","doi":"10.1080/00207217.2023.2278437","DOIUrl":"https://doi.org/10.1080/00207217.2023.2278437","url":null,"abstract":"ABSTRACTThis paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of -77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves -59.7 dBc. It measures the 1.2 μs settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 μs settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is -105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.KEYWORDS: Phase-locked loop (PLL)cascaded PLLgate-diffusion input (GDI)Voltage-controlled oscillator (VCO)pulse width amplifier (PWA)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135540058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.1080/00207217.2023.2278434
S. Dhanasekar
ABSTRACTThis article proposes a compact compressor adder of Vedic multiplication for an area-efficient FFT architecture. A standard multi-radix-24,22,23 FFT with a single-path delay feedback structure is considered. Vedic multipliers employ the Urdhva Tiryakbhyam method, which reduces redundant steps and generates parallel partial products. The proposed 4-2 compressor adders have been introduced inside the vedic multiplier to minimise carry delay and speed up the multiplication process. The vedic multiplier designed on the compressor adder saves power and gate count. The devised FFT algorithm is implemented using 45 nm CMOS technology. Simulation results show a gate reduction of 21.5% and power consumption of 18.5%. The throughput had increased to 1.86 GS/s at 186 MHz compared to existing FFT architectures.KEYWORDS: Compressor adderFast fourier transformVedic multiplierUrdhva TiryakbhyamWireless personal area networkDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Disclosure statementNo potential conflict of interest was reported by the author.Additional informationFundingThis work is not funded by any organization or institution.
{"title":"An area efficient vedic multiplier for FFT Processor implementation using 4-2 compressor adder","authors":"S. Dhanasekar","doi":"10.1080/00207217.2023.2278434","DOIUrl":"https://doi.org/10.1080/00207217.2023.2278434","url":null,"abstract":"ABSTRACTThis article proposes a compact compressor adder of Vedic multiplication for an area-efficient FFT architecture. A standard multi-radix-24,22,23 FFT with a single-path delay feedback structure is considered. Vedic multipliers employ the Urdhva Tiryakbhyam method, which reduces redundant steps and generates parallel partial products. The proposed 4-2 compressor adders have been introduced inside the vedic multiplier to minimise carry delay and speed up the multiplication process. The vedic multiplier designed on the compressor adder saves power and gate count. The devised FFT algorithm is implemented using 45 nm CMOS technology. Simulation results show a gate reduction of 21.5% and power consumption of 18.5%. The throughput had increased to 1.86 GS/s at 186 MHz compared to existing FFT architectures.KEYWORDS: Compressor adderFast fourier transformVedic multiplierUrdhva TiryakbhyamWireless personal area networkDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Disclosure statementNo potential conflict of interest was reported by the author.Additional informationFundingThis work is not funded by any organization or institution.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135634836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-05DOI: 10.1080/00207217.2023.2278435
Banoth Vasu Naik, Arun Kumar Sinha
ABSTRACTThis paper presents simulation analysis of an inverter made from non-aligned double gate field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n-channel NADGFET and p-channel NADGFET device with a channel length of 40 nm and 50% non-alignment between gate and source/drain. The response of the inverter was tested by a combination of gate dielectric constant (k) and metal work function (ϕ). Three gate dielectrics namely, SiO2 (k = 3.9), Si3N4 (k = 7.2), HfO2 (k = 24), and three metal work function namely tungsten (ϕ = 4.5 eV), molybdenum (ϕ = 4.75 eV), gold (ϕ = 5 eV), were considered in the NADGFET inverter. This paper defines a kϕ index as characterising parameter to explore the best response from inverter configuration with minimum propagation delay, and minimum power consumption at super-high frequency. The paper proposes to analyse the NADGNFET device, in term of ION current, ION/IOFF ratio, cut-off frequency, and gate delay. And observes that low k material with moderate metal work function gives best response. The work then simulates the inverter and group the results into voltage transfer curve (VTC), transient response, and power dissipation category. The result shows that when inverter was subjected to high frequency, all the kϕ combination responds good, however when the inverter was subjected to super-high frequency, the low value of kϕ combination performs well. Thus, the result concludes that SiO2-M2 combination will be best selection to get minimum propagation delay and dynamic power dissipation by the inverter. The test strategy presented in this paper on the basis of kϕ index can serve as benchmark to test inverter device at super-high frequency.KEYWORDS: Cut-off frequencyDG-MOSFETgate-oxide dielectrichigh-frequencyinvertermetal work functionpower consumptionSub-100nm deviceTransient simulationVoltage transfer curveDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. AcknowledgmentsThe authors would like to express gratitude to VIT-AP management for their resources.Disclosure statementNo potential conflict of interest was reported by the author(s).
{"title":"Effects of metal work function and gate-Oxide dielectric on super high frequency Performance of a non-align junction DG-MOSFET based inverter in the <i>sub</i> -100 nm regime: a TCAD simulation Analysis","authors":"Banoth Vasu Naik, Arun Kumar Sinha","doi":"10.1080/00207217.2023.2278435","DOIUrl":"https://doi.org/10.1080/00207217.2023.2278435","url":null,"abstract":"ABSTRACTThis paper presents simulation analysis of an inverter made from non-aligned double gate field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n-channel NADGFET and p-channel NADGFET device with a channel length of 40 nm and 50% non-alignment between gate and source/drain. The response of the inverter was tested by a combination of gate dielectric constant (k) and metal work function (ϕ). Three gate dielectrics namely, SiO2 (k = 3.9), Si3N4 (k = 7.2), HfO2 (k = 24), and three metal work function namely tungsten (ϕ = 4.5 eV), molybdenum (ϕ = 4.75 eV), gold (ϕ = 5 eV), were considered in the NADGFET inverter. This paper defines a kϕ index as characterising parameter to explore the best response from inverter configuration with minimum propagation delay, and minimum power consumption at super-high frequency. The paper proposes to analyse the NADGNFET device, in term of ION current, ION/IOFF ratio, cut-off frequency, and gate delay. And observes that low k material with moderate metal work function gives best response. The work then simulates the inverter and group the results into voltage transfer curve (VTC), transient response, and power dissipation category. The result shows that when inverter was subjected to high frequency, all the kϕ combination responds good, however when the inverter was subjected to super-high frequency, the low value of kϕ combination performs well. Thus, the result concludes that SiO2-M2 combination will be best selection to get minimum propagation delay and dynamic power dissipation by the inverter. The test strategy presented in this paper on the basis of kϕ index can serve as benchmark to test inverter device at super-high frequency.KEYWORDS: Cut-off frequencyDG-MOSFETgate-oxide dielectrichigh-frequencyinvertermetal work functionpower consumptionSub-100nm deviceTransient simulationVoltage transfer curveDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. AcknowledgmentsThe authors would like to express gratitude to VIT-AP management for their resources.Disclosure statementNo potential conflict of interest was reported by the author(s).","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"111 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135726406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-05DOI: 10.1080/00207217.2023.2278440
Mohammad Hossein Mousavi, Hassan Moradi
ABSTRACTThere are many effective techniques for virtual inertia emulation in DC microgrids that can help DC bus voltage stability through power exchange with virtual inertia injection. But one of the vexingly complicated challenges in virtual inertia emulation is the connection of unbalanced loads on the AC side of a DC microgrid. Unbalanced AC loads connected to a DC microgrid may cause severe fluctuations in DC bus voltage and battery power, as well as distorting AC side voltage. The need to solve this issue is very important because it can be a threat to the microgrid DC bus voltage stability and feed sensitive loads. One effective method to mimic the real inertia feature and dampen the unfavourable unbalanced conditions is to employ a virtual synchronous generator (VSG) equipped with a decoupled double synchronous reference frame (DDSRF) approach. The DDSRF can extract positive and negative components with high precision and create pure DC signals for the control system to improve accuracy and controllability. Hence, this paper investigates a combination of a VSG structure enhanced with a DDSRF technique to attenuate the fluctuations of DC bus voltage, battery power, and AC-side voltage caused by an unbalanced AC load in an islanded DC microgrid. The simulation results confirm that the unbalanced loads connected to the AC side of the microgrid are destructive for DC bus voltage, battery power, and also create voltage imbalances for AC loads. Furthermore, the proposed DDSRF-based VSG control system that has been implemented on the AC side of the microgrid can strongly dampen the fluctuations on the DC bus, battery, and AC loads.KEYWORDS: DC bus voltage regulationunbalanced load compensationvirtual synchronous generatorDDSRFmicrogridDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Conflict of InterestThe authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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