Pub Date : 2023-11-02DOI: 10.1080/00207217.2023.2278438
Yi Wu, Keqi Mei, Lu Liu, Shinghong Ding, Yuanzhu Wu, Qunhui Ge
ABSTRACTTraditional vector control strategies can not eliminate the disturbances existing in permanent magnet synchronous motor (PMSM) systems while maintaining their dynamic performances. To address this issue, this paper proposes an adaptive continuous twisting (ACT) control method to further improve the control accuracy and anti-interference ability of the PMSM system. Firstly, a continuous twisting controller is designed to generate a continuous signal, which is utilised in the speed loop. It can guarantee that the tracking error of the speed regulation system finite-time converges to zero. This not only enhances the robustness of PMSM system, but also effectively weakens the control chattering. Secondly, on this basis, an ACT controller is constructed to handle the disturbances with unknown bounds in PMSM systems. Finally, simulation and experimental results show that the proposed control method can improve the performances of PMSM system.KEYWORDS: PMSMadaptive controlspeed controlcontinuous twisting controlDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Additional informationFundingThis work was supported by the National Natural Science Foundation of China under Grant 61973142, Grant 62373170 and Grant 62203188.
{"title":"Adaptive continuous twisting control for speed regulation in PMSM","authors":"Yi Wu, Keqi Mei, Lu Liu, Shinghong Ding, Yuanzhu Wu, Qunhui Ge","doi":"10.1080/00207217.2023.2278438","DOIUrl":"https://doi.org/10.1080/00207217.2023.2278438","url":null,"abstract":"ABSTRACTTraditional vector control strategies can not eliminate the disturbances existing in permanent magnet synchronous motor (PMSM) systems while maintaining their dynamic performances. To address this issue, this paper proposes an adaptive continuous twisting (ACT) control method to further improve the control accuracy and anti-interference ability of the PMSM system. Firstly, a continuous twisting controller is designed to generate a continuous signal, which is utilised in the speed loop. It can guarantee that the tracking error of the speed regulation system finite-time converges to zero. This not only enhances the robustness of PMSM system, but also effectively weakens the control chattering. Secondly, on this basis, an ACT controller is constructed to handle the disturbances with unknown bounds in PMSM systems. Finally, simulation and experimental results show that the proposed control method can improve the performances of PMSM system.KEYWORDS: PMSMadaptive controlspeed controlcontinuous twisting controlDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Additional informationFundingThis work was supported by the National Natural Science Foundation of China under Grant 61973142, Grant 62373170 and Grant 62203188.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135933021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-30DOI: 10.1080/00207217.2023.2267219
T. Vijayalakshmi, J. Selvakumar
{"title":"Circuit fault detection model using multiclass support vector machine","authors":"T. Vijayalakshmi, J. Selvakumar","doi":"10.1080/00207217.2023.2267219","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267219","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"439 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136102597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-27DOI: 10.1080/00207217.2023.2276684
Chong Zhang, Donghu Li, Yushun Zhao, Dongsheng Yu
{"title":"Wide voltage range and low Current ripple bidirectional DC/DC converter","authors":"Chong Zhang, Donghu Li, Yushun Zhao, Dongsheng Yu","doi":"10.1080/00207217.2023.2276684","DOIUrl":"https://doi.org/10.1080/00207217.2023.2276684","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136316385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
ABSTRACTA Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA) based resistor tunable memristor emulator has been proposed in this work. The emulator can be used in both grounded and floating circumstances. The proposed design incorporates only one active block along with few passive components. Moreover, the circuit can operate in both incremental and decremental modes, by simply changing the input ports. The circuit demonstrates all the characteristics of an ideal memristor up to 6 MHz. The proposed model has been simulated using TSMC 0.18μm process parameter and occupies an area of 51 × 42.5 μm2 chip-area, excluding capacitor. The circuit’s reliability has been verified by studying non-ideal, non-volatile, Monte-Carlo, process corner variations analysis. The circuit applicability has been tested through series/parallel combinations. To validate the experimental demonstration, AD844AN and CA3080 have been used to make a prototype, which shows good agreement with theoretical and simulation results.KEYWORDS: Memristor emulator (MRE), Current mode (CM)Differential difference Current conveyor transconductance amplifier (DDCCTA)Pinched hysteresis loop (PHL)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"Tunable floating and grounded memristor emulator Model","authors":"Sagar Surendra Prasad, Somenath Dutta, Chandan Kumar Chobey, Sanjay Kumar Dubey, Bindu Priyadarshini, Rajeev Kumar Ranjan","doi":"10.1080/00207217.2023.2267218","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267218","url":null,"abstract":"ABSTRACTA Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA) based resistor tunable memristor emulator has been proposed in this work. The emulator can be used in both grounded and floating circumstances. The proposed design incorporates only one active block along with few passive components. Moreover, the circuit can operate in both incremental and decremental modes, by simply changing the input ports. The circuit demonstrates all the characteristics of an ideal memristor up to 6 MHz. The proposed model has been simulated using TSMC 0.18μm process parameter and occupies an area of 51 × 42.5 μm2 chip-area, excluding capacitor. The circuit’s reliability has been verified by studying non-ideal, non-volatile, Monte-Carlo, process corner variations analysis. The circuit applicability has been tested through series/parallel combinations. To validate the experimental demonstration, AD844AN and CA3080 have been used to make a prototype, which shows good agreement with theoretical and simulation results.KEYWORDS: Memristor emulator (MRE), Current mode (CM)Differential difference Current conveyor transconductance amplifier (DDCCTA)Pinched hysteresis loop (PHL)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135804036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-09DOI: 10.1080/00207217.2023.2267216
N Agnes Shiny Rachel, G Rajakumar
ABSTRACTHeart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The Least mean square (LMS) filter with Co-ordinate Rotation Digital Computer(CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies leakage power has started to occupy 30-50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, Integrated coarse grained Power and Clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch, AND and OR based clock gating with Forced transistor stacking and sleep transistor whose width and length is doubled from the rest of the Complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques is found to be 36.95% from the non-gated CORDIC LMS filter design.KEYWORDS: Clock gatingpower gatingpacemakerCORDIC algorithmLMS filterDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"A ROBUST LOW POWER FSM CORDIC LMS FILTER DESIGN for EXPONENTIAL NOISE REMOVAL in PACEMAKER","authors":"N Agnes Shiny Rachel, G Rajakumar","doi":"10.1080/00207217.2023.2267216","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267216","url":null,"abstract":"ABSTRACTHeart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The Least mean square (LMS) filter with Co-ordinate Rotation Digital Computer(CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies leakage power has started to occupy 30-50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, Integrated coarse grained Power and Clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch, AND and OR based clock gating with Forced transistor stacking and sleep transistor whose width and length is doubled from the rest of the Complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques is found to be 36.95% from the non-gated CORDIC LMS filter design.KEYWORDS: Clock gatingpower gatingpacemakerCORDIC algorithmLMS filterDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135045364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-06DOI: 10.1080/00207217.2023.2267214
S. Sathishkumar, V. Kamatchi Kannan, C. Maheswari, S. Albert Alexander
ABSTRACTWith the advancements in electric vehicles in the market, it is necessary to rephrase the converter for effective gain. The proposed Two Input – Two Output (TITO) converter accepts input from two sources: Battery and Solar PV panel included with non-isolated buck, boost, and buck-boost DC-DC converters. Also, the proposed TITO converter topology uses only three switches when compared to conventional multiport converter where the number of semiconductor switches are higher. The conventional converter has a higher number of components whereas the proposed converter has a reduced number of conduction components as well as switching semiconductors. As a result, there is a reduction in energy lost. The proposed topology is designed and simulated in MATLAB Simulink and observed with a lower ripple voltage during buck, boost and buck-boost mode. The experimental setup results are also obtained from the prototype of the proposed converter which confirms the theoretical considerations and effectiveness of the proposed topology.KEYWORDS: BLDCbuckboost and buck-boost converterEV lightingMultiportSolar PVDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"High gain novel Two input Two output buck - boost converter for electric vehicle applications","authors":"S. Sathishkumar, V. Kamatchi Kannan, C. Maheswari, S. Albert Alexander","doi":"10.1080/00207217.2023.2267214","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267214","url":null,"abstract":"ABSTRACTWith the advancements in electric vehicles in the market, it is necessary to rephrase the converter for effective gain. The proposed Two Input – Two Output (TITO) converter accepts input from two sources: Battery and Solar PV panel included with non-isolated buck, boost, and buck-boost DC-DC converters. Also, the proposed TITO converter topology uses only three switches when compared to conventional multiport converter where the number of semiconductor switches are higher. The conventional converter has a higher number of components whereas the proposed converter has a reduced number of conduction components as well as switching semiconductors. As a result, there is a reduction in energy lost. The proposed topology is designed and simulated in MATLAB Simulink and observed with a lower ripple voltage during buck, boost and buck-boost mode. The experimental setup results are also obtained from the prototype of the proposed converter which confirms the theoretical considerations and effectiveness of the proposed topology.KEYWORDS: BLDCbuckboost and buck-boost converterEV lightingMultiportSolar PVDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134944085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-06DOI: 10.1080/00207217.2023.2267217
Mehmet Ali USTA, Erdinç Şahi̇n
ABSTRACT– This paper presents ready-to-use nonlinear and linear averaged models of an improved cascade buck converter (ICBC) for the first time. A detailed steady-state analysis is also given, providing its operating modes, equilibrium values, and design guidelines. The modelling process consists of two stages. First, the nonlinear model is obtained using the state-space averaging technique. Subsequently, the averaged model is linearised by applying the small-ripple approximation and the small-signal model is achieved. Furthermore, the developed small-signal model is employed to derive three significant transfer functions of the converter. The proposed converter model is valid for the continuous conduction mode (CCM) when the duty cycle is lower than 0.5. To be used in validation studies, an exemplary converter with 144W rated power that steps down 320V input voltage to 24V is designed. The accuracy of theoretical analyses is confirmed by the simulation results of the designed converter. Similarly, all proposed models are validated with the simulations done in both frequency-domain and time-domain. The results show that the proposed parametric model response closely matches that of the switching (non-parametric) model and hence it can be safely used for controller design in feedback systems.KEYWORDS: Cascade buck converterhigh step-down conversion ratiosteady-state analysisstate-space averaging techniquesmall-signal modeltransfer functionDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"Detailed analysis and modeling of improved cascade buck converter","authors":"Mehmet Ali USTA, Erdinç Şahi̇n","doi":"10.1080/00207217.2023.2267217","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267217","url":null,"abstract":"ABSTRACT– This paper presents ready-to-use nonlinear and linear averaged models of an improved cascade buck converter (ICBC) for the first time. A detailed steady-state analysis is also given, providing its operating modes, equilibrium values, and design guidelines. The modelling process consists of two stages. First, the nonlinear model is obtained using the state-space averaging technique. Subsequently, the averaged model is linearised by applying the small-ripple approximation and the small-signal model is achieved. Furthermore, the developed small-signal model is employed to derive three significant transfer functions of the converter. The proposed converter model is valid for the continuous conduction mode (CCM) when the duty cycle is lower than 0.5. To be used in validation studies, an exemplary converter with 144W rated power that steps down 320V input voltage to 24V is designed. The accuracy of theoretical analyses is confirmed by the simulation results of the designed converter. Similarly, all proposed models are validated with the simulations done in both frequency-domain and time-domain. The results show that the proposed parametric model response closely matches that of the switching (non-parametric) model and hence it can be safely used for controller design in feedback systems.KEYWORDS: Cascade buck converterhigh step-down conversion ratiosteady-state analysisstate-space averaging techniquesmall-signal modeltransfer functionDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134944489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-06DOI: 10.1080/00207217.2023.2267211
Xiaotong Zhou, Dongsheng Yu, Zhaokun Li, Shenglong Yu, Muhammad Junaid
ABSTRACTMemristors (MRs) have been used in integrated circuit design due to their nanoscale size and low power consumption. In this study, a flux-controlled binary MR emulator is designed by using off-the-shelf circuit components. Then, two MR-based multi-vibrators are constructed and applied to pulse train (PT) controlled Buck converters. Compared with traditional PT controlled Buck converters requiring two pulse train generators, only one single memristive pulse generator with controllable duty cycle is used to regulate the output voltage. To suppress the low-frequency oscillations of the PT-controlled Buck converter in continuous conduction mode (CCM), an inductor current based PT (IC-PT) control method is devised with the proposed MR-based pulse generator. Simulation and experimental results both show that the IC-PT-controlled Buck converter with the MR-based pulse generator can achieve fast transient response and minimum low-frequency voltage oscillations in the CCM.KEYWORDS: Memristormemristor based multi-vibratorPT controlpower converterDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Additional informationFundingNational Natural Science Foundation of China, Grant Number: 51977208.
{"title":"A pulse train controlled Buck converter based on a Single Memristive multi-Vibrator","authors":"Xiaotong Zhou, Dongsheng Yu, Zhaokun Li, Shenglong Yu, Muhammad Junaid","doi":"10.1080/00207217.2023.2267211","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267211","url":null,"abstract":"ABSTRACTMemristors (MRs) have been used in integrated circuit design due to their nanoscale size and low power consumption. In this study, a flux-controlled binary MR emulator is designed by using off-the-shelf circuit components. Then, two MR-based multi-vibrators are constructed and applied to pulse train (PT) controlled Buck converters. Compared with traditional PT controlled Buck converters requiring two pulse train generators, only one single memristive pulse generator with controllable duty cycle is used to regulate the output voltage. To suppress the low-frequency oscillations of the PT-controlled Buck converter in continuous conduction mode (CCM), an inductor current based PT (IC-PT) control method is devised with the proposed MR-based pulse generator. Simulation and experimental results both show that the IC-PT-controlled Buck converter with the MR-based pulse generator can achieve fast transient response and minimum low-frequency voltage oscillations in the CCM.KEYWORDS: Memristormemristor based multi-vibratorPT controlpower converterDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Additional informationFundingNational Natural Science Foundation of China, Grant Number: 51977208.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135350342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-06DOI: 10.1080/00207217.2023.2267210
G Sivakannu, R Marshal, P Muthuchidambaranathan
ABSTRACTNon Orthogonal Multiple Access technique (NOMA) is a potential and promising candidate for 5 G and beyond 5 G due to its better spectral efficiency and low latency. However, it faces implementation challenges in densely populated networks due to its computational complexity. In NOMA, for decoding Nth user information at the receiver end, it needs to perform (N−1) times perfect Successive Interference Cancellation (SIC) operation. Hence, in a dense network, where the number of users is high, the implementation of NOMA becomes tedious. In order to improve the performance of NOMA implementation, in this work, the concept of Cooperative Modulated-NOMA (CM-NOMA) is applied in the considered densely populated networks model. Performance analysis of the system in terms of outage probability, Symbol-to-Error Rate (SER) and achievable data rate in both one-to-one and cooperative communications scenarios are done. The analytical expressions are also validated using Monte Carlo simulation. The results show that the deployment of CM-NOMA in a densely populated network increases the performance of the system, and also reduces the computational complexity.KEYWORDS: 5GNon orthogonal multiple access technique (NOMA)Cooperative modulated-NOMA (CM-NOMA)Outage probabilitySuccessive interference cancellation (SIC)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Data AvailabilityData sharing not applicable to this article as no datasets were generated or analyzed during the current study.Conflict of interestThe authors declare that they have no conflict of interest.
{"title":"Performance Improvement and Analysis of NOMA in densely populated networks","authors":"G Sivakannu, R Marshal, P Muthuchidambaranathan","doi":"10.1080/00207217.2023.2267210","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267210","url":null,"abstract":"ABSTRACTNon Orthogonal Multiple Access technique (NOMA) is a potential and promising candidate for 5 G and beyond 5 G due to its better spectral efficiency and low latency. However, it faces implementation challenges in densely populated networks due to its computational complexity. In NOMA, for decoding Nth user information at the receiver end, it needs to perform (N−1) times perfect Successive Interference Cancellation (SIC) operation. Hence, in a dense network, where the number of users is high, the implementation of NOMA becomes tedious. In order to improve the performance of NOMA implementation, in this work, the concept of Cooperative Modulated-NOMA (CM-NOMA) is applied in the considered densely populated networks model. Performance analysis of the system in terms of outage probability, Symbol-to-Error Rate (SER) and achievable data rate in both one-to-one and cooperative communications scenarios are done. The analytical expressions are also validated using Monte Carlo simulation. The results show that the deployment of CM-NOMA in a densely populated network increases the performance of the system, and also reduces the computational complexity.KEYWORDS: 5GNon orthogonal multiple access technique (NOMA)Cooperative modulated-NOMA (CM-NOMA)Outage probabilitySuccessive interference cancellation (SIC)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Data AvailabilityData sharing not applicable to this article as no datasets were generated or analyzed during the current study.Conflict of interestThe authors declare that they have no conflict of interest.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134943849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-06DOI: 10.1080/00207217.2023.2267212
Ahmad Ghiasi, Salah I. Yahya, Abbas Rezaei
ABSTRACTIn this paper, two new silicon on insulator metal-semiconductor field effect transistor (SOI-MESFET) structures are presented. Two parallel layers of oxide and aluminium are added at the gate edge of these structures. Also, in the buried oxide part of the Aluminium Edge and Silicon-Well MESFET (AESW-MESFET) structure, a silicon well and two aluminium layers are added. Moreover, and to improve the DC and RF characteristics, as compared to the Conventional MESFET (C-MESFET) structure, a silicon well and a silicon layer are added in the box oxide section in the Silicon Edge and Silicon-Well MESFET (SESW-MESFET) structure. By these changes, the value of the breakdown voltage in the normal structure has increased from 15.8 V to 33.1 V and 30.9 V in the proposed AESW-MESFET and SESW-MESFET structures, respectively. In addition, the maximum output power has been associated with a significant increase of 4.44 and 5.24 times, respectively. Compared to the C-MESFET, the proposed structures reduce gate-source and gate-drain capacitors and significantly increases conductivity. The cut-off frequency values are increased from 19.3 GHz (the normal structure) to 37.3 GHz and 35 GHz (the proposed structures), and the maximum oscillation frequencies are increased from 80 GHz to 154 GHz and 102.3 GHz. Therefore, the results show that the proposed structures have good performance and the ability to work at high power and high frequency.KEYWORDS: SOI-MESFETBreakdown voltageElectric fieldCut-off frequency (FT)maximum oscillation frequency (Fmax)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Data Availability StatementNo Data associated in the manuscript.
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