Pub Date : 2008-03-31DOI: 10.1109/TEPM.2008.919342
M.-H.C. Li, Abbas Al-Refaie, Cheng-Yu Yang
One of the major manufacturing processes of surface-mount technology (SMT) is the solder paste printing process. In this process, the thickness of deposited solder paste on printed circuit board (PCB) pads is a key quality characteristic (QCH) of main concern. In practice, large deviations of solder thickness from a nominal value result in SMT defects that may cause PCB failure. This paper implements the define-measure-analyze-improve-control (DMAIC) approach to improve the capability of the solder paste printing process by reducing thickness variations from a nominal value. Process mapping and identifying key QCH are carried out in the "define" phase, while mean x macr and range R control charts followed by the estimates of process capability indices are adopted in the "measure" phase. Then, the Taguchi method including L18 orthogonal array (OA), signal-to-noise (S/N) ratio, and analysis of variance (ANOVA) for S/N ratio is implemented in the "analyze" phase. Taguchi's two-step optimization is conducted in the "improve phase." Finally, the x macr and R control charts for solder thickness are used in the "control" phase. Adopting the DMAIC approach including the Taguchi method, the estimated standard deviation sigma circ of solder thickness is reduced from 13.69 to 6.04, while the process mean is adjusted on 150.1 mum which is very close to the target value of 150 mum. In addition, the process capability index C circpk is enhanced from 0.487 to 1.432.
表面贴装技术(SMT)的主要制造工艺之一是焊膏印刷工艺。在此过程中，印制电路板(PCB)焊盘上沉积锡膏的厚度是主要关注的关键质量特性(QCH)。在实践中，焊料厚度与标称值的较大偏差会导致SMT缺陷，从而可能导致PCB失效。本文实现了定义-测量-分析-改进-控制(DMAIC)方法，通过减少标称值的厚度变化来提高锡膏印刷过程的能力。在“定义”阶段进行过程映射和识别关键QCH，在“测量”阶段采用mean x macr和range R控制图，然后对过程能力指标进行估计。然后，在“分析”阶段实现了包括L18正交阵列(OA)、信噪比(S/N)和信噪比方差分析(ANOVA)在内的田口法。田口的两步优化是在“改进阶段”进行的。最后，在“控制”阶段使用焊料厚度的x macr和R控制图。采用包括田口法在内的DMAIC方法，将焊料厚度的估计标准差sigma circ从13.69降低到6.04，而将工艺平均值调整为150.1 mum，非常接近目标值150 mum。加工能力指数C circpk由0.487提高到1.432。
{"title":"DMAIC Approach to Improve the Capability of SMT Solder Printing Process","authors":"M.-H.C. Li, Abbas Al-Refaie, Cheng-Yu Yang","doi":"10.1109/TEPM.2008.919342","DOIUrl":"https://doi.org/10.1109/TEPM.2008.919342","url":null,"abstract":"One of the major manufacturing processes of surface-mount technology (SMT) is the solder paste printing process. In this process, the thickness of deposited solder paste on printed circuit board (PCB) pads is a key quality characteristic (QCH) of main concern. In practice, large deviations of solder thickness from a nominal value result in SMT defects that may cause PCB failure. This paper implements the define-measure-analyze-improve-control (DMAIC) approach to improve the capability of the solder paste printing process by reducing thickness variations from a nominal value. Process mapping and identifying key QCH are carried out in the \"define\" phase, while mean x macr and range R control charts followed by the estimates of process capability indices are adopted in the \"measure\" phase. Then, the Taguchi method including L18 orthogonal array (OA), signal-to-noise (S/N) ratio, and analysis of variance (ANOVA) for S/N ratio is implemented in the \"analyze\" phase. Taguchi's two-step optimization is conducted in the \"improve phase.\" Finally, the x macr and R control charts for solder thickness are used in the \"control\" phase. Adopting the DMAIC approach including the Taguchi method, the estimated standard deviation sigma circ of solder thickness is reduced from 13.69 to 6.04, while the process mean is adjusted on 150.1 mum which is very close to the target value of 150 mum. In addition, the process capability index C circpk is enhanced from 0.487 to 1.432.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"59 1","pages":"126-133"},"PeriodicalIF":0.0,"publicationDate":"2008-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87379203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-31DOI: 10.1109/TEPM.2008.919332
T. Wang, Y. Lai
A design that optimizes package-level along with board-level thermomechanical reliability of a flip-chip package implemented with an organic or a silicon substrate is provided for the package subjected to an accelerated thermal cycling test condition. Different control factors including thickness of substrate, die, board, and polyimide or soldermask are considered. The optimal design is obtained using an L9 (34) orthogonal array according to the Taguchi optimization method. Importance of each of these control factors is also ranked.
{"title":"Optimization of Thermomechanical Reliability of Board-Level Flip-Chip Packages Implemented With Organic or Silicon Substrates","authors":"T. Wang, Y. Lai","doi":"10.1109/TEPM.2008.919332","DOIUrl":"https://doi.org/10.1109/TEPM.2008.919332","url":null,"abstract":"A design that optimizes package-level along with board-level thermomechanical reliability of a flip-chip package implemented with an organic or a silicon substrate is provided for the package subjected to an accelerated thermal cycling test condition. Different control factors including thickness of substrate, die, board, and polyimide or soldermask are considered. The optimal design is obtained using an L9 (34) orthogonal array according to the Taguchi optimization method. Importance of each of these control factors is also ranked.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"62 2 1","pages":"174-179"},"PeriodicalIF":0.0,"publicationDate":"2008-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88457081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-31DOI: 10.1109/TEPM.2008.919339
K. Noh, Hyeon-Cheol Lee, Dae-Young Kim, M. Oh
Practical studies on the method of contamination control for yield enhancement in the cellular phone modules production line were carried out. A contamination control method was proposed, consisting of data collection, data analysis, improvement action, verification, and implementation of control. The partition check method and the composition analysis for data collection and data analysis were respectively used in the cellular phone modules manufacturing process, and these methods were evaluated by the variation of yield loss before and after implementing the actions for improvement. In the partition check method, the critical process step was selected, and yield loss reduction through improvement actions was observed, whereas in the composition analysis, critical sources were selected, and yield loss reduction through improvement actions was investigated. From the results, it is concluded that the partition check and the composition analysis are effective solutions for contamination control in cleanroom production lines.
{"title":"Study on Contamination Control for Yield Enhancement in the Manufacturing Line of Cellular Phone Modules","authors":"K. Noh, Hyeon-Cheol Lee, Dae-Young Kim, M. Oh","doi":"10.1109/TEPM.2008.919339","DOIUrl":"https://doi.org/10.1109/TEPM.2008.919339","url":null,"abstract":"Practical studies on the method of contamination control for yield enhancement in the cellular phone modules production line were carried out. A contamination control method was proposed, consisting of data collection, data analysis, improvement action, verification, and implementation of control. The partition check method and the composition analysis for data collection and data analysis were respectively used in the cellular phone modules manufacturing process, and these methods were evaluated by the variation of yield loss before and after implementing the actions for improvement. In the partition check method, the critical process step was selected, and yield loss reduction through improvement actions was observed, whereas in the composition analysis, critical sources were selected, and yield loss reduction through improvement actions was investigated. From the results, it is concluded that the partition check and the composition analysis are effective solutions for contamination control in cleanroom production lines.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"94 1","pages":"143-149"},"PeriodicalIF":0.0,"publicationDate":"2008-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83451265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-07DOI: 10.1109/TEPM.2007.914210
K. Courey, S. Asfour, A. Onar, J. Bayliss, L. L. Ludwig, M. Wright
Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that has an unknown probability associated with it. Note however that due to contact resistance, electrical shorts may not occur at lower voltage levels. In our first paper, we developed an empirical probability model for tin whisker shorting. In this paper, we develop a more comprehensive empirical model using a refined experiment with a larger sample size, in which we studied the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From the resulting data, we estimated the probability distribution of an electrical short, as a function of voltage. In addition, the unexpected polycrystalline structure seen in the focused ion beam (FIB) cross section in the first experiment was confirmed in this experiment using transmission electron microscopy (TEM). The FIB was also used to cross section two card guides to facilitate the measurement of the grain size of each card guide's tin plating to determine its finish.
{"title":"Tin Whisker Electrical Short Circuit Characteristics—Part II","authors":"K. Courey, S. Asfour, A. Onar, J. Bayliss, L. L. Ludwig, M. Wright","doi":"10.1109/TEPM.2007.914210","DOIUrl":"https://doi.org/10.1109/TEPM.2007.914210","url":null,"abstract":"Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that has an unknown probability associated with it. Note however that due to contact resistance, electrical shorts may not occur at lower voltage levels. In our first paper, we developed an empirical probability model for tin whisker shorting. In this paper, we develop a more comprehensive empirical model using a refined experiment with a larger sample size, in which we studied the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From the resulting data, we estimated the probability distribution of an electrical short, as a function of voltage. In addition, the unexpected polycrystalline structure seen in the focused ion beam (FIB) cross section in the first experiment was confirmed in this experiment using transmission electron microscopy (TEM). The FIB was also used to cross section two card guides to facilitate the measurement of the grain size of each card guide's tin plating to determine its finish.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"13 1","pages":"41-48"},"PeriodicalIF":0.0,"publicationDate":"2008-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74234731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-07DOI: 10.1109/TEPM.2007.914211
S. Iyer, S. Sajjala, P. Damodaran, K. Srihari
The introduction of 0201 components is another step taken in the world of electronics to aid the miniaturization of electronic products. Capacitors and resistors are now being produced in a 0201 package size; in dimensions, it means a length of 0.02 in and a width of 0.01 in. The assembly of miniature components on printed circuit boards (PCBs) poses numerous process challenges. Legislative measures to eliminate the usage of lead from electronics products compel electronics manufacturers to implement lead-free assembly. This mandates the use of lead-free 0201 components and a lead-free soldering process. The current research focuses on high-density lead-free memory module assemblies using a 1.27-mm-thick organic solderability preservative (OSP)-coated boards. The spacing between components is as low as 0.25 mm. The objective of this research is to develop a robust assembly process for lead-free 0201 components used in memory modules. The stencil, PCB land pattern designs, solder paste printing, component placement, and reflow soldering processes were studied. The process and design changes required for achieving a robust manufacturing process for assembling lead-free 0201 components on high-density assemblies have been identified and reported.
{"title":"Implementing 0201s On High-Density Lead-Free Memory Modules","authors":"S. Iyer, S. Sajjala, P. Damodaran, K. Srihari","doi":"10.1109/TEPM.2007.914211","DOIUrl":"https://doi.org/10.1109/TEPM.2007.914211","url":null,"abstract":"The introduction of 0201 components is another step taken in the world of electronics to aid the miniaturization of electronic products. Capacitors and resistors are now being produced in a 0201 package size; in dimensions, it means a length of 0.02 in and a width of 0.01 in. The assembly of miniature components on printed circuit boards (PCBs) poses numerous process challenges. Legislative measures to eliminate the usage of lead from electronics products compel electronics manufacturers to implement lead-free assembly. This mandates the use of lead-free 0201 components and a lead-free soldering process. The current research focuses on high-density lead-free memory module assemblies using a 1.27-mm-thick organic solderability preservative (OSP)-coated boards. The spacing between components is as low as 0.25 mm. The objective of this research is to develop a robust assembly process for lead-free 0201 components used in memory modules. The stencil, PCB land pattern designs, solder paste printing, component placement, and reflow soldering processes were studied. The process and design changes required for achieving a robust manufacturing process for assembling lead-free 0201 components on high-density assemblies have been identified and reported.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"12 1","pages":"41-50"},"PeriodicalIF":0.0,"publicationDate":"2008-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82418376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-07DOI: 10.1109/TEPM.2007.914222
L. Ladani, A. Dasgupta, I. Cardoso, E. Monlevade
This paper presents a systematic approach to study the effect of manufacturing variables on the creation of defects and the effect of those defects on the durability of lead-free (Pb-free) solder joints. An experiment was designed to systematically vary the printing and reflow process variables in order to fabricate error-seeded test assemblies. The error-seeded samples were then inspected visually and with X-ray, to identify different types of defects, especially voids, and then test for electrical performance. The specimens were subjected to an accelerated thermal cycling test to characterize the durability of these error-seeded specimens and to study the effect of each manufacturing variable on the durability of the solder joints. The response variables for the design of experiments are thermal cycling durability of the solder joints and void area percentage in ball grid array (BGA) solder joints. Pretest microstructural analysis showed that specimens produced under inadequate reflow profiles suffered from insufficient wetting and insufficient intermetallic formation. Statistical analysis of the response variables shows that waiting time, heating ramp, peak temperature, and cooling rate have nonlinear effects on thermal cycling durability. Two variables in particular [peak temperature and waiting time (the time waited after the solder paste barrel was opened and before print)] appear to have optimum values within the ranges investigated. Statistical analysis of void percentage area for all design of experiment (DOE) runs show that higher stencil thickness results in higher void percentage and that void percentage increases as time above melt and peak temperature increases.
{"title":"Effect of Selected Process Parameters on Durability and Defects in Surface-Mount Assemblies for Portable Electronics","authors":"L. Ladani, A. Dasgupta, I. Cardoso, E. Monlevade","doi":"10.1109/TEPM.2007.914222","DOIUrl":"https://doi.org/10.1109/TEPM.2007.914222","url":null,"abstract":"This paper presents a systematic approach to study the effect of manufacturing variables on the creation of defects and the effect of those defects on the durability of lead-free (Pb-free) solder joints. An experiment was designed to systematically vary the printing and reflow process variables in order to fabricate error-seeded test assemblies. The error-seeded samples were then inspected visually and with X-ray, to identify different types of defects, especially voids, and then test for electrical performance. The specimens were subjected to an accelerated thermal cycling test to characterize the durability of these error-seeded specimens and to study the effect of each manufacturing variable on the durability of the solder joints. The response variables for the design of experiments are thermal cycling durability of the solder joints and void area percentage in ball grid array (BGA) solder joints. Pretest microstructural analysis showed that specimens produced under inadequate reflow profiles suffered from insufficient wetting and insufficient intermetallic formation. Statistical analysis of the response variables shows that waiting time, heating ramp, peak temperature, and cooling rate have nonlinear effects on thermal cycling durability. Two variables in particular [peak temperature and waiting time (the time waited after the solder paste barrel was opened and before print)] appear to have optimum values within the ranges investigated. Statistical analysis of void percentage area for all design of experiment (DOE) runs show that higher stencil thickness results in higher void percentage and that void percentage increases as time above melt and peak temperature increases.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"14 1","pages":"51-60"},"PeriodicalIF":0.0,"publicationDate":"2008-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89605046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-07DOI: 10.1109/TEPM.2007.914217
C. Banda, R.W. Johnson, Tan Zhang, Z. Hou, H. Charles
Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented.
{"title":"Flip Chip Assembly of Thinned Silicon Die on Flex Substrates","authors":"C. Banda, R.W. Johnson, Tan Zhang, Z. Hou, H. Charles","doi":"10.1109/TEPM.2007.914217","DOIUrl":"https://doi.org/10.1109/TEPM.2007.914217","url":null,"abstract":"Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"183 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2008-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74632436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-07DOI: 10.1109/TEPM.2007.914229
K. Pochampally, Surendra M. Gupta
Strategic planning (also called designing) is a challenging aspect of a reverse supply chain network. To effectively satisfy drivers such as profitability, environmental regulations, and asset recovery, only the most economical used products must be reprocessed in only the recovery facilities that have the potential to efficiently reprocess them. Due to uncertainties in supply, quality, and reprocessing times of used products, the cost-benefit function in the literature that selects the most economical product to reprocess from a set of used products is not appropriate for direct adoption. Moreover, due to the same uncertainties, any traditional forward supply chain approach to identify potential manufacturing facilities cannot be employed to identify potential recovery facilities. This paper proposes a three-phase fuzzy logic approach, taking the above uncertainties into account, to design a reverse supply chain network. Application of the approach is detailed through an illustrative example in each phase.
{"title":"A Multiphase Fuzzy Logic Approach to Strategic Planning of a Reverse Supply Chain Network","authors":"K. Pochampally, Surendra M. Gupta","doi":"10.1109/TEPM.2007.914229","DOIUrl":"https://doi.org/10.1109/TEPM.2007.914229","url":null,"abstract":"Strategic planning (also called designing) is a challenging aspect of a reverse supply chain network. To effectively satisfy drivers such as profitability, environmental regulations, and asset recovery, only the most economical used products must be reprocessed in only the recovery facilities that have the potential to efficiently reprocess them. Due to uncertainties in supply, quality, and reprocessing times of used products, the cost-benefit function in the literature that selects the most economical product to reprocess from a set of used products is not appropriate for direct adoption. Moreover, due to the same uncertainties, any traditional forward supply chain approach to identify potential manufacturing facilities cannot be employed to identify potential recovery facilities. This paper proposes a three-phase fuzzy logic approach, taking the above uncertainties into account, to design a reverse supply chain network. Application of the approach is detailed through an illustrative example in each phase.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"15 1","pages":"72-82"},"PeriodicalIF":0.0,"publicationDate":"2008-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89955482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-07DOI: 10.1109/TEPM.2007.914220
R. E. Powell, I. C. Ume
In this paper, a warpage measurement system to simulate forced convective reflow is discussed. A warpage measurement system that can simulate convective reflow enables the real-time monitoring of printed wiring boards (PWBs), PWB assemblies (PWBAs), and chip package warpage during the reflow process. This paper will describe the two major parts of the warpage measurement system: the optical measurement part which utilizes the projection Moire method and advanced image processing, as well as the laboratory oven which is used to simulate forced convective reflow. This is the first system that allows PWB/PWBA/chip package warpage to be measured during a simulated convective reflow process. Also, this is the first system that employs automatic image segmentation to separately extract the warpage of the PWB and electronic components from the same measurement. The results will show that when compared to infrared heating which was previously used in this research area, convective heating minimizes thermal gradients on the PWB/PWBA sample. Thermal gradients on the PWB/PWBA sample have the inadvertent effect of inducing warpage into the sample and will interfere with the warpage measurement result. In the first design iteration presented in this paper, the system can simulate low ramp rate industrial convective reflow profiles and simultaneously measure the warpage of PWBAs. A computational fluid dynamics (CFD) model of the system was developed to determine how to increase the system's heating rate. The CFD model was used to perform a design of simulations (DOS) and regression analysis. The validated regression results will be used to predict oven design parameters to enable the next iteration of the convective system to simulate high ramp rate convective reflow profiles. This paper will show that the presented system is a powerful tool for measuring the warpage of PWBs, PWBAs, and chip packages.
{"title":"Development of Warpage Measurement System to Simulate Convective Solder Reflow Process","authors":"R. E. Powell, I. C. Ume","doi":"10.1109/TEPM.2007.914220","DOIUrl":"https://doi.org/10.1109/TEPM.2007.914220","url":null,"abstract":"In this paper, a warpage measurement system to simulate forced convective reflow is discussed. A warpage measurement system that can simulate convective reflow enables the real-time monitoring of printed wiring boards (PWBs), PWB assemblies (PWBAs), and chip package warpage during the reflow process. This paper will describe the two major parts of the warpage measurement system: the optical measurement part which utilizes the projection Moire method and advanced image processing, as well as the laboratory oven which is used to simulate forced convective reflow. This is the first system that allows PWB/PWBA/chip package warpage to be measured during a simulated convective reflow process. Also, this is the first system that employs automatic image segmentation to separately extract the warpage of the PWB and electronic components from the same measurement. The results will show that when compared to infrared heating which was previously used in this research area, convective heating minimizes thermal gradients on the PWB/PWBA sample. Thermal gradients on the PWB/PWBA sample have the inadvertent effect of inducing warpage into the sample and will interfere with the warpage measurement result. In the first design iteration presented in this paper, the system can simulate low ramp rate industrial convective reflow profiles and simultaneously measure the warpage of PWBAs. A computational fluid dynamics (CFD) model of the system was developed to determine how to increase the system's heating rate. The CFD model was used to perform a design of simulations (DOS) and regression analysis. The validated regression results will be used to predict oven design parameters to enable the next iteration of the convective system to simulate high ramp rate convective reflow profiles. This paper will show that the presented system is a powerful tool for measuring the warpage of PWBs, PWBAs, and chip packages.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"25 1","pages":"83-90"},"PeriodicalIF":0.0,"publicationDate":"2008-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83252548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-07DOI: 10.1109/TEPM.2007.914209
Jun Cheng, C. Chung, E. Lam, Kenneth S. M. Fung, Fan Wang, W. Leung
Advanced electronic manufacturing requires the 3-D inspection of very small surfaces like the solder bumps on wafers for direct die-to-die bonding. Yet the microscopic size and highly specular and textureless nature of the surfaces make the task difficult. It is also demanded that the size of the entire inspection system be small so as to minimize restraint on the operation of the various moving parts involved in the manufacturing process. In this paper, we describe a new 3-D reconstruction mechanism for the task. The mechanism is based upon the well-known concept of structured-light projection, but adapted to a new configuration that owns a particularly small system size and operates in a different manner. Unlike the traditional mechanisms which involve an array of light sources that occupy a rather extended physical space, the proposed mechanism consists of only a single light source plus a binary grating for projecting binary pattern. To allow the projection at each position of the inspected surface to vary and form distinct binary code, the binary grating is shifted in space. In every shift, a separate image of the illuminated surface is taken. With the use of pattern projection, and of discrete coding instead of analog coding in the projection, issues like texture-absence, image saturation, and image noise of the inspected surfaces are much lessened. Experimental results on a variety of objects are presented to illustrate the effectiveness of this mechanism.
{"title":"Structured-Light Based Sensing Using a Single Fixed Fringe Grating: Fringe Boundary Detection and 3-D Reconstruction","authors":"Jun Cheng, C. Chung, E. Lam, Kenneth S. M. Fung, Fan Wang, W. Leung","doi":"10.1109/TEPM.2007.914209","DOIUrl":"https://doi.org/10.1109/TEPM.2007.914209","url":null,"abstract":"Advanced electronic manufacturing requires the 3-D inspection of very small surfaces like the solder bumps on wafers for direct die-to-die bonding. Yet the microscopic size and highly specular and textureless nature of the surfaces make the task difficult. It is also demanded that the size of the entire inspection system be small so as to minimize restraint on the operation of the various moving parts involved in the manufacturing process. In this paper, we describe a new 3-D reconstruction mechanism for the task. The mechanism is based upon the well-known concept of structured-light projection, but adapted to a new configuration that owns a particularly small system size and operates in a different manner. Unlike the traditional mechanisms which involve an array of light sources that occupy a rather extended physical space, the proposed mechanism consists of only a single light source plus a binary grating for projecting binary pattern. To allow the projection at each position of the inspected surface to vary and form distinct binary code, the binary grating is shifted in space. In every shift, a separate image of the illuminated surface is taken. With the use of pattern projection, and of discrete coding instead of analog coding in the projection, issues like texture-absence, image saturation, and image noise of the inspected surfaces are much lessened. Experimental results on a variety of objects are presented to illustrate the effectiveness of this mechanism.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"31 1","pages":"19-31"},"PeriodicalIF":0.0,"publicationDate":"2008-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72949269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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