Pub Date : 2009-08-28DOI: 10.1109/TEPM.2009.2027894
Kiwon Lee, H. Kim, M. Yim, K. Paik
In this paper, a novel anisotropic conductive film (ACF) flip chip bonding method using ultrasonic vibration for flip chip interconnection is demonstrated. The curing and bonding behaviors of ACFs by ultrasonic vibration were investigated using a 40-kHz ultrasonic bonder with longitudinal vibration. In situ temperature of the ACF layer during ultrasonic (U/S) bonding was measured to investigate the effects of substrate materials and substrate temperature. Curing of the ACFs by ultrasonic vibration was investigated by dynamic scanning calorimetry (DSC) analysis in comparison with isothermal curing. Die adhesion strength of U/S-bonded specimens was compared with that of thermo-compression (T/C) bonded specimens. The temperature of the ACF layer during U/S bonding was significantly affected by the type of substrate materials rather than by the substrate heating temperature. With room the temperature U/S bonding process, the temperature of the ACF layer increased up to 300degC within 2 s on FR-4 substrates and 250degC within 4 s on glass substrates. ACFs were fully cured within 3 s by ultrasonic vibration, because the ACF temperature exceeded 300degC within 3 s. Die adhesion strengths of U/S-bonded specimens were as high as those of T/C bonded specimens both on FR-4 and glass substrates. In summary, U/S bonding of ACF significantly reduces the ACF bonding times to several seconds, and also makes bonding possible at room temperature compared with T/C bonding which requires tens of seconds for bonding time and a bonding temperature of more than 180degC.
{"title":"Ultrasonic Bonding Using Anisotropic Conductive Films (ACFs) for Flip Chip Interconnection","authors":"Kiwon Lee, H. Kim, M. Yim, K. Paik","doi":"10.1109/TEPM.2009.2027894","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2027894","url":null,"abstract":"In this paper, a novel anisotropic conductive film (ACF) flip chip bonding method using ultrasonic vibration for flip chip interconnection is demonstrated. The curing and bonding behaviors of ACFs by ultrasonic vibration were investigated using a 40-kHz ultrasonic bonder with longitudinal vibration. In situ temperature of the ACF layer during ultrasonic (U/S) bonding was measured to investigate the effects of substrate materials and substrate temperature. Curing of the ACFs by ultrasonic vibration was investigated by dynamic scanning calorimetry (DSC) analysis in comparison with isothermal curing. Die adhesion strength of U/S-bonded specimens was compared with that of thermo-compression (T/C) bonded specimens. The temperature of the ACF layer during U/S bonding was significantly affected by the type of substrate materials rather than by the substrate heating temperature. With room the temperature U/S bonding process, the temperature of the ACF layer increased up to 300degC within 2 s on FR-4 substrates and 250degC within 4 s on glass substrates. ACFs were fully cured within 3 s by ultrasonic vibration, because the ACF temperature exceeded 300degC within 3 s. Die adhesion strengths of U/S-bonded specimens were as high as those of T/C bonded specimens both on FR-4 and glass substrates. In summary, U/S bonding of ACF significantly reduces the ACF bonding times to several seconds, and also makes bonding possible at room temperature compared with T/C bonding which requires tens of seconds for bonding time and a bonding temperature of more than 180degC.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"294 1","pages":"241-247"},"PeriodicalIF":0.0,"publicationDate":"2009-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73479700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-08-28DOI: 10.1109/TEPM.2009.2028880
Tan Zhang, Z. Hou, R.W. Johnson, L. Del Castillo, A. Moussessian, R. Greenwell, B. Blalock
Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.
{"title":"Flexible Electronics: Thin Silicon Die on Flexible Substrates","authors":"Tan Zhang, Z. Hou, R.W. Johnson, L. Del Castillo, A. Moussessian, R. Greenwell, B. Blalock","doi":"10.1109/TEPM.2009.2028880","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2028880","url":null,"abstract":"Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"38 1","pages":"291-300"},"PeriodicalIF":0.0,"publicationDate":"2009-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81973398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-08-07DOI: 10.1109/TEPM.2009.2022541
S. Iyer, K. Srihari
Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The complex nature of stacked chip-scale package (CSP) components coupled with a lead-free process presents unique rework challenges that needed to be studied and addressed. Reworking a CSP is complicated as the solder joints are hidden underneath the component. The process window available for the lead-free rework process is very narrow. There are number of other critical factors, which complicate and affect the repeatability of the rework process. The complications only increase with the use of stacked CSP devices. The rework of package stacked CSP components, which are complex in nature, is a daunting task. The key issues and observations with regard to the issues and challenges associated with the lead-free rework of mirror-imaged package stacked CSP components has been presented in this paper. In addition, the paper also provides a recipe for reliably reworking these packages.
{"title":"Reliable Lead-Free Rework Process for Stacked CSP Components","authors":"S. Iyer, K. Srihari","doi":"10.1109/TEPM.2009.2022541","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2022541","url":null,"abstract":"Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The complex nature of stacked chip-scale package (CSP) components coupled with a lead-free process presents unique rework challenges that needed to be studied and addressed. Reworking a CSP is complicated as the solder joints are hidden underneath the component. The process window available for the lead-free rework process is very narrow. There are number of other critical factors, which complicate and affect the repeatability of the rework process. The complications only increase with the use of stacked CSP devices. The rework of package stacked CSP components, which are complex in nature, is a daunting task. The key issues and observations with regard to the issues and challenges associated with the lead-free rework of mirror-imaged package stacked CSP components has been presented in this paper. In addition, the paper also provides a recipe for reliably reworking these packages.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"30 1","pages":"214-220"},"PeriodicalIF":0.0,"publicationDate":"2009-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88938458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-10DOI: 10.1109/TEPM.2009.2022544
X. Qian, Hongchao Zhang
Nowadays, more and more manufacturing enterprises are working hard to improve the environmental performance of their products. Pollution may be generated through the life cycle of a product. To maximally improve a product's overall environmental performance and reduce potential environmental impacts, Design for the Environment can be used as early as the design stage for the product. For electromechanical products, modular design is a widely used design method. While traditional modularity analysis pays little attention to environmental factors, this research aims at including comprehensive environmentally conscious criteria into modularity analysis. This paper presents a semi-quantitative environmentally conscious modular analysis model in order to reduce pollution. Eight criteria are identified to capture most of potential environmental impacts of modular products, some of which are fuzzy criteria. Fuzzy Analytic Hierarchy Process is used to rank these environmental criteria, and fuzzy numbers are used to map some uncertain judgments of decision makers with crisp numbers. Structure of a product is represented as a fuzzy graph. The proposed modularity analysis includes similarity analysis and independence analysis. In the end, an example is given to illustrate the developed methodology.
{"title":"Design for Environment: An Environmentally Conscious Analysis Model for Modular Design","authors":"X. Qian, Hongchao Zhang","doi":"10.1109/TEPM.2009.2022544","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2022544","url":null,"abstract":"Nowadays, more and more manufacturing enterprises are working hard to improve the environmental performance of their products. Pollution may be generated through the life cycle of a product. To maximally improve a product's overall environmental performance and reduce potential environmental impacts, Design for the Environment can be used as early as the design stage for the product. For electromechanical products, modular design is a widely used design method. While traditional modularity analysis pays little attention to environmental factors, this research aims at including comprehensive environmentally conscious criteria into modularity analysis. This paper presents a semi-quantitative environmentally conscious modular analysis model in order to reduce pollution. Eight criteria are identified to capture most of potential environmental impacts of modular products, some of which are fuzzy criteria. Fuzzy Analytic Hierarchy Process is used to rank these environmental criteria, and fuzzy numbers are used to map some uncertain judgments of decision makers with crisp numbers. Structure of a product is represented as a fuzzy graph. The proposed modularity analysis includes similarity analysis and independence analysis. In the end, an example is given to illustrate the developed methodology.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"16 1","pages":"164-175"},"PeriodicalIF":0.0,"publicationDate":"2009-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81806454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/TEPM.2009.2022270
W. Pearn, Y. Tai, J. Lee
In the semiconductor industry, to enhance customer satisfactions and ability of quick responses, the development of cycle time estimation model is very important. Cycle time estimation is an essential planning basis, which has many applications, especially on the analyses of performance indexes, capacity planning, and the assignments of due dates. In this paper, we provide a statistical approach for cycle time estimation in semiconductor plastic ball grid array (PBGA) packaging factories. Due to today's fierce competitive environments in the semiconductor industry, planners involved in PBGA packaging factories need an approach to obtain estimated cycle times with different confidence to ensure the due date assignments more accurately. Therefore, upper confidence bounds of estimated cycle times at various confidence coefficients are also presented in this paper. We demonstrate the applicability of the proposed cycle time estimation model incorporating the upper confidence bounds by presenting a real-world example taken from a PBGA packaging shop floor in a semiconductor packaging factory located in the Science-Based Industrial Park in Hsinchu, Taiwan.
{"title":"Statistical Approach for Cycle Time Estimation in Semiconductor Packaging Factories","authors":"W. Pearn, Y. Tai, J. Lee","doi":"10.1109/TEPM.2009.2022270","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2022270","url":null,"abstract":"In the semiconductor industry, to enhance customer satisfactions and ability of quick responses, the development of cycle time estimation model is very important. Cycle time estimation is an essential planning basis, which has many applications, especially on the analyses of performance indexes, capacity planning, and the assignments of due dates. In this paper, we provide a statistical approach for cycle time estimation in semiconductor plastic ball grid array (PBGA) packaging factories. Due to today's fierce competitive environments in the semiconductor industry, planners involved in PBGA packaging factories need an approach to obtain estimated cycle times with different confidence to ensure the due date assignments more accurately. Therefore, upper confidence bounds of estimated cycle times at various confidence coefficients are also presented in this paper. We demonstrate the applicability of the proposed cycle time estimation model incorporating the upper confidence bounds by presenting a real-world example taken from a PBGA packaging shop floor in a semiconductor packaging factory located in the Science-Based Industrial Park in Hsinchu, Taiwan.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"9 1","pages":"198-205"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88465225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-23DOI: 10.1109/TEPM.2009.2017773
A. Majid, D. Keezer
This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a plusmn 18-ps timing accuracy. The generated signals exhibit low jitter ( ~ 35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.
{"title":"A 5-Gbps Test System for Wafer-Level Packaged Devices","authors":"A. Majid, D. Keezer","doi":"10.1109/TEPM.2009.2017773","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2017773","url":null,"abstract":"This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a plusmn 18-ps timing accuracy. The generated signals exhibit low jitter ( ~ 35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"255 1","pages":"144-151"},"PeriodicalIF":0.0,"publicationDate":"2009-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89478243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-16DOI: 10.1109/TEPM.2009.2020742
P. Khuntontong, T. Blaser, W. Schomburg
Ultrasonic hot embossing allows fabrication of metal patterns onto a polymer film with a low cost and rapid process. A polymer layer with a thin metal film on top is welded onto the polymer substrate where there are protruding micro structures on the tool. Edges around the protruding structures cut the metal layer and ensure electrical insulation. The entire process performs in a few seconds. The non-welded areas are mechanically removed after this process. An antenna of a radio frequency identification device (RFID) and a flexible membrane keyboard were fabricated by embossing 10- mum-thick conductive paths from an aluminum foil onto polypropylene films, 150 and 250 mum in thickness. Antenna circuits have been proven to show the expected resonance frequencies and the keyboard was successfully employed as an input device for a PC.
{"title":"Fabrication of Molded Interconnection Devices by Ultrasonic Hot Embossing on Thin Polymer Films","authors":"P. Khuntontong, T. Blaser, W. Schomburg","doi":"10.1109/TEPM.2009.2020742","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2020742","url":null,"abstract":"Ultrasonic hot embossing allows fabrication of metal patterns onto a polymer film with a low cost and rapid process. A polymer layer with a thin metal film on top is welded onto the polymer substrate where there are protruding micro structures on the tool. Edges around the protruding structures cut the metal layer and ensure electrical insulation. The entire process performs in a few seconds. The non-welded areas are mechanically removed after this process. An antenna of a radio frequency identification device (RFID) and a flexible membrane keyboard were fabricated by embossing 10- mum-thick conductive paths from an aluminum foil onto polypropylene films, 150 and 250 mum in thickness. Antenna circuits have been proven to show the expected resonance frequencies and the keyboard was successfully employed as an input device for a PC.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"18 1","pages":"152-156"},"PeriodicalIF":0.0,"publicationDate":"2009-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85147448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-02DOI: 10.1109/TEPM.2009.2019340
S. Chung, Y. Tai, W. Pearn
Polyimide printing (PI) is an important process operation but also often the cause of bottlenecks in capital-intensive cell assembly factories. Therefore, the development of an effective scheduling method to maximize throughput in this PI process is essential and difficult. In the polyimide printing scheduling problem (PISP), jobs are given weights and clustered by their product types, which must be processed on identical parallel PI machines. The setup times for two consecutive jobs between different product types in the PI machines are sequence-dependent. In this paper, the PISP is formulated as a mixed integer linear programming model. The PISP is also transformed into a multiple tour maximum collection problem (MTMCP), a well-known network problem which has been investigated extensively. Based on this transformation, one can therefore solve the PISP near-optimally using the efficient algorithm.
聚酰亚胺印刷(PI)是一个重要的工艺操作，但往往是造成瓶颈的资本密集型电池组装工厂。因此，开发一种有效的调度方法，以最大限度地提高该PI过程的吞吐量是必要的和困难的。在聚酰亚胺印刷调度问题(PISP)中，作业被赋予权重并按其产品类型聚类，这些作业必须在相同的并行PI机器上加工。PI机器中不同产品类型之间的两个连续作业的设置时间是顺序相关的。本文将PISP表述为一个混合整数线性规划模型。PISP也被转化为一个被广泛研究的著名网络问题MTMCP (multiple tour maximum collection problem)。基于这种转换，我们可以使用高效的算法来求解PISP问题。
{"title":"An Effective Scheduling Approach for Maximizing Polyimide Printing Weighted Throughput in Cell Assembly Factories","authors":"S. Chung, Y. Tai, W. Pearn","doi":"10.1109/TEPM.2009.2019340","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2019340","url":null,"abstract":"Polyimide printing (PI) is an important process operation but also often the cause of bottlenecks in capital-intensive cell assembly factories. Therefore, the development of an effective scheduling method to maximize throughput in this PI process is essential and difficult. In the polyimide printing scheduling problem (PISP), jobs are given weights and clustered by their product types, which must be processed on identical parallel PI machines. The setup times for two consecutive jobs between different product types in the PI machines are sequence-dependent. In this paper, the PISP is formulated as a mixed integer linear programming model. The PISP is also transformed into a multiple tour maximum collection problem (MTMCP), a well-known network problem which has been investigated extensively. Based on this transformation, one can therefore solve the PISP near-optimally using the efficient algorithm.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"18 1","pages":"185-197"},"PeriodicalIF":0.0,"publicationDate":"2009-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76606009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-02DOI: 10.1109/TEPM.2009.2021259
G. Izuta, T. Tanabe, K. Suganuma
In lead-free soldering on printed circuit boards (PCBs), the dissolution and disappearance of PCB copper electrodes in solder bath has been a problem for the dip soldering method, such as wave soldering, in which PCBs are dipped in molten solder. In the former report, it has been estimated the influence of solder composition, temperature, and flowing velocity on the dissolution of copper electrodes by the experiment of the dip soldering process and clarified the dissolution rate for Sn-3.0Ag-xCu alloys, which is defined by solder temperature and copper concentration. Based on above study, the simplified measuring method of copper concentration in the solder bath has been developed, which uses the dissolution of wedge-shaped copper pattern formed on FR-4 PCB. As a result of the experiment on dipping the PCB in solder of Sn-3.0Ag-xCu (x = 0.5, 0.9, 1.2 and 1.5) alloys, it has been confirmed that the method enables the measuring copper concentration in the solder bath easily.
{"title":"Simplified Measuring Method of Copper Concentration in Solder Bath Utilizing Copper Dissolution","authors":"G. Izuta, T. Tanabe, K. Suganuma","doi":"10.1109/TEPM.2009.2021259","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2021259","url":null,"abstract":"In lead-free soldering on printed circuit boards (PCBs), the dissolution and disappearance of PCB copper electrodes in solder bath has been a problem for the dip soldering method, such as wave soldering, in which PCBs are dipped in molten solder. In the former report, it has been estimated the influence of solder composition, temperature, and flowing velocity on the dissolution of copper electrodes by the experiment of the dip soldering process and clarified the dissolution rate for Sn-3.0Ag-xCu alloys, which is defined by solder temperature and copper concentration. Based on above study, the simplified measuring method of copper concentration in the solder bath has been developed, which uses the dissolution of wedge-shaped copper pattern formed on FR-4 PCB. As a result of the experiment on dipping the PCB in solder of Sn-3.0Ag-xCu (x = 0.5, 0.9, 1.2 and 1.5) alloys, it has been confirmed that the method enables the measuring copper concentration in the solder bath easily.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"72 1","pages":"138-143"},"PeriodicalIF":0.0,"publicationDate":"2009-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86265123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-02DOI: 10.1109/TEPM.2009.2019123
A. Shah, M. Mayer, Y.N. Zhou, S. Hong, J. Moon
Thermosonic ball bonding processes on test chips with Al metallized bonding pads are optimized with one Au and two Cu wire types, all 25 mum diameter, obtaining average shear strengths of more than 120 MPa. The process temperature is ~110degC. Ball bonds made with Cu wire show at least 15% higher shear strength than those made with Au wire. The estimated maximum shear strength cpk value determined for Cu ball bonding (cpk = 3.7 plusmn 1.2) is almost 1.5 times as large as that of the Au ball bonding process (cpk = 2.3 plusmn 0.9), where LSL is 65.2 MPa. However, the ultrasound level required for Cu is approximately 1.3 times than that required for Au. Consequently, about 30% higher ultrasonic forces induced to the bonding pad are measured using integrated real-time microsensors. The accompanying higher stresses increase the risk of under-pad damage. One way to reduce ultrasonic bonding stresses is by choosing the softer of the two Cu wire types, resulting in a measured ultrasonic force reduction of about 5%. A second way is to reduce the ultrasound level. While this causes the average shear strength to fall by 15%, the ultrasonic force falls by 9%. The cpk value does not change significantly, suggesting that a successful Cu ball bonding operation can be run with about 0.9 times the conventionally optimized ultrasound level. The process adjusted in this way reduces the extra stress observed with Cu wire compared to that observed with Au wire by 42%.
{"title":"Low-Stress Thermosonic Copper Ball Bonding","authors":"A. Shah, M. Mayer, Y.N. Zhou, S. Hong, J. Moon","doi":"10.1109/TEPM.2009.2019123","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2019123","url":null,"abstract":"Thermosonic ball bonding processes on test chips with Al metallized bonding pads are optimized with one Au and two Cu wire types, all 25 mum diameter, obtaining average shear strengths of more than 120 MPa. The process temperature is ~110degC. Ball bonds made with Cu wire show at least 15% higher shear strength than those made with Au wire. The estimated maximum shear strength cpk value determined for Cu ball bonding (cpk = 3.7 plusmn 1.2) is almost 1.5 times as large as that of the Au ball bonding process (cpk = 2.3 plusmn 0.9), where LSL is 65.2 MPa. However, the ultrasound level required for Cu is approximately 1.3 times than that required for Au. Consequently, about 30% higher ultrasonic forces induced to the bonding pad are measured using integrated real-time microsensors. The accompanying higher stresses increase the risk of under-pad damage. One way to reduce ultrasonic bonding stresses is by choosing the softer of the two Cu wire types, resulting in a measured ultrasonic force reduction of about 5%. A second way is to reduce the ultrasound level. While this causes the average shear strength to fall by 15%, the ultrasonic force falls by 9%. The cpk value does not change significantly, suggesting that a successful Cu ball bonding operation can be run with about 0.9 times the conventionally optimized ultrasound level. The process adjusted in this way reduces the extra stress observed with Cu wire compared to that observed with Au wire by 42%.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"64 1","pages":"176-184"},"PeriodicalIF":0.0,"publicationDate":"2009-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81482670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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