Pub Date : 2009-05-29DOI: 10.1109/TEPM.2009.2021766
Yuhan Cao, Wenguo Ning, L. Luo
In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a ldquoY-shapedrdquo through wafer interconnection structure to shorten the TSV in order to reduce cost. Ansoft HFSSTM 3-D electromagnetic simulator is used to assess the transition properties of signal with frequency of the new interconnection structure. Sn solder bonding is utilized to achieve simultaneous TSV connection and cavity hermetic sealing. Average shear strength of 19.5 Mpa and excellent leak rate of around 1.9 times 10-9 atm cc/s have been achieved, which meet the requirements of MIL-STD-883E. Kevin structure is also fabricated to measure the resistance of the metallized TSV, the resistance of the ldquoY-shapedrdquo through wafer interconnection and the contact resistance of the Cu/Sn IMC bond joint.
{"title":"Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device","authors":"Yuhan Cao, Wenguo Ning, L. Luo","doi":"10.1109/TEPM.2009.2021766","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2021766","url":null,"abstract":"In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a ldquoY-shapedrdquo through wafer interconnection structure to shorten the TSV in order to reduce cost. Ansoft HFSSTM 3-D electromagnetic simulator is used to assess the transition properties of signal with frequency of the new interconnection structure. Sn solder bonding is utilized to achieve simultaneous TSV connection and cavity hermetic sealing. Average shear strength of 19.5 Mpa and excellent leak rate of around 1.9 times 10-9 atm cc/s have been achieved, which meet the requirements of MIL-STD-883E. Kevin structure is also fabricated to measure the resistance of the metallized TSV, the resistance of the ldquoY-shapedrdquo through wafer interconnection and the contact resistance of the Cu/Sn IMC bond joint.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"130 1","pages":"125-132"},"PeriodicalIF":0.0,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73893350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-29DOI: 10.1109/TEPM.2009.2020515
X.B. Chen, M. G. Li, N. Cao
In the contact dispensing process, the contact of the fluid with the target board is essentially needed in order to transfer a certain volume of fluid to the board. Due to the action of surface tension, part of the fluid extruded from the needle hangs on the needle after the process, and this causes the difference between the fluid volume extruded and the one transferred to the board. This difference is usually ignored in the literature, yet is critical to the precise process control. In this paper, a model to represent the difference is developed based on the Young-Laplace capillarity equation as well as the boundary conditions established for this particular problem. Experiments and simulations were carried out to verify the model effectiveness as well as to investigate the influence of the fluid volume extruded from the needle, the needle size, and the initial height of the needle on the fluid volume transferred in the contact dispensing process.
{"title":"Modeling of the Fluid Volume Transferred in Contact Dispensing Processes","authors":"X.B. Chen, M. G. Li, N. Cao","doi":"10.1109/TEPM.2009.2020515","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2020515","url":null,"abstract":"In the contact dispensing process, the contact of the fluid with the target board is essentially needed in order to transfer a certain volume of fluid to the board. Due to the action of surface tension, part of the fluid extruded from the needle hangs on the needle after the process, and this causes the difference between the fluid volume extruded and the one transferred to the board. This difference is usually ignored in the literature, yet is critical to the precise process control. In this paper, a model to represent the difference is developed based on the Young-Laplace capillarity equation as well as the boundary conditions established for this particular problem. Experiments and simulations were carried out to verify the model effectiveness as well as to investigate the influence of the fluid volume extruded from the needle, the needle size, and the initial height of the needle on the fluid volume transferred in the contact dispensing process.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"1 1","pages":"133-137"},"PeriodicalIF":0.0,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78804446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-29DOI: 10.1109/TEPM.2009.2019338
J. Lee, M. Mayer, Y. Zhou, S. Hong, J. Moon
In conventional wire bonding process optimization, the crescent bond is tested by destructive pulling the loop and measure the pull force (PF) required to break the bond. While this method assures the final quality, it does not necessarily minimize production stoppages which can reduce throughput significantly. Many stoppages are caused by short-tail and tail-lift errors which in turn are caused by reduced tail bond strength. The tail breaking force (TBF) is a measure for tail bond strength. A consistent tail breaking operation is needed for robust Cu wire bond production with little operator assistance required to restart stopped machines. We report the concurrent (simultaneous) optimization of PF and TBF using standard pull testing and a method that directly measures the tail bond strength in-process, respectively. The example process uses standard 25-mum-diameter Cu wire on standard Ag-plated leadframe diepads and wire loops oriented perpendicular to the ultrasonic horn. The optimization consists of (1) finding the factors to obtain a symmetrical bond shape, (2) choosing fixed values for bond time (25 ms) and heater stage temperature (220degC), and (3) adding the new optimization step of maximizing the TBF by iteratively optimizing the impact force (IF), bonding force (BF), and ultrasound (US) parameters. Among these parameters, the US and BF are the most significant. A process window (PW) is defined as the set of US/BF parameter combinations that result in a response being inside a previously defined range. PWs for PF and TBF are determined and compared with each other. There is only a partial overlap of these PWs. To increase the process capability index (cpk) for TBF, it is recommended to first carry out conventional PF optimization followed by a minimization of the bonding force parameter to the lowest value still fulfilling the PF cpk requirement.
{"title":"Concurrent Optimization of Crescent Bond Pull Force and Tail Breaking Force in a Thermosonic Cu Wire Bonding Process","authors":"J. Lee, M. Mayer, Y. Zhou, S. Hong, J. Moon","doi":"10.1109/TEPM.2009.2019338","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2019338","url":null,"abstract":"In conventional wire bonding process optimization, the crescent bond is tested by destructive pulling the loop and measure the pull force (PF) required to break the bond. While this method assures the final quality, it does not necessarily minimize production stoppages which can reduce throughput significantly. Many stoppages are caused by short-tail and tail-lift errors which in turn are caused by reduced tail bond strength. The tail breaking force (TBF) is a measure for tail bond strength. A consistent tail breaking operation is needed for robust Cu wire bond production with little operator assistance required to restart stopped machines. We report the concurrent (simultaneous) optimization of PF and TBF using standard pull testing and a method that directly measures the tail bond strength in-process, respectively. The example process uses standard 25-mum-diameter Cu wire on standard Ag-plated leadframe diepads and wire loops oriented perpendicular to the ultrasonic horn. The optimization consists of (1) finding the factors to obtain a symmetrical bond shape, (2) choosing fixed values for bond time (25 ms) and heater stage temperature (220degC), and (3) adding the new optimization step of maximizing the TBF by iteratively optimizing the impact force (IF), bonding force (BF), and ultrasound (US) parameters. Among these parameters, the US and BF are the most significant. A process window (PW) is defined as the set of US/BF parameter combinations that result in a response being inside a previously defined range. PWs for PF and TBF are determined and compared with each other. There is only a partial overlap of these PWs. To increase the process capability index (cpk) for TBF, it is recommended to first carry out conventional PF optimization followed by a minimization of the bonding force parameter to the lowest value still fulfilling the PF cpk requirement.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"96 1","pages":"157-163"},"PeriodicalIF":0.0,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81168331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-03DOI: 10.1109/TEPM.2009.2015768
H.H. Fellows, C. Mastrangelo, K. P. White
Yield analysis is an important activity in the assessment and control of semiconductor fabrication processes. Tests of spatial randomness provide a means of enhancing yield analysis by considering the patterns of good and defective chips on the wafer. These patterns can be related to the likely sources of defects during production. This paper compares two approaches for determining spatial randomness based on join-count statistics. The first assumes that a random distribution of defects can be modeled as a spatially homogenous Bernoulli process (SHBP). The second uses a Markov random field (MRF) as the null distribution. While both methods are shown to have good performance, the MRF outperforms the SHBP on both clustered and random defect data.
{"title":"An Empirical Comparison of Spatial Randomness Models for Yield Analysis","authors":"H.H. Fellows, C. Mastrangelo, K. P. White","doi":"10.1109/TEPM.2009.2015768","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2015768","url":null,"abstract":"Yield analysis is an important activity in the assessment and control of semiconductor fabrication processes. Tests of spatial randomness provide a means of enhancing yield analysis by considering the patterns of good and defective chips on the wafer. These patterns can be related to the likely sources of defects during production. This paper compares two approaches for determining spatial randomness based on join-count statistics. The first assumes that a random distribution of defects can be modeled as a spatially homogenous Bernoulli process (SHBP). The second uses a Markov random field (MRF) as the null distribution. While both methods are shown to have good performance, the MRF outperforms the SHBP on both clustered and random defect data.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"60 1","pages":"115-120"},"PeriodicalIF":0.0,"publicationDate":"2009-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78207583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-31DOI: 10.1109/TEPM.2009.2015288
Kyung-Woon Jang, K. Paik
In this paper, the effects of anisotropic conductive film (ACF) viscosity on ACF fillet formation and, ultimately, on the pressure cooker test (PCT) reliability of ACF flip chip assemblies were investigated. The ACF viscosity was controlled by varying the molecular weight of the epoxy materials. It was found that the ACF viscosity increased as the increase of molecular weight of the epoxy materials. However, there was little variation of the thermomechanical properties among the evaluated ACFs with different viscosites. Also, the results showed that the ACFs have no differences in moisture absorption rate, die adhesion strength, and degree-of-cure. In scanning electron microscopy images, the lower ACF viscosity resulted in the smoother ACF fillet shape and the higher fillet height. From the results of PCT, the ACF flip chip assembly with the smoother fillet shape showed better reliability in terms of contact resistance changes. After 130 h of PCT, the flip chip assembly with lower ACF viscosity also showed a lesser degree of delamination at the ACF/chip interface.
{"title":"Effects of Anisotropic Conductive Film Viscosity on ACF Fillet Formation and Chip-On-Board Packages","authors":"Kyung-Woon Jang, K. Paik","doi":"10.1109/TEPM.2009.2015288","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2015288","url":null,"abstract":"In this paper, the effects of anisotropic conductive film (ACF) viscosity on ACF fillet formation and, ultimately, on the pressure cooker test (PCT) reliability of ACF flip chip assemblies were investigated. The ACF viscosity was controlled by varying the molecular weight of the epoxy materials. It was found that the ACF viscosity increased as the increase of molecular weight of the epoxy materials. However, there was little variation of the thermomechanical properties among the evaluated ACFs with different viscosites. Also, the results showed that the ACFs have no differences in moisture absorption rate, die adhesion strength, and degree-of-cure. In scanning electron microscopy images, the lower ACF viscosity resulted in the smoother ACF fillet shape and the higher fillet height. From the results of PCT, the ACF flip chip assembly with the smoother fillet shape showed better reliability in terms of contact resistance changes. After 130 h of PCT, the flip chip assembly with lower ACF viscosity also showed a lesser degree of delamination at the ACF/chip interface.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"436 1","pages":"74-80"},"PeriodicalIF":0.0,"publicationDate":"2009-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83054714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-27DOI: 10.1109/TEPM.2009.2015592
Sangil Lee, M. Yim, R. Master, C. Wong, D. Baldwin
The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.
{"title":"Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill","authors":"Sangil Lee, M. Yim, R. Master, C. Wong, D. Baldwin","doi":"10.1109/TEPM.2009.2015592","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2015592","url":null,"abstract":"The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"51 1","pages":"106-114"},"PeriodicalIF":0.0,"publicationDate":"2009-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78288163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-27DOI: 10.1109/TEPM.2009.2017514
Y. Liu, T. Luk, S. Irving
This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact model is developed for the probe tip and wafer bond pad. Modeling results have shown that the probe test OT, probe tip shape and tip diameters, contact friction between the probe tip and bond pad, as well as the probe scrub of the probe tip on bond pad are important parameters that impact the failure of interlayer dielectric (ILD) layer under bond pad. Comparison between probe test damage and wire bonding failure shows the degree of damage to both probe test and wire bonding on the same bond pad structures. In addition that, a design of experiment (DOE) probe test with different ILD and metal thickness is carried. The correlation between the modeling and the DOE test is studied. The results show that the modeling solution agrees with the DOE probe test data. Modeling results have further revealed that probe test can induce the local tensile (or bending) first principal stress in ILD layer, which may be a root cause of the ILD failure in probe test.
{"title":"Parameter Modeling for Wafer Probe Test","authors":"Y. Liu, T. Luk, S. Irving","doi":"10.1109/TEPM.2009.2017514","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2017514","url":null,"abstract":"This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact model is developed for the probe tip and wafer bond pad. Modeling results have shown that the probe test OT, probe tip shape and tip diameters, contact friction between the probe tip and bond pad, as well as the probe scrub of the probe tip on bond pad are important parameters that impact the failure of interlayer dielectric (ILD) layer under bond pad. Comparison between probe test damage and wire bonding failure shows the degree of damage to both probe test and wire bonding on the same bond pad structures. In addition that, a design of experiment (DOE) probe test with different ILD and metal thickness is carried. The correlation between the modeling and the DOE test is studied. The results show that the modeling solution agrees with the DOE probe test data. Modeling results have further revealed that probe test can induce the local tensile (or bending) first principal stress in ILD layer, which may be a root cause of the ILD failure in probe test.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"266 ","pages":"81-88"},"PeriodicalIF":0.0,"publicationDate":"2009-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TEPM.2009.2017514","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72435105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-02-10DOI: 10.1109/TEPM.2009.2012865
L. Mats, J. T. Cain, M. Mickle
Packaging of RFID transponders that operate at ultrahigh frequencies (UHF) requires nontraditional materials and innovative methods in order to make a functional, reliable, and inexpensive RFID transponders. Presented is a statistical analysis along with the model as the way to evaluate measured results and provide the quality and process control for the electrical and mechanical performance of the packaging of RFID tags with respect to different manufacturing processes. The power analysis is presented in support of the statistical analysis and the sample size selection.
{"title":"Statistical Analysis of Transponder Packaging in UHF RFID Systems","authors":"L. Mats, J. T. Cain, M. Mickle","doi":"10.1109/TEPM.2009.2012865","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2012865","url":null,"abstract":"Packaging of RFID transponders that operate at ultrahigh frequencies (UHF) requires nontraditional materials and innovative methods in order to make a functional, reliable, and inexpensive RFID transponders. Presented is a statistical analysis along with the model as the way to evaluate measured results and provide the quality and process control for the electrical and mechanical performance of the packaging of RFID tags with respect to different manufacturing processes. The power analysis is presented in support of the statistical analysis and the sample size selection.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"47 1","pages":"97-105"},"PeriodicalIF":0.0,"publicationDate":"2009-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91212743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-02-10DOI: 10.1109/TEPM.2008.2011813
M. Liukkonen, T. Hiltunen, Elina Havia, H. Leinonen, Y. Hiltunen
Multilayer perceptrons (MLPs ) are well-known artificial neural networks (ANNs) that are used in many different applications. In this paper, MLP neural networks were used to predict product quality in a wave soldering research case. The aims were to construct process models and to determine whether the formation of soldering defects could be predicted reliably by using the method. In addition, the scope of the research included demonstrating the prediction performance of the created models. A MLP-based variable selection procedure with a back-propagation algorithm was used to create defect formation models and to find the most important factors affecting the number of detected defects. The process parameters were used as inputs for the MLP network and each defect type in turn as a model output. In conclusion, the results were promising, and the method used showed potential considering the wider use of the data processing procedure in the electronics or any other industry.
{"title":"Modeling of Soldering Quality by Using Artificial Neural Networks","authors":"M. Liukkonen, T. Hiltunen, Elina Havia, H. Leinonen, Y. Hiltunen","doi":"10.1109/TEPM.2008.2011813","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2011813","url":null,"abstract":"Multilayer perceptrons (MLPs ) are well-known artificial neural networks (ANNs) that are used in many different applications. In this paper, MLP neural networks were used to predict product quality in a wave soldering research case. The aims were to construct process models and to determine whether the formation of soldering defects could be predicted reliably by using the method. In addition, the scope of the research included demonstrating the prediction performance of the created models. A MLP-based variable selection procedure with a back-propagation algorithm was used to create defect formation models and to find the most important factors affecting the number of detected defects. The process parameters were used as inputs for the MLP network and each defect type in turn as a model output. In conclusion, the results were promising, and the method used showed potential considering the wider use of the data processing procedure in the electronics or any other industry.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"172 1","pages":"89-96"},"PeriodicalIF":0.0,"publicationDate":"2009-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79463782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-09DOI: 10.1109/TEPM.2008.2005779
A. Lago, C. Peñalver, J. Marcos, J. Doval‐Gandoy, A. Melendez, Ó. López, F. Santiago, F. Freijedo, J. Vilas, J.C. Lorenzo
The geometry of a twisted pair largely determines its electrical characteristics. To improve and refine the value of these characteristics according to preset values, the optimization of the manufacturing processes requires comprehensive knowledge of twisted pair geometry and of how electrical magnitudes are affected by the construction features of the twisted pair. This paper studies the relation between the length of a twisted pair cable and the length of each of the wires that compose the cable, by analyzing concepts such as pitch angle and radius of the helix. In addition, it examines the deformations and irregularities that can occur in the twisted pair during the manufacturing process and their effects on the geometry of the twisted pair. Results showed in this paper are a part of a larger research project carried out in association with the R&D department of a cable manufacturing company, and these results are being applied into the design department of this company.
{"title":"Geometric Analysis and Manufacturing Considerations for Optimizing the Characteristics of a Twisted Pair","authors":"A. Lago, C. Peñalver, J. Marcos, J. Doval‐Gandoy, A. Melendez, Ó. López, F. Santiago, F. Freijedo, J. Vilas, J.C. Lorenzo","doi":"10.1109/TEPM.2008.2005779","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2005779","url":null,"abstract":"The geometry of a twisted pair largely determines its electrical characteristics. To improve and refine the value of these characteristics according to preset values, the optimization of the manufacturing processes requires comprehensive knowledge of twisted pair geometry and of how electrical magnitudes are affected by the construction features of the twisted pair. This paper studies the relation between the length of a twisted pair cable and the length of each of the wires that compose the cable, by analyzing concepts such as pitch angle and radius of the helix. In addition, it examines the deformations and irregularities that can occur in the twisted pair during the manufacturing process and their effects on the geometry of the twisted pair. Results showed in this paper are a part of a larger research project carried out in association with the R&D department of a cable manufacturing company, and these results are being applied into the design department of this company.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":" 47","pages":"22-31"},"PeriodicalIF":0.0,"publicationDate":"2009-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TEPM.2008.2005779","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72379462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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