IET Power Electronics最新文献

This paper investigates the impact of parasitic elements on the performance of switched impedance inverters. This work develops a non-ideal impedance source inverter model, enabling more accurate predictions of voltage gain, current relationships, and overall converter behaviour under practical operating conditions. By quantifying the influence of parasitic components on key parameters such as voltage, current, and component selection, this research provides valuable insights for optimising the design of switched impedance inverters. Furthermore, the reliability modelling highlights the sensitive elements in the operation of the inverter. The analysis examines power transfer characteristics within the inverter bridge, considering both zero and non-zero states, and investigates the impact of switching frequency, output frequency, and duty cycle on the DC-link current. Experimental results validate the findings, demonstrating the practical significance of considering parasitic elements in the design and optimisation of switched impedance inverters. By improving the accuracy of theoretical predictions, this research contributes to reducing experimental iterations, minimising costs, and mitigating the risk of encountering unforeseen issues during the development and implementation of these converters.

Seven-level hybrid-clamped (7L-HC) converters are new and promising candidates for high-power medium-voltage applications. Their configurations can be simplified further by reducing one of the two flying capacitors per phase. However, such simplification significantly reduces the available redundant states, making it hard for dc-link capacitors balancing and operation optimisation. In this article, the optimised operations and a low switching frequency modulation scheme are proposed for S7L-HC converters. Various new switching states are explored to help reduce the switching frequency, facilitate the balance of switching frequency distributions and reduction of the dynamic voltage stress on switches. The proposed modulation based on an improved selective harmonic elimination pulse width modulation (PWM) can achieve voltage balancing for all capacitors under a low switching frequency. Simulation and experimental results verify the proposed operations and modulation scheme.

In the design of high-power converters, significant parameter dispersion among different SiC MOSFET devices can cause substantial current differences during switching when devices are directly paralleled. To address this issue, a method is proposed to suppress transient current imbalance based on gate-source voltage compensation. First, the impact mechanism of threshold voltage differences on transient current imbalance during the switching of parallel SiC MOSFETs is analysed, and the role of gate-source voltage differences in current sharing is explored. The proposed method introduces a gate current extraction structure during the on-state and a current injection structure during the off-state to generate gate-source voltage differences between two devices, thereby eliminating the current differences caused by inconsistent device turn-on sequences. Compensation parameters are determined by analysing the mathematical model of gate-source voltage differences during switching transients. Finally, simulation analysis and experimental tests using LTspice simulation software and a parallel double-pulse test platform demonstrate that the proposed current sharing method significantly improves transient current imbalance between parallel devices.

In existing modulation strategies for active neutral-point-clamped three-level (ANPC-3L) inverters, high-frequency and low-frequency switches are separated, with loss mainly concentrated in some fixed high-frequency operating switches, resulting in uneven loss distribution across switches among bridge arms. To address these issues, a loss-balance optimization modulation strategy is proposed. In this paper, the loss distribution of power switches under different commutation paths is analysed, and a loss-estimation model for switches is established based on the characteristics of power switches to quantify the total losses. Aimed at loss balancing for all power switches, the switching modes (commutation paths) in the modulation process are automatically selected by the proposed strategy, achieving relatively balanced losses among all switches. Experiments are carried out with an 18 kW three-phase ANPC-3L inverter. Compared with existing loss-balance strategies, the proposed strategy shows better loss (temperature) balance performance and almost equal efficiency.

This paper presents an optimisation method for an inserted-shunt integrated planar transformer based on 3D simulation in Ansys Maxwell. The optimisation objective is enhanced efficiency and power density for the transformer. Thermal analysis verifies the optimisation to ensure the transformer's operability under limited temperature conditions when its size is reduced. The optimised integrated transformer is implemented for verification, with the presentation of experimental results, including AC resistance, efficiency, operating waveforms, and thermal imagery. Furthermore, the paper provides insight into the loss distribution of the transformer. The study shows that the optimisation enhances the power density of the inserted-shunt integrated planar transformer by 270% compared to the conventional design. Additionally, the CLLLC converter incorporating the optimised transformer achieves approximately 1.84 percentage points higher efficiency than the conventional design.

Full electric vessels can benefit from hybrid energy storage systems (HESS) that combine two storage technologies of different characteristics in terms of power and energy density. The optimal design of a HESS for a vessel is generally a rather complex multivariable optimization with several degrees of freedom and constraints. Indeed, the optimization should account for the operational characteristics of the storage units, including their progressive aging. Moreover, the sizing of the storage units is tightly linked to the strategy implemented in the energy management system (EMS) for allocating the power needed by the load to the storage units. This paper presents a two-stage Pareto-based design optimization procedure for HESS intended for a full-electric vessel. The methodology first identifies a Pareto front as the set of all the optimal configurations in terms of capacity of the two storage units that fulfil the operational constraints within a large discrete configuration space. These constraints account for capacity degradation and limitations in power and energy. The degrees of freedom in the EMS are included in the configuration space. A second stage identifies the optimal configuration on the Pareto front based on a defined cost function. The approach decouples the analysis of the solutions that can fulfil the operational constraints from the optimization and can be very effective in exploring the effect of several alternative cost functions on the optimal solution. Moreover, the shape of the Pareto front can offer a visual clue to the benefits offered by a hybrid storage compared to a single technology solution and on the optimization margins. The procedure is illustrated with a case of a full electric tugboat highlighting when a HESS can be beneficial and how the optimal design can be facilitated.

In photovoltaic power generation applications, multiple low-voltage PV modules must be boosted and connected in parallel for high power output. However, due to the variability of PV energy input, the parallel DC-DC converter modules often operate under asymmetric conditions, which deteriorates bus voltage ripple and reduces system stability and component lifespan. To address these issues, this paper proposes an optimal phase-shift modulation method with asymmetric phase shifts to effectively suppress the ripples at the point of common coupling of parallel-connected converters. To do so, a model for the output voltage ripple of boost and buck–boost parallel converter is established using the equivalent small parameter method (ESPM) with the optimal phase-shift angle determined by this modulation approach. Furthermore, a triple-loop current-sharing control strategy is implemented to ensure current sharing among the modules, enhancing the overall ripple suppression capability of the proposed modulation technique. Simulation and experimental results indicate that this integrated approach significantly improves the performance and stability of parallel converter systems.

Within control system architectures, the proportional-proportional-delay (PPD) controller is theoretically characterized by enhanced dynamic responsiveness, a streamlined control structure, and reduced computational demands. Nevertheless, this control strategy demonstrates heightened dependence on system model accuracy coupled with compromised robustness, thus imposing significant constraints on its practical deployment in industrial control scenarios. To improve steady-state control performance of the PPD controller against circuit parameters variations, this paper investigates quantity relationships between circuit parameters variations and grid current amplitude changes first, and a dominant factor and some minor factors affecting the grid current are found out successfully. As a result, linear control of the PPD controller against model parameters changes has been proposed based on a linear function. Meanwhile, an integral controller composed has been integrated into the control strategy to eliminate the residual steady-state error of the proposed linear controller. Finally, a combined control structure with both linear and integral controllers has been proposed, and experimental results have been presented to verify the correctness and effectiveness of the combined control.

Finite Control Set Model Predictive Control (FCS-MPC) is widely used in Modular Multilevel Converters (MMC), but it faces challenges such as heavy computational burden and the complexity of designing weighting factors. Unbalanced grid voltage conditions frequently occur, and for grid-connected MMC with passive loads, the stability of the DC bus voltage is crucial. To address these issues, this paper proposes an arm current finite control set model predictive control strategy based on three-phase coupled modeling, along with a compensation mechanism for stabilizing the DC voltage. The proposed method is independent of the number of submodules and does not require weighting factor design, while effectively stabilizing the DC bus voltage without compromising the system's control objectives.

The study proposes an advanced control technique for modular-structured series-resonant converters, unifying pulse-density modulation (PDM) and phase-shift control to mitigate output current amplitude fluctuations. Series-resonant converters, widely utilised for their efficiency in various applications, typically employ PDM to achieve zero-voltage and quasi-zero-current switching, minimising switching losses. However, these converters often encounter challenges with amplitude fluctuations in the output current, particularly during deep current regulation, which can compromise performance and lead to increased electromagnetic interference and overvoltage issues. The presented control strategy combines PDM with phase-shift control, significantly reducing these fluctuations and maintaining higher minimum peak currents. This unified approach ensures greater stability and efficiency in the converter's operation. Detailed experimental validation confirms the theoretical benefits, highlighting the proposed method's superiority over traditional PDM control techniques in achieving stable and efficient converter performance.