Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581563
I. Saha, Ratan Rahul Jeldi, R. Chakraborty
Design, implementation and characterization of Physically Unclonable Functions (PUFs) in silicon have drawn considerable research interest in recent years. However, side-by-side, there are concerns that these PUF circuits, although physically unclonable, might be vulnerable to computational model-building attacks that compromise their security. In this work, we have used ideas from evolutionary computation, specifically genetic programming, to build accurate and compact mathematical models to approximate the response of FPGA-based ring oscillator PUFs (RO-PUFs). Hence, we have demonstrated the feasibility of a computationally simple scheme to model FPGA-based PUFs, and we believe this work will pave the way for similar attempts to attack more sophisticated PUF implementations.
{"title":"Model building attacks on Physically Unclonable Functions using genetic programming","authors":"I. Saha, Ratan Rahul Jeldi, R. Chakraborty","doi":"10.1109/HST.2013.6581563","DOIUrl":"https://doi.org/10.1109/HST.2013.6581563","url":null,"abstract":"Design, implementation and characterization of Physically Unclonable Functions (PUFs) in silicon have drawn considerable research interest in recent years. However, side-by-side, there are concerns that these PUF circuits, although physically unclonable, might be vulnerable to computational model-building attacks that compromise their security. In this work, we have used ideas from evolutionary computation, specifically genetic programming, to build accurate and compact mathematical models to approximate the response of FPGA-based ring oscillator PUFs (RO-PUFs). Hence, we have demonstrated the feasibility of a computationally simple scheme to model FPGA-based PUFs, and we believe this work will pave the way for similar attempts to attack more sophisticated PUF implementations.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"15 1","pages":"41-44"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75220293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581573
Yier Jin, Bo Yang, Y. Makris
We propose a new information assurance model which can dynamically track the information flow in circuit designs and hence protect sensitive data from malicious leakage. Relying on the Coq proof assistant platform, the new model maps register transfer level (RTL) codes written in hardware description languages (HDLs) into structural Coq representatives by assigning all input, output, and internal signal sensitivity levels. The signal sensitivity levels can be dynamically adjusted after each clock cycle based on proposed signal sensitivity transition rules. The development of data secrecy properties and theorem generation functions makes the translation process from security properties to Coq theorems independent of target circuits and, for the first time, makes it possible to construct a property library, facilitating (semi) automation of the proof. The proposed cycle accurate information assurance scheme is successfully demonstrated on cryptographic circuits with various complexities from a small-scale DES encryption core to a state-of-the-art AES encryption design prohibiting the leakage of sensitive information caused by hardware Trojans inserted in RTL codes.
{"title":"Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing","authors":"Yier Jin, Bo Yang, Y. Makris","doi":"10.1109/HST.2013.6581573","DOIUrl":"https://doi.org/10.1109/HST.2013.6581573","url":null,"abstract":"We propose a new information assurance model which can dynamically track the information flow in circuit designs and hence protect sensitive data from malicious leakage. Relying on the Coq proof assistant platform, the new model maps register transfer level (RTL) codes written in hardware description languages (HDLs) into structural Coq representatives by assigning all input, output, and internal signal sensitivity levels. The signal sensitivity levels can be dynamically adjusted after each clock cycle based on proposed signal sensitivity transition rules. The development of data secrecy properties and theorem generation functions makes the translation process from security properties to Coq theorems independent of target circuits and, for the first time, makes it possible to construct a property library, facilitating (semi) automation of the proof. The proposed cycle accurate information assurance scheme is successfully demonstrated on cryptographic circuits with various complexities from a small-scale DES encryption core to a state-of-the-art AES encryption design prohibiting the leakage of sensitive information caused by hardware Trojans inserted in RTL codes.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"127 1","pages":"99-106"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73201849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581577
Mostafa M. I. Taha, P. Schaumont
NIST recently completed the SHA-3 competition with the selection of Keccak as the new standard for crypto-graphic hashing. In this paper, we present a comprehensive Side-Channel Analysis of Keccak, when it is used with a secret key to generate a Message Authentication Code (MAC) (MAC-Keccak). Our analysis covers all the variations of the algorithm. We show that the side-channel resistance of the MAC-Keccak depends on the key-length used, and we derive the optimum key-length as ((n * rate) - 1), where (n ∈ [2 : ∞]) and rate is the Keccak input block size. Finally, the paper demonstrates the feasibility of our side-channel analysis with a practical attack against MAC-Keccak implemented on a 32-bit Microblaze processor.
{"title":"Side-Channel Analysis of MAC-Keccak","authors":"Mostafa M. I. Taha, P. Schaumont","doi":"10.1109/HST.2013.6581577","DOIUrl":"https://doi.org/10.1109/HST.2013.6581577","url":null,"abstract":"NIST recently completed the SHA-3 competition with the selection of Keccak as the new standard for crypto-graphic hashing. In this paper, we present a comprehensive Side-Channel Analysis of Keccak, when it is used with a secret key to generate a Message Authentication Code (MAC) (MAC-Keccak). Our analysis covers all the variations of the algorithm. We show that the side-channel resistance of the MAC-Keccak depends on the key-length used, and we derive the optimum key-length as ((n * rate) - 1), where (n ∈ [2 : ∞]) and rate is the Keccak input block size. Finally, the paper demonstrates the feasibility of our side-channel analysis with a practical attack against MAC-Keccak implemented on a 32-bit Microblaze processor.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"92 9 1","pages":"125-130"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77283730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581569
Obaid Khalid, C. Rolfes, A. Ibing
This paper presents an implementation of trusted boot for embedded systems. While in PCs the trusted computing hardware functionality is spread over CPU, memory controller hub (MCH), IO controller hub (ICH) and Trusted Platform Module (TPM), for embedded systems it is desirable to integrate the whole functionality in one system on chip. Our implementation is a two-processor design with LEON3 open source soft cores (SPARC V8 instruction set), coupled over an AHB interface. One of the processors acts as application processor, the other one as `secure' coprocessor. The application processor is synthesized with a boot ROM as static root of trust for measurement. The `secure' coprocessor runs TPM frmware and enables the application processor to boot and run different software while sealing corresponding keys and other secrets to the respective software identity (computed as hash value). We evaluate the design in a Virtex5 FPGA with respect to different measures like resource consumption, code sizes and start times. The `trusted boot' functionality is realised with a boot time increase of around 25% for a Linux system.
{"title":"On implementing trusted boot for embedded systems","authors":"Obaid Khalid, C. Rolfes, A. Ibing","doi":"10.1109/HST.2013.6581569","DOIUrl":"https://doi.org/10.1109/HST.2013.6581569","url":null,"abstract":"This paper presents an implementation of trusted boot for embedded systems. While in PCs the trusted computing hardware functionality is spread over CPU, memory controller hub (MCH), IO controller hub (ICH) and Trusted Platform Module (TPM), for embedded systems it is desirable to integrate the whole functionality in one system on chip. Our implementation is a two-processor design with LEON3 open source soft cores (SPARC V8 instruction set), coupled over an AHB interface. One of the processors acts as application processor, the other one as `secure' coprocessor. The application processor is synthesized with a boot ROM as static root of trust for measurement. The `secure' coprocessor runs TPM frmware and enables the application processor to boot and run different software while sealing corresponding keys and other secrets to the respective software identity (computed as hash value). We evaluate the design in a Virtex5 FPGA with respect to different measures like resource consumption, code sizes and start times. The `trusted boot' functionality is realised with a boot time increase of around 25% for a Linux system.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"1970 1","pages":"75-80"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91358569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581581
Jim Aarestad, J. Plusquellic, D. Acharyya
Cryptographic and authentication applications in application-specific integrated circuits (ASICs) and FPGAs, as well as codes for the activation of on-chip features, require the use of embedded secret information. The generation of secret bitstrings using physical unclonable functions, or PUFs, provides several distinct advantages over conventional methods, including the elimination of costly non-volatile memory, and the potential to increase the number of random bits available to applications. In this paper, we propose a Hardware-Embedded Delay PUF (HELP) that is designed to leverage path delay variations that occur in the core logic macros of a chip to create random bitstrings. The bitstrings produced by a set of 30 FPGA boards are evaluated with regard to several statistical quality metrics including uniqueness, randomness, and stability. The stability characteristics of the bitstrings are evaluated by subjecting the FPGAs to commercial-level temperature and supply voltage variations. In particular, we evaluate the reproducibility of the bitstrings generated at 0°C, 25°C, and 70°C, and at nominal and ±10% of the supply voltage. An error avoidance scheme is proposed that provides significant improvement against bit-flip errors in the bitstrings.
{"title":"Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF","authors":"Jim Aarestad, J. Plusquellic, D. Acharyya","doi":"10.1109/HST.2013.6581581","DOIUrl":"https://doi.org/10.1109/HST.2013.6581581","url":null,"abstract":"Cryptographic and authentication applications in application-specific integrated circuits (ASICs) and FPGAs, as well as codes for the activation of on-chip features, require the use of embedded secret information. The generation of secret bitstrings using physical unclonable functions, or PUFs, provides several distinct advantages over conventional methods, including the elimination of costly non-volatile memory, and the potential to increase the number of random bits available to applications. In this paper, we propose a Hardware-Embedded Delay PUF (HELP) that is designed to leverage path delay variations that occur in the core logic macros of a chip to create random bitstrings. The bitstrings produced by a set of 30 FPGA boards are evaluated with regard to several statistical quality metrics including uniqueness, randomness, and stability. The stability characteristics of the bitstrings are evaluated by subjecting the FPGAs to commercial-level temperature and supply voltage variations. In particular, we evaluate the reproducibility of the bitstrings generated at 0°C, 25°C, and 70°C, and at nominal and ±10% of the supply voltage. An error avoidance scheme is proposed that provides significant improvement against bit-flip errors in the bitstrings.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"6 1","pages":"151-158"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76042968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581564
K. Xiao, M. Tehranipoor
Hardware Trojans have become a significant threat to government agencies and enterprises that require security and trustworthiness in systems with critical applications. Detecting hardware Trojans is very challenging because of the diversity of Trojans and unpredictable process variations during fabrication. In this paper, we propose a novel technique, called built-in self-authentication (BISA), that can fill unused spaces in a circuit layout by functional filler cells instead of non-functional filler cells. All functional filler cells will be tested by BISA itself and a digital signature would be generated. Any modification on BISA will result in a different signature. Thus, BISA can be used to prevent Trojan insertion or make Trojan insertion extremely difficult. BISA can be applied to any single-module or bottom-up hierarchical design, and we evaluate it on different circuits to demonstrate the effective of this technique.
{"title":"BISA: Built-in self-authentication for preventing hardware Trojan insertion","authors":"K. Xiao, M. Tehranipoor","doi":"10.1109/HST.2013.6581564","DOIUrl":"https://doi.org/10.1109/HST.2013.6581564","url":null,"abstract":"Hardware Trojans have become a significant threat to government agencies and enterprises that require security and trustworthiness in systems with critical applications. Detecting hardware Trojans is very challenging because of the diversity of Trojans and unpredictable process variations during fabrication. In this paper, we propose a novel technique, called built-in self-authentication (BISA), that can fill unused spaces in a circuit layout by functional filler cells instead of non-functional filler cells. All functional filler cells will be tested by BISA itself and a digital signature would be generated. Any modification on BISA will result in a different signature. Thus, BISA can be used to prevent Trojan insertion or make Trojan insertion extremely difficult. BISA can be applied to any single-module or bottom-up hierarchical design, and we evaluate it on different circuits to demonstrate the effective of this technique.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"28 1","pages":"45-50"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79254195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581560
F. Melzani, A. Palomba
This paper gives an assessment of the threats posed by Fault Sensitivity Analysis attacks. We propose an overall discussion of the possibilities in attacking a hardware implementation of AES. The limitations of the current methodology are presented, together with new approaches that allow for more effective attacks. Utilizing gate level simulations, a comparison is performed of the performances of different variations of the attack methodology on different AES implementations. We also introduce the application of template attacks to the Fault Sensitivity Analysis. Results indicate that the use of templates helps to overcome some of the limitations of the original attack.
{"title":"Enhancing fault sensitivity analysis through templates","authors":"F. Melzani, A. Palomba","doi":"10.1109/HST.2013.6581560","DOIUrl":"https://doi.org/10.1109/HST.2013.6581560","url":null,"abstract":"This paper gives an assessment of the threats posed by Fault Sensitivity Analysis attacks. We propose an overall discussion of the possibilities in attacking a hardware implementation of AES. The limitations of the current methodology are presented, together with new approaches that allow for more effective attacks. Utilizing gate level simulations, a comparison is performed of the performances of different variations of the attack methodology on different AES implementations. We also introduce the application of template attacks to the Fault Sensitivity Analysis. Results indicate that the use of templates helps to overcome some of the limitations of the original attack.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"40 1","pages":"25-28"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89505544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581556
Clemens Helfmeier, C. Boit, Dmitry Nedospasov, Jean-Pierre Seifert
As system security demands continue to evolve, Physically Unclonable Functions (PUFs) are a promising solution for secure storage on Integrated Circuits (ICs). SRAM PUFs are among the most popular types of PUFs, since they require no additional circuitry and can be implemented with on-die memories such as caches and data memory that are readily available on both ASICs and FPGAs. This work demonstrates that SRAM PUFs are not well suited as PUFs, as they do not meet several requirements that constitute an ideal PUF. The compact nature of SRAM, standard interconnects and resiliency to environmental effects make SRAM PUFs particularly easy to clone. We consider several ways in which SRAM PUFs can be characterized and demonstrate a Focused Ion Beam circuit edit with which we were able to produce a physical clone of our Proof-of-Concept SRAM PUF implementation. As a result of the circuit edit, when challenged, the physical clone produced an identical physical response to the original device. To the best of our knowledge, this is the first work in which a physical clone of a Physically Unclonable Function was produced.
{"title":"Cloning Physically Unclonable Functions","authors":"Clemens Helfmeier, C. Boit, Dmitry Nedospasov, Jean-Pierre Seifert","doi":"10.1109/HST.2013.6581556","DOIUrl":"https://doi.org/10.1109/HST.2013.6581556","url":null,"abstract":"As system security demands continue to evolve, Physically Unclonable Functions (PUFs) are a promising solution for secure storage on Integrated Circuits (ICs). SRAM PUFs are among the most popular types of PUFs, since they require no additional circuitry and can be implemented with on-die memories such as caches and data memory that are readily available on both ASICs and FPGAs. This work demonstrates that SRAM PUFs are not well suited as PUFs, as they do not meet several requirements that constitute an ideal PUF. The compact nature of SRAM, standard interconnects and resiliency to environmental effects make SRAM PUFs particularly easy to clone. We consider several ways in which SRAM PUFs can be characterized and demonstrate a Focused Ion Beam circuit edit with which we were able to produce a physical clone of our Proof-of-Concept SRAM PUF implementation. As a result of the circuit edit, when challenged, the physical clone produced an identical physical response to the original device. To the best of our knowledge, this is the first work in which a physical clone of a Physically Unclonable Function was produced.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"6 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79216011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581561
M. Aagaard, G. Gong, Rajesh K. Mota
This paper presents two versions of a Welch-Gong cipher designed for use in passive RFID tags. The low-cost and low-power requirements for passive RFID tags impose stringent design constraints for the chips used in the tags. The WG5-80(x) cipher operates over the finite field F25, and has an 80-bit secret key and 80-bit initialization vector. WG5-80(x11) is the same as WG5-80(x), but includes a decimation function of x11, which increases the linear complexity at the cost of losing the 1-order resiliency property that is inherent in the WG-transform. Both ciphers can be implemented using parallel LFSRs to provide throughputs ranging from one to twenty-five bits per clock cycle. On a 130 nm fabrication process with a clockspeed of 100 kHz and a throughput of 100 kbps, WG5-80(x) has an area of 1229 GE (gate equivalents) and a power consumption of 0.78 μW. The linear complexity of the cipher is 217. The corresponding numbers for WG5-80(x11) are 1235GE, 0.79 μW, and 222. This paper presents results for a 130 nm and a 180 nm process, and data rates of 100 kbps and 200 kbps. The combined area and power results for the WG5 ciphers are approximately 5% better than previous results for low-data-rate ciphers. In addition, WG-ciphers offer mathematically guaranteed randomness and cryptographic properties not provided by other ciphers.
{"title":"Hardware implementations of the WG-5 cipher for passive RFID tags","authors":"M. Aagaard, G. Gong, Rajesh K. Mota","doi":"10.1109/HST.2013.6581561","DOIUrl":"https://doi.org/10.1109/HST.2013.6581561","url":null,"abstract":"This paper presents two versions of a Welch-Gong cipher designed for use in passive RFID tags. The low-cost and low-power requirements for passive RFID tags impose stringent design constraints for the chips used in the tags. The WG5-80(x) cipher operates over the finite field F25, and has an 80-bit secret key and 80-bit initialization vector. WG5-80(x11) is the same as WG5-80(x), but includes a decimation function of x11, which increases the linear complexity at the cost of losing the 1-order resiliency property that is inherent in the WG-transform. Both ciphers can be implemented using parallel LFSRs to provide throughputs ranging from one to twenty-five bits per clock cycle. On a 130 nm fabrication process with a clockspeed of 100 kHz and a throughput of 100 kbps, WG5-80(x) has an area of 1229 GE (gate equivalents) and a power consumption of 0.78 μW. The linear complexity of the cipher is 217. The corresponding numbers for WG5-80(x11) are 1235GE, 0.79 μW, and 222. This paper presents results for a 130 nm and a 180 nm process, and data rates of 100 kbps and 200 kbps. The combined area and power results for the WG5 ciphers are approximately 5% better than previous results for low-data-rate ciphers. In addition, WG-ciphers offer mathematically guaranteed randomness and cryptographic properties not provided by other ciphers.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"1 1","pages":"29-34"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86583694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581557
Stéphanie Kerckhof, François Durvaux, François-Xavier Standaert, Benoît Gérard
The use of Soft Physical Hash (SPH) functions has been recently introduced as a flexible and efficient way to detect Intellectual Property (IP) cores in microelectronic systems. Previous works have mainly investigated software IP to validate this approach. In this paper, we extend it towards the practically important case of FPGA designs. Based on experiments, we put forward that SPH functions-based detection is a promising and low-cost solution for preventing anti-counterfeiting, as it does not require any a-priori modification of the design flow. In particular, we illustrate its performances with stand-alone FPGA designs, re-synthetized FPGA designs, and in the context of parasitic IPs running in parallel.
{"title":"Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results","authors":"Stéphanie Kerckhof, François Durvaux, François-Xavier Standaert, Benoît Gérard","doi":"10.1109/HST.2013.6581557","DOIUrl":"https://doi.org/10.1109/HST.2013.6581557","url":null,"abstract":"The use of Soft Physical Hash (SPH) functions has been recently introduced as a flexible and efficient way to detect Intellectual Property (IP) cores in microelectronic systems. Previous works have mainly investigated software IP to validate this approach. In this paper, we extend it towards the practically important case of FPGA designs. Based on experiments, we put forward that SPH functions-based detection is a promising and low-cost solution for preventing anti-counterfeiting, as it does not require any a-priori modification of the design flow. In particular, we illustrate its performances with stand-alone FPGA designs, re-synthetized FPGA designs, and in the context of parasitic IPs running in parallel.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"54 1","pages":"7-12"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75893304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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