{"title":"Breast Cancer Detection Based on Multi-Slotted Patch Antenna at ISM Band","authors":"Mussa Elsaadi, Rema Hamad","doi":"10.4236/cs.2023.145001","DOIUrl":"https://doi.org/10.4236/cs.2023.145001","url":null,"abstract":"","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70482522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply VDD = 1.8 V, the resulting set of performance parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
{"title":"Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation","authors":"Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra","doi":"10.4236/cs.2023.146003","DOIUrl":"https://doi.org/10.4236/cs.2023.146003","url":null,"abstract":"This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply VDD = 1.8 V, the resulting set of performance parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135106283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Behavioral Model of Molecular Gap-Type Atomic Switches and Its SPICE Integration","authors":"H. Kubota, T. Hasegawa, M. Akai‐Kasaya, T. Asai","doi":"10.4236/cs.2022.131001","DOIUrl":"https://doi.org/10.4236/cs.2022.131001","url":null,"abstract":"","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70482015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Aslan, Mahbubur Rahman, Sourav Das, B. Schnitta
Image-guided needles are currently used for drug delivery in bodies, but the additional time associated with aligning and maintaining the needle’s position results in increased patient discomfort or risk of invasion of the human body. In this paper, a needle guidance system using piezoelectric materials is designed and analyzed for precise drug delivery without damaging parts of the body and improving processing time. A piezoelectric generates an ultrasound wave that can propagate through different mediums, and a second piezoelectric crystal can receive that energy and convert it into voltage. A 1D real-time image represents the changes of the voltage induced in the double piezoelectric crystal. Extensive data analysis and visualization are done using different obstacles and location of the needle verified for other mediums. The presence of obstacles in between those crystals can be identified in the real-time grayscale image. The needle can reach its destination using this image information as directional guidance. This guided drug delivery improves patient recovery time and eliminates extra injuries that can be caused due to wrong needle injections, such as lumbar puncture-related nerve damage.
{"title":"Ultrasound Needle Guidance System for Precision Vaccinations and Drug Deliver","authors":"S. Aslan, Mahbubur Rahman, Sourav Das, B. Schnitta","doi":"10.4236/CS.2021.121001","DOIUrl":"https://doi.org/10.4236/CS.2021.121001","url":null,"abstract":"Image-guided \u0000needles are currently used for drug delivery in bodies, but the additional time \u0000associated with aligning and maintaining the needle’s position results in increased patient discomfort \u0000or risk of invasion of the human body. In this paper, a needle guidance system \u0000using piezoelectric materials is designed and analyzed for precise drug \u0000delivery without damaging parts of the body and improving processing time. A \u0000piezoelectric generates an ultrasound wave that can propagate through different \u0000mediums, and a second piezoelectric crystal can receive that energy and convert \u0000it into voltage. A 1D real-time image represents the changes of the voltage \u0000induced in the double piezoelectric crystal. Extensive data analysis and \u0000visualization are done using different obstacles and location of the needle \u0000verified for other mediums. The presence of obstacles in between those crystals \u0000can be identified in the real-time grayscale image. The needle can reach its \u0000destination using this image information as directional guidance. This guided \u0000drug delivery improves patient recovery time and eliminates extra injuries that \u0000can be caused due to wrong needle injections, such as lumbar puncture-related \u0000nerve damage.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"12 1","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2021-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42044971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Large-scale scientific instruments strongly support top-level research all around the world. Besides their intrinsic merits, they often play a valuable role as pathfinders for developing and testing instrumentation and as training grounds for young researchers. Strategies and roadmaps for these facilities have become a priority for a number of private and public funding organizations. Despite the large amount of mature work done in the industrial arena, it is difficult to find documents providing clear and concise orientation on how to prevent or minimize the damage caused by electrostatic discharges (ESD) in research infrastructure. This paper aims to gather all this information to develop a static charge control plan for a large-scale scientific facility. The specific case of the static charge control plan for the installation of CTA-LST telescopes is added as an example and verification of the actual applicability of the measures proposed in this document, providing static charge in human body monitoring measurements. Specific tests performed on equipment with ESD sensitive components are also described, which helped to assess any possible damage.
{"title":"Drafting an Electrostatic Charge Control Plan for a Large Scale Scientific Instrument: Guidelines and a Case Study","authors":"C. Oliver, O. Martínez, S. Ronda, J. M. Miranda","doi":"10.4236/cs.2021.123003","DOIUrl":"https://doi.org/10.4236/cs.2021.123003","url":null,"abstract":"Large-scale scientific instruments strongly support top-level research all around the world. Besides their intrinsic merits, they often play a valuable role as pathfinders for developing and testing instrumentation and as training grounds for young researchers. Strategies and roadmaps for these facilities have become a priority for a number of private and public funding organizations. Despite the large amount of mature work done in the industrial arena, it is difficult to find documents providing clear and concise orientation on how to prevent or minimize the damage caused by electrostatic discharges (ESD) in research infrastructure. This paper aims to gather all this information to develop a static charge control plan for a large-scale scientific facility. The specific case of the static charge control plan for the installation of CTA-LST telescopes is added as an example and verification of the actual applicability of the measures proposed in this document, providing static charge in human body monitoring measurements. Specific tests performed on equipment with ESD sensitive components are also described, which helped to assess any possible damage.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44944291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling of Waveguide Filter Using Wave Concept Iterative Procedure","authors":"A. Sassi, N. Sboui, A. Gharbi, H. Baudrand","doi":"10.4236/CS.2021.122002","DOIUrl":"https://doi.org/10.4236/CS.2021.122002","url":null,"abstract":"","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"12 1","pages":"13-22"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70481812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
DG-MOSFETs are the most widely explored device architectures for na-no-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (t si < 10 nm) DG-MOS structures, charge carriers are affected by t si induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, I ON - I OFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (T op ), channel doping concentration (N c ), gate oxide thickness (t ox ) and Silicon film thickness (t si ). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLAS TM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.
{"title":"Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs","authors":"Yashu Swami, Sanjeev Rai","doi":"10.4236/cs.2021.124004","DOIUrl":"https://doi.org/10.4236/cs.2021.124004","url":null,"abstract":"DG-MOSFETs are the most widely explored device architectures for na-no-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (t si < 10 nm) DG-MOS structures, charge carriers are affected by t si induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, I ON - I OFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (T op ), channel doping concentration (N c ), gate oxide thickness (t ox ) and Silicon film thickness (t si ). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLAS TM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70481994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An efficient way of noise reduction has been presented: A modified Costas loop called as Masterpiece. The basic version of the Costas loop has been developed for SSB SC demodulation, but the same circuit can be applied for QAM (quadrature amplitude modulation) demodulation as well. Noise sensitivity of the basic version has been decreased. One trick is the transformation of the real channel input into complex signal, the other one is the application of our folding algorithm. The result is that the Masterpiece provides a 4QAM symbol error rate (SER) of 6 × 10−4 for input signal to noise ratio (SNR) of −1 dB. In this paper, an improved version of the original Masterpiece is introduced. The complex channel input signal is normalized, and rotational average is applied. The 4QAM result is SER of 3 × 10−4 for SNR of −1 dB. At SNR of 0 dB, the improved version produces 100 times better SER than that the original Costas loop does. In our times, this topic has a special importance because by application of our Masterpiece, all dangerous field strengths from 5G and WiFi, could be decreased by orders of magnitude. The Masterpiece can break the Shannon formula.
{"title":"Noise Reduction for Digital Communications—The Masterpiece, a Modified Costas Loop","authors":"Janos Ladvanszky","doi":"10.4236/cs.2020.116006","DOIUrl":"https://doi.org/10.4236/cs.2020.116006","url":null,"abstract":"An efficient way of noise reduction has been presented: A modified Costas loop called as Masterpiece. The basic version of the Costas loop has been developed for SSB SC demodulation, but the same circuit can be applied for QAM (quadrature amplitude modulation) demodulation as well. Noise sensitivity of the basic version has been decreased. One trick is the transformation of the real channel input into complex signal, the other one is the application of our folding algorithm. The result is that the Masterpiece provides a 4QAM symbol error rate (SER) of 6 × 10−4 for input signal to noise ratio (SNR) of −1 dB. In this paper, an improved version of the original Masterpiece is introduced. The complex channel input signal is normalized, and rotational average is applied. The 4QAM result is SER of 3 × 10−4 for SNR of −1 dB. At SNR of 0 dB, the improved version produces 100 times better SER than that the original Costas loop does. In our times, this topic has a special importance because by application of our Masterpiece, all dangerous field strengths from 5G and WiFi, could be decreased by orders of magnitude. The Masterpiece can break the Shannon formula.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70481713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zainab Haseeb, D. Prasad, Mainuddin nbsp, M. W. Akram
This paper presents a floating resistor employing CIDITA (current inverting differential input transconductance amplifier). The proposed floating resistor is based on CMOS technology of 0.18 μm. For the realization of this floating inductor, two CIDITA have been cascaded together, no other passive elements are used, giving advantage of reduced chip area and hence reduced losses. The given circuit topology has an advantage of realizing both positive and negative resistors. This paper presents a simple circuitry of floating resistor in which the value of resistance can be tuned by adjusting the gate voltage of MOSFET. The PSpice simulation result shows constant resistance of 1.6 KΩ for frequency bandwidth of 1 Hz to 1 MHz, with supply voltage of ±1.25 volts.
{"title":"Tunable Floating Resistor Based on Current Inverting Differential Input Transconductance Amplifier","authors":"Zainab Haseeb, D. Prasad, Mainuddin nbsp, M. W. Akram","doi":"10.4236/cs.2020.115005","DOIUrl":"https://doi.org/10.4236/cs.2020.115005","url":null,"abstract":"This paper presents a floating resistor employing CIDITA (current inverting differential input transconductance amplifier). The proposed floating resistor is based on CMOS technology of 0.18 μm. For the realization of this floating inductor, two CIDITA have been cascaded together, no other passive elements are used, giving advantage of reduced chip area and hence reduced losses. The given circuit topology has an advantage of realizing both positive and negative resistors. This paper presents a simple circuitry of floating resistor in which the value of resistance can be tuned by adjusting the gate voltage of MOSFET. The PSpice simulation result shows constant resistance of 1.6 KΩ for frequency bandwidth of 1 Hz to 1 MHz, with supply voltage of ±1.25 volts.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"11 1","pages":"51-56"},"PeriodicalIF":0.0,"publicationDate":"2020-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42822747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new first order all pass filter configurations. The proposed all pass filter configuration employs two configurations namely VDVTA and OTAs based first order all pass filter configuration. The first proposed configuration employs a single VDVTA and one grounded capacitor whereas the second proposed configuration employs two OTAs and one grounded capacitor. Both types of proposed configurations are fully electronically tunable and their quality factors do not depend on tunable pole frequency range. The reported configurations yield low active and passive sensitivities and also have low power consumption with very low supply voltage ± 0.85 V with Bias Voltage ± 0.50 V. The PSPICE simulation of the proposed VDVTA and two OTAs based first order all pass filter configurations are verified using 0.18 μm CMOS Technology Process Parameters.
{"title":"CMOS Realization of VDVTA and OTA Based Fully Electronically Tunable First Order All Pass Filter with Optimum Linearity at Low Supply Voltage ± 0.85 V","authors":"G. Singh","doi":"10.4236/cs.2020.114004","DOIUrl":"https://doi.org/10.4236/cs.2020.114004","url":null,"abstract":"This paper presents a new first order all pass filter configurations. The proposed all pass filter configuration employs two configurations namely VDVTA and OTAs based first order all pass filter configuration. The first proposed configuration employs a single VDVTA and one grounded capacitor whereas the second proposed configuration employs two OTAs and one grounded capacitor. Both types of proposed configurations are fully electronically tunable and their quality factors do not depend on tunable pole frequency range. The reported configurations yield low active and passive sensitivities and also have low power consumption with very low supply voltage ± 0.85 V with Bias Voltage ± 0.50 V. The PSPICE simulation of the proposed VDVTA and two OTAs based first order all pass filter configurations are verified using 0.18 μm CMOS Technology Process Parameters.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43720848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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