A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the five standard biquadratic filters: low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) from the same circuit configuration. The presented universal filter offers low active and passive sensitivities. SPICE (Version 16.5) simulation results using 0.18 μm TSMC technology have been included.
{"title":"MISO-Type Voltage-Mode Universal Biquadratic Filter Using Single Universal Voltage Conveyor","authors":"K. L. Pushkar, Kavya Gupta","doi":"10.4236/CS.2017.89015","DOIUrl":"https://doi.org/10.4236/CS.2017.89015","url":null,"abstract":"A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the five standard biquadratic filters: low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) from the same circuit configuration. The presented universal filter offers low active and passive sensitivities. SPICE (Version 16.5) simulation results using 0.18 μm TSMC technology have been included.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"227-236"},"PeriodicalIF":0.0,"publicationDate":"2017-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47293502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock; a performance increase of up to 16 times.
在密码学中，三重DES（3DES、TDES或正式的TDEA）是一种对称密钥块密码，它将数据加密标准（DES）密码算法应用于每个数据块三次。众所周知，电子支付系统使用TDES方案来加密/解密数据，因此更快的实现具有重要意义。现场可编程门阵列（FPGA）为优化应用程序的性能提供了一种新的解决方案，同时三重数据加密标准（TDES）为信息安全提供了手段。在本文中，我们提出了一种在VHDL中以电子代码簿（EBC）模式实现的这种常用密码方案的流水线实现，旨在提高性能。我们通过在DES解密密钥调度器中实现TDES密钥缓冲器和右旋转来实现48级流水线深度。以Altera Cyclone II FPGA为平台，利用Altera提供的EDA工具对其实现进行了设计和验证。我们从合成和时序结果中收集成本和吞吐量信息，并将我们的设计性能与其他文献中介绍的常见实现进行比较。我们的设计在50 MHz时钟下实现了3.2 Gbps的吞吐量；性能提高了16倍。
{"title":"A Fast FPGA Implementation for Triple DES Encryption Scheme","authors":"E. D. Rosal, Sanjeev Kumar","doi":"10.4236/CS.2017.89016","DOIUrl":"https://doi.org/10.4236/CS.2017.89016","url":null,"abstract":"In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock; a performance increase of up to 16 times.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"237-246"},"PeriodicalIF":0.0,"publicationDate":"2017-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49550603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Antonios N. Dadaliaris, P. Oikonomou, M. Koziri, Evangelia Nerantzaki, Thanasis Loukopoulos, G. Stamoulis
Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.
{"title":"A Connectivity-Based Legalization Scheme for Standard Cell Placement","authors":"Antonios N. Dadaliaris, P. Oikonomou, M. Koziri, Evangelia Nerantzaki, Thanasis Loukopoulos, G. Stamoulis","doi":"10.4236/CS.2017.88013","DOIUrl":"https://doi.org/10.4236/CS.2017.88013","url":null,"abstract":"Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"191-201"},"PeriodicalIF":0.0,"publicationDate":"2017-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44315416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a gross examination about Unified Power Quality Conditioner (UPQC) to invigorate the power issues at the distribution level of the electrical system. Nowadays power electronics research has added the importance of power quality studies, for concrete illustration, Custom Power Devices (CPD) and Flexible AC Transmission position (FACTS) devices. The approach offered in this paper utilizes the series and shunt compensator of Unified Power Quality Conditioner (UPQC) to inject a compensation voltage in-phase with the source current over voltage fluctuations. The execution of two structures of UPQC, left-shunt (L-UPQC) and right-shunt (R-UPQC) are investigated under diverse operating conditions based on the fuzzy logic controller to raise the value of power quality of a single feeder distribution system by MATLAB/Simulink programming. Various power quality issues have been analyzed in this study. Finally, the right shunt UPQC is outperformed in this proposed power system.
{"title":"Fuzzy Logic Controller Implementation of Power Quality Improvement Using UPQC","authors":"S. Balaslubramaniyan, T. S. Sivakumaran","doi":"10.4236/CS.2017.88014","DOIUrl":"https://doi.org/10.4236/CS.2017.88014","url":null,"abstract":"This paper presents a gross examination about Unified Power Quality Conditioner (UPQC) to invigorate the power issues at the distribution level of the electrical system. Nowadays power electronics research has added the importance of power quality studies, for concrete illustration, Custom Power Devices (CPD) and Flexible AC Transmission position (FACTS) devices. The approach offered in this paper utilizes the series and shunt compensator of Unified Power Quality Conditioner (UPQC) to inject a compensation voltage in-phase with the source current over voltage fluctuations. The execution of two structures of UPQC, left-shunt (L-UPQC) and right-shunt (R-UPQC) are investigated under diverse operating conditions based on the fuzzy logic controller to raise the value of power quality of a single feeder distribution system by MATLAB/Simulink programming. Various power quality issues have been analyzed in this study. Finally, the right shunt UPQC is outperformed in this proposed power system.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"202-226"},"PeriodicalIF":0.0,"publicationDate":"2017-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44789980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent days, the multilevel inverter technology is widely applied to domestic and industrial applications for medium voltage conversion. But, the power quality issues of the multilevel inverter limit the usage of much sensitive equipment like medical instruments. The lower distortion level of the output voltage and current can generate a quality sinusoidal output voltage in inverters and they can be used for many applications. The harmonics can cause major problems in equipments due to the nonlinear loads connected with the power system. So, it is necessary to minimize the losses to raise its overall efficiency. In this paper, a new topology of seven level asymmetrical cascaded H-bridge multilevel inverter with a Fuzzy logic controller had been implemented to reduce the Total Harmonic Distortion (THD) and to improve the overall performance of the inverter. The proposed model is well suited for use with a solar PV application. In this topology, only six IGBT switches are used with three different voltage ratings of PV modules (1:2:4). The lower number of semiconductor switches leads to minimizing overall di/dt ratings and voltage stress on each switches and switching losses. The gate pulses generated by Sinusoidal Pulse Width Modulation (SPWM) technique with a Fuzzy logic controller are also introduced. A buck-boost converter is used to maintain the constant PV voltage level integrated by an MPPT technique followed by Perturb and Observer algorithm is also implemented. The MPPT is used to harness the maximum power of solar radiations under its various climatic conditions. The new topology is evaluated by a Matlab/Simulink model and compared with a hardware model. The results proved that the THD achieved by this topology is 1.66% and realized that it meets the IEEE harmonic standards.
{"title":"THD Analysis of Cascaded H-Bridge Inverter with Fuzzy Logic Controller","authors":"N. Sivakumar, A. Sumathi","doi":"10.4236/CS.2017.87011","DOIUrl":"https://doi.org/10.4236/CS.2017.87011","url":null,"abstract":"In recent days, the multilevel inverter technology is widely applied to domestic \u0000and industrial applications for medium voltage conversion. But, the power \u0000quality issues of the multilevel inverter limit the usage of much sensitive \u0000equipment like medical instruments. The lower distortion level of the output \u0000voltage and current can generate a quality sinusoidal output voltage in inverters \u0000and they can be used for many applications. The harmonics can cause \u0000major problems in equipments due to the nonlinear loads connected with the \u0000power system. So, it is necessary to minimize the losses to raise its overall efficiency. \u0000In this paper, a new topology of seven level asymmetrical cascaded \u0000H-bridge multilevel inverter with a Fuzzy logic controller had been implemented \u0000to reduce the Total Harmonic Distortion (THD) and to improve the \u0000overall performance of the inverter. The proposed model is well suited for use \u0000with a solar PV application. In this topology, only six IGBT switches are used \u0000with three different voltage ratings of PV modules (1:2:4). The lower number \u0000of semiconductor switches leads to minimizing overall di/dt ratings and voltage \u0000stress on each switches and switching losses. The gate pulses generated by \u0000Sinusoidal Pulse Width Modulation (SPWM) technique with a Fuzzy logic \u0000controller are also introduced. A buck-boost converter is used to maintain the \u0000constant PV voltage level integrated by an MPPT technique followed by Perturb \u0000and Observer algorithm is also implemented. The MPPT is used to harness \u0000the maximum power of solar radiations under its various climatic conditions. \u0000The new topology is evaluated by a Matlab/Simulink model and compared \u0000with a hardware model. The results proved that the THD achieved by \u0000this topology is 1.66% and realized that it meets the IEEE harmonic standards.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"171-183"},"PeriodicalIF":0.0,"publicationDate":"2017-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42349694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an intelligent algorithm for heart diseases diagnosis using phonocardiogram (PCG). The proposed technique consists of four stages: Data acquisition, pre-processing, feature extraction and classification. PASCAL heart sound database is used in this research. The second stage concerns with removing noise and artifacts from the PCG signals. Feature extraction stage is carried out using discrete wavelet transform (DWT). Finally, artificial neural network (ANN) has been used for classification stage with an overall accuracy 97%.
{"title":"Heart Diseases Diagnosis Using Intelligent Algorithm Based on PCG Signal Analysis","authors":"Mohammed Nabih-Ali, E. El-Dahshan, Ashraf S Yahia","doi":"10.4236/CS.2017.87012","DOIUrl":"https://doi.org/10.4236/CS.2017.87012","url":null,"abstract":"This paper presents an intelligent algorithm for heart diseases diagnosis using \u0000phonocardiogram (PCG). The proposed technique consists of four stages: \u0000Data acquisition, pre-processing, feature extraction and classification. PASCAL \u0000heart sound database is used in this research. The second stage concerns with \u0000removing noise and artifacts from the PCG signals. Feature extraction stage is \u0000carried out using discrete wavelet transform (DWT). Finally, artificial neural \u0000network (ANN) has been used for classification stage with an overall accuracy \u000097%.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"184-190"},"PeriodicalIF":0.0,"publicationDate":"2017-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46889791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kota Ando, Shinya Takamaeda-Yamazaki, M. Ikebe, T. Asai, M. Motomura
Convolutional neural network (CNN) is an essential model to achieve high accuracy in various machine learning applications, such as image recognition and natural language processing. One of the important issues for CNN acceleration with high energy efficiency and processing performance is efficient data reuse by exploiting the inherent data locality. In this paper, we propose a novel CGRA (Coarse Grained Reconfigurable Array) architecture with time-domain multithreading for exploiting input data locality. The multithreading on each processing element enables the input data reusing through multiple computation periods. This paper presents the accelerator design performance analysis of the proposed architecture. We examine the structure of memory subsystems, as well as the architecture of the computing array, to supply required data with minimal performance overhead. We explore efficient architecture design alternatives based on the characteristics of modern CNN configurations. The evaluation results show that the available bandwidth of the external memory can be utilized efficiently when the output plane is wider (in earlier layers of many CNNs) while the input data locality can be utilized maximally when the number of output channel is larger (in later layers).
{"title":"A Multithreaded CGRA for Convolutional Neural Network Processing","authors":"Kota Ando, Shinya Takamaeda-Yamazaki, M. Ikebe, T. Asai, M. Motomura","doi":"10.4236/CS.2017.86010","DOIUrl":"https://doi.org/10.4236/CS.2017.86010","url":null,"abstract":"Convolutional neural network (CNN) is an essential model to achieve high accuracy in various machine learning applications, such as image recognition and natural language processing. One of the important issues for CNN acceleration with high energy efficiency and processing performance is efficient data reuse by exploiting the inherent data locality. In this paper, we propose a novel CGRA (Coarse Grained Reconfigurable Array) architecture with time-domain multithreading for exploiting input data locality. The multithreading on each processing element enables the input data reusing through multiple computation periods. This paper presents the accelerator design performance analysis of the proposed architecture. We examine the structure of memory subsystems, as well as the architecture of the computing array, to supply required data with minimal performance overhead. We explore efficient architecture design alternatives based on the characteristics of modern CNN configurations. The evaluation results show that the available bandwidth of the external memory can be utilized efficiently when the output plane is wider (in earlier layers of many CNNs) while the input data locality can be utilized maximally when the number of output channel is larger (in later layers).","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"149-170"},"PeriodicalIF":0.0,"publicationDate":"2017-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70482126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ali Mohsen, A. Harb, N. Deltimple, Abraham Serhane
This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.
{"title":"28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II","authors":"Ali Mohsen, A. Harb, N. Deltimple, Abraham Serhane","doi":"10.4236/CS.2017.85007","DOIUrl":"https://doi.org/10.4236/CS.2017.85007","url":null,"abstract":"This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"8 1","pages":"111-121"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44099295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Itaru Hida, Shinya Takamaeda-Yamazaki, M. Ikebe, M. Motomura, T. Asai
In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation; this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.
{"title":"A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator","authors":"Itaru Hida, Shinya Takamaeda-Yamazaki, M. Ikebe, M. Motomura, T. Asai","doi":"10.4236/CS.2017.85009","DOIUrl":"https://doi.org/10.4236/CS.2017.85009","url":null,"abstract":"In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation; this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"134-147"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45208284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, efficient, high gain and pencil beam grid antenna array is proposed for hyperthermia breast cancer therapy system. The proposed antenna bandwidth extends from 4.8 GHz to 4.9 GHz at resonant frequency of 4.86 GHz. This frequency band has been reported for the breast cancer hyperthermia therapy. The grid long and short sides are responsible for the undesired cross-polarized radiation and desired copolarized radiation, respectively. The unsuitability of the conventional grid antenna array is ensured by investigating its radiation properties. The proposed grid antenna array short side width is varied and its long side width is kept wide as possible to enhance the radiation properties and to reduce the losses. Also, a reflector has been used for gain enhancement purpose. The proposed grid antenna array achieves side lobe level and 3 dB beam width of —27.9 dB and 25.9° for the E-plane and —27.9 dB and 26.3° for the H-plane, respectively. The breast phantom is irradiated by both proposed and conventional grid antenna arrays for 10 minutes. The proposed grid antenna array achieves 8°C temperature increase within the breast phantom area compared to 2°C temperature increase for conventional one. The proposed grid antenna array is highly efficient, high gain and light weight, and it has a very suitable radiation property for hyperthermia breast cancer therapy.
{"title":"Pencil Beam Grid Antenna Array for Hyperthermia Breast Cancer Treatment System","authors":"M. Tayel, T. Abouelnaga, A. Elnagar","doi":"10.4236/CS.2017.85008","DOIUrl":"https://doi.org/10.4236/CS.2017.85008","url":null,"abstract":"In this paper, efficient, high gain and pencil beam grid antenna array is proposed for hyperthermia breast cancer therapy system. The proposed \u0000antenna bandwidth extends from 4.8 GHz to 4.9 GHz at resonant frequency of 4.86 GHz. This frequency band has been reported for \u0000the breast cancer hyperthermia therapy. The grid long and short sides are responsible for \u0000the undesired cross-polarized radiation and desired copolarized radiation, \u0000respectively. The unsuitability of the conventional grid antenna array is \u0000ensured by investigating its radiation properties. The proposed grid antenna \u0000array short side width is varied and its long side width is kept wide as \u0000possible to enhance the radiation properties and to reduce the losses. Also, a \u0000reflector has been used for gain enhancement purpose. The proposed grid antenna array achieves side lobe level and 3 dB beam width of —27.9 dB and 25.9° for the E-plane and —27.9 dB and 26.3° for the H-plane, respectively. The breast phantom is irradiated by both proposed and conventional grid \u0000antenna arrays for 10 minutes. The proposed grid antenna array achieves 8°C temperature increase within the breast phantom area compared to 2°C \u0000temperature increase for conventional one. The proposed grid antenna array is highly efficient, high gain and light weight, and it has a very suitable \u0000radiation property for hyperthermia breast \u0000cancer therapy.","PeriodicalId":63422,"journal":{"name":"电路与系统(英文)","volume":"08 1","pages":"122-133"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48676246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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