Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105418
C. Chen, Sunghyun Park, T. Krishna, L. Peh
Networks-on-Chip (NoCs) are emerging as the answer to non-scalable buses for connecting multiple cores in Chip Multi Processors (CMPs), and multiple IP blocks in Multi Processor Systems-on-Chip (MPSoCs). These networks require an extremely low-power datapath to ensure sustained scalability, and higher performance/watt. Crossbars and links form the core of a network datapath, and integrating low-swing links within these will reduce power significantly. Low-swing links however require significant custom circuit design effort to deliver good power efficiency and high bit rate, in the face of noise. As a result, low-swing links have not been able to make it to mainstream chips which rely on crossbar and link generators from RTL. In this paper, we present a datapath generator that creates automated layouts for crossbars with noise-robust low-swing links within them. To the best of our knowledge, this is the first crossbar generator that (1) creates layouts, instead of generating just synthesizable RTL; and (2) integrates noise-robust low-swing links in an automated manner. We demonstrate our generated datapath in a fully-synthesized NoC router, and observe 50% power reduction on datapath.
{"title":"A low-swing crossbar and link generator for low-power networks-on-chip","authors":"C. Chen, Sunghyun Park, T. Krishna, L. Peh","doi":"10.1109/ICCAD.2011.6105418","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105418","url":null,"abstract":"Networks-on-Chip (NoCs) are emerging as the answer to non-scalable buses for connecting multiple cores in Chip Multi Processors (CMPs), and multiple IP blocks in Multi Processor Systems-on-Chip (MPSoCs). These networks require an extremely low-power datapath to ensure sustained scalability, and higher performance/watt. Crossbars and links form the core of a network datapath, and integrating low-swing links within these will reduce power significantly. Low-swing links however require significant custom circuit design effort to deliver good power efficiency and high bit rate, in the face of noise. As a result, low-swing links have not been able to make it to mainstream chips which rely on crossbar and link generators from RTL. In this paper, we present a datapath generator that creates automated layouts for crossbars with noise-robust low-swing links within them. To the best of our knowledge, this is the first crossbar generator that (1) creates layouts, instead of generating just synthesizable RTL; and (2) integrates noise-robust low-swing links in an automated manner. We demonstrate our generated datapath in a fully-synthesized NoC router, and observe 50% power reduction on datapath.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86135498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105344
X. Gao, L. Macchiarulo
In this paper, we propose a jumper insertion algorithm under timing and antenna ratio constraints. Differently from the existing works which assume the jumpers to be placed above the highest layer of a routing tree, our work allows the jumpers to be placed on any routing layer. Furthermore, our algorithm is aware of the delay caused by the jumpers. Experimental results show that, by allowing the jumpers to be placed on any layer, the number of vias added by the jumpers can be reduced by 50%. The experiments also show that our timing-aware jumper insertion algorithm is better at satisfying the timing constraints.
{"title":"A jumper insertion algorithm under antenna ratio and timing constraints","authors":"X. Gao, L. Macchiarulo","doi":"10.1109/ICCAD.2011.6105344","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105344","url":null,"abstract":"In this paper, we propose a jumper insertion algorithm under timing and antenna ratio constraints. Differently from the existing works which assume the jumpers to be placed above the highest layer of a routing tree, our work allows the jumpers to be placed on any routing layer. Furthermore, our algorithm is aware of the delay caused by the jumpers. Experimental results show that, by allowing the jumpers to be placed on any layer, the number of vias added by the jumpers can be reduced by 50%. The experiments also show that our timing-aware jumper insertion algorithm is better at satisfying the timing constraints.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78322302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105367
Tsung-Wei Huang, Tsung-Yi Ho, K. Chakrabarty
Designs for pin-constrained digital microfluidic biochips (PDMFBs) are receiving much attention because they simplify chip fabrication and packaging, and reduce product cost. To reduce the pin count, broadcast addressing, by minimally grouping electrode sets with non-conflict signal merging, has emerged as a promising solution. Nevertheless, naive signal merging has the potential to cause excessive electrode actuations, which has been reported to have direct and adverse effect on chip reliability. According to recent studies, reliability is an important attribute for PDMFBs particularly developed for medical applications as it directly affects the final medical decision making. However, no research findings have been reported on the reliability problem in pin-constrained designs. To make PDMFBs more feasible for practical applications, we propose in this paper the first matching-based reliability-oriented broadcast-addressing algorithm for PDMFBs. We identify the factors that affect reliability and incorporate into the design-technique attributes that enhance reliability. Experimental results demonstrate the effectiveness of the proposed algorithm.
{"title":"Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips","authors":"Tsung-Wei Huang, Tsung-Yi Ho, K. Chakrabarty","doi":"10.1109/ICCAD.2011.6105367","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105367","url":null,"abstract":"Designs for pin-constrained digital microfluidic biochips (PDMFBs) are receiving much attention because they simplify chip fabrication and packaging, and reduce product cost. To reduce the pin count, broadcast addressing, by minimally grouping electrode sets with non-conflict signal merging, has emerged as a promising solution. Nevertheless, naive signal merging has the potential to cause excessive electrode actuations, which has been reported to have direct and adverse effect on chip reliability. According to recent studies, reliability is an important attribute for PDMFBs particularly developed for medical applications as it directly affects the final medical decision making. However, no research findings have been reported on the reliability problem in pin-constrained designs. To make PDMFBs more feasible for practical applications, we propose in this paper the first matching-based reliability-oriented broadcast-addressing algorithm for PDMFBs. We identify the factors that affect reliability and incorporate into the design-technique attributes that enhance reliability. Experimental results demonstrate the effectiveness of the proposed algorithm.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85620104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105303
B. Zatt, M. Shafique, S. Bampi, J. Henkel
A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the leakage energy of the on-chip memory. The knowledge of motion and disparity estimation algorithm in conjunction with video properties are considered to predict the memory requirements of each Macroblock. A cost function is evaluated to determine an appropriate sleep mode for the idle memory sectors, while considering the wakeup overhead (latency and energy). The complete motion and disparity estimation architecture is implemented in a 65nm low power IBM technology. The experiments (for various test video sequences) demonstrate that our architecture provides up to 80% leakage energy reduction compared to state-of-the-art. Our scheme processes motion and disparity estimation of four HD1080p views encoding at 30fps with a power consumption of 57mW.
{"title":"A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding","authors":"B. Zatt, M. Shafique, S. Bampi, J. Henkel","doi":"10.1109/ICCAD.2011.6105303","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105303","url":null,"abstract":"A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the leakage energy of the on-chip memory. The knowledge of motion and disparity estimation algorithm in conjunction with video properties are considered to predict the memory requirements of each Macroblock. A cost function is evaluated to determine an appropriate sleep mode for the idle memory sectors, while considering the wakeup overhead (latency and energy). The complete motion and disparity estimation architecture is implemented in a 65nm low power IBM technology. The experiments (for various test video sequences) demonstrate that our architecture provides up to 80% leakage energy reduction compared to state-of-the-art. Our scheme processes motion and disparity estimation of four HD1080p views encoding at 30fps with a power consumption of 57mW.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86302927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105387
Di-An Li, M. Marek-Sadowska
Due to shrinking wire dimensions, higher current density, and process variations, electromigration (EM) has become a major reliability problem. The existing backend design flows use the maximum allowed current density as the only practical guidance to prevent EM. There is a need for tools capable of performing comprehensive EM analyses. In this paper, we first explain why current density alone does not determine wire's susceptibility to EM. We introduce our variation-aware EM analysis tool, VEMA, for power/ground networks, which are typically the EM-critical parts of a chip. Our tool considers two types of variations: circuit-level and wire geometry-level. VEMA reports distributions of wire lifetimes for circuit-level variations. Compared to existing EM analyzer SysRel, VEMA filters out EM-immortal wires more efficiently and provides detailed feedback for EM violation corrections. VEMA also provides information of geometry-level tolerance for EM-mortal wires.
{"title":"Variation-aware electromigration analysis of power/ground networks","authors":"Di-An Li, M. Marek-Sadowska","doi":"10.1109/ICCAD.2011.6105387","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105387","url":null,"abstract":"Due to shrinking wire dimensions, higher current density, and process variations, electromigration (EM) has become a major reliability problem. The existing backend design flows use the maximum allowed current density as the only practical guidance to prevent EM. There is a need for tools capable of performing comprehensive EM analyses. In this paper, we first explain why current density alone does not determine wire's susceptibility to EM. We introduce our variation-aware EM analysis tool, VEMA, for power/ground networks, which are typically the EM-critical parts of a chip. Our tool considers two types of variations: circuit-level and wire geometry-level. VEMA reports distributions of wire lifetimes for circuit-level variations. Compared to existing EM analyzer SysRel, VEMA filters out EM-immortal wires more efficiently and provides detailed feedback for EM violation corrections. VEMA also provides information of geometry-level tolerance for EM-mortal wires.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84478971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105355
Ting Mei, H. Thornquist, E. Keiter, S. Hutchinson
Many subsystems encountered in communication systems can be modeled as linear periodic time-varyiing (LPTV) systems. In this paper, we present a novel structure preserving reduced-order modeling algorithm for LPTV systems. A key advance of our approach is that it preserves the periodic time-varying structure during the reduction process, thus resulting in reduced LPTV systems. Unlike prior LPTV model order reduction (MOR) techniques which recast the LPTV systems to artificial linear time-invariant (LTI) systems and apply LTI MOR techniques for reduction, our structure preserving algorithm uses a time-varying projection directly on the original LPTV systems. Our approach always produces a smaller system than the original system, which was not valid for previous LPTV MOR techniques. We validate the proposed technique with several circuit examples, demonstrating significant size reductions and excellent accuracy.
{"title":"Structure preserving reduced-order modeling of linear periodic time-varying systems","authors":"Ting Mei, H. Thornquist, E. Keiter, S. Hutchinson","doi":"10.1109/ICCAD.2011.6105355","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105355","url":null,"abstract":"Many subsystems encountered in communication systems can be modeled as linear periodic time-varyiing (LPTV) systems. In this paper, we present a novel structure preserving reduced-order modeling algorithm for LPTV systems. A key advance of our approach is that it preserves the periodic time-varying structure during the reduction process, thus resulting in reduced LPTV systems. Unlike prior LPTV model order reduction (MOR) techniques which recast the LPTV systems to artificial linear time-invariant (LTI) systems and apply LTI MOR techniques for reduction, our structure preserving algorithm uses a time-varying projection directly on the original LPTV systems. Our approach always produces a smaller system than the original system, which was not valid for previous LPTV MOR techniques. We validate the proposed technique with several circuit examples, demonstrating significant size reductions and excellent accuracy.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89635670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105339
C. Sze
The clock distribution network presents one of the most important design challenges in high-performance synchronous VLSI designs. However, automation in clock network synthesis is usually limited to local clock domains for two main reasons. (1) Global clock is too important for designers to take the risk of adopting a fully automated clocking flow. (2) Unlike in other EDA areas (such as synthesis/placement/routing), clock synthesis tools are highly tied to clock network topologies, ground/power planning, clock gating, macro floorplanning, clocking methodologies, etc. It is thus very difficult to implement a set of generic clock synthesis tools for design productivity considerations. That being said, industrial clocking methodologies usually resort to overdesigning because clock synthesis is just too critical to fail.
{"title":"The future of clock network synthesis","authors":"C. Sze","doi":"10.1109/ICCAD.2011.6105339","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105339","url":null,"abstract":"The clock distribution network presents one of the most important design challenges in high-performance synchronous VLSI designs. However, automation in clock network synthesis is usually limited to local clock domains for two main reasons. (1) Global clock is too important for designers to take the risk of adopting a fully automated clocking flow. (2) Unlike in other EDA areas (such as synthesis/placement/routing), clock synthesis tools are highly tied to clock network topologies, ground/power planning, clock gating, macro floorplanning, clocking methodologies, etc. It is thus very difficult to implement a set of generic clock synthesis tools for design productivity considerations. That being said, industrial clocking methodologies usually resort to overdesigning because clock synthesis is just too critical to fail.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82710853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105365
Zahra Lak, N. Nicolici
Addressing lifetime performance degradation caused by circuit ageing has been a topic of active research for the past few years. In this paper we present a different perspective to this problem, by leveraging the presence of clock tuning elements that are commonly available in high-performance designs. By combining clock tuning elements with on-chip sensors for predicting setup/hold-time violations, we introduce a new clock tuning mechanism that operates on-the-fly and it maintains the maximum achievable performance in-system for each circuit sample affected by ageing.
{"title":"In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation","authors":"Zahra Lak, N. Nicolici","doi":"10.1109/ICCAD.2011.6105365","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105365","url":null,"abstract":"Addressing lifetime performance degradation caused by circuit ageing has been a topic of active research for the past few years. In this paper we present a different perspective to this problem, by leveraging the presence of clock tuning elements that are commonly available in high-performance designs. By combining clock tuning elements with on-chip sensors for predicting setup/hold-time violations, we introduce a new clock tuning mechanism that operates on-the-fly and it maintains the maximum achievable performance in-system for each circuit sample affected by ageing.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85950160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105405
Sheng Li, Ke Chen, Jung Ho Ahn, J. Brockman, N. Jouppi
This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.
{"title":"CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques","authors":"Sheng Li, Ke Chen, Jung Ho Ahn, J. Brockman, N. Jouppi","doi":"10.1109/ICCAD.2011.6105405","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105405","url":null,"abstract":"This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77242837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-07DOI: 10.1109/ICCAD.2011.6105386
Moongon Jung, Xi Liu, S. Sitaraman, D. Pan, S. Lim
In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as landing pad and dielectric liner on TSV interfacial crack. Next, we present a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.
{"title":"Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC","authors":"Moongon Jung, Xi Liu, S. Sitaraman, D. Pan, S. Lim","doi":"10.1109/ICCAD.2011.6105386","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105386","url":null,"abstract":"In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as landing pad and dielectric liner on TSV interfacial crack. Next, we present a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75899887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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