Application developers request safe and reliable layers on which to operate. Reliability has been assumed for years, as CMOS circuits were correct-by-construction. Nowadays, shrinking transistor size implies a reduction in yield and reliability of SoC, due to the presence or appearance of physical defects in the circuit. Nanotechnologies face same issues and despite many efforts for yield improvement, circuits remain unreliable. Rethinking the methodologies and design tools becomes now critical. We promote the use of FPGA-like overlay architectures, that offer a stable layer over time for application designers, while embedding fault-mitigation techniques that depend on the underlying technology.
{"title":"Virtual prototyping of R2D NASIC based FPGA","authors":"C. Teodorov, Loïc Lagadec","doi":"10.1145/2770287.2770332","DOIUrl":"https://doi.org/10.1145/2770287.2770332","url":null,"abstract":"Application developers request safe and reliable layers on which to operate. Reliability has been assumed for years, as CMOS circuits were correct-by-construction. Nowadays, shrinking transistor size implies a reduction in yield and reliability of SoC, due to the presence or appearance of physical defects in the circuit. Nanotechnologies face same issues and despite many efforts for yield improvement, circuits remain unreliable. Rethinking the methodologies and design tools becomes now critical. We promote the use of FPGA-like overlay architectures, that offer a stable layer over time for application designers, while embedding fault-mitigation techniques that depend on the underlying technology.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"16 1","pages":"179-180"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75988268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Ghasemzadeh, P. Gaillardon, Majid Yazdani, G. Micheli
With growing concern about process variation in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for design and verification. However, the high dimensionality of parameter space is a serious modeling challenge for emerging VLSI technologies, where the models are increasingly more complex. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. Despite the commonly used methods such as Principal Component Analysis (PCA) and Independent Component Analysis (ICA), this method is capable of dealing with mixed Gaussian and non-Gaussian parameters, and performs a parameter selection in the input space rather than creating a new space. By considering non-linear dependencies among input parameters and outputs, the method results in an effective parameter selection. The application of this method is demonstrated in digital circuit timing analysis to effectively reduce the number of simulations. The experimental results on Double-Gate Silicon NanoWire FET (DG-SiNWFET) technology indicate 2.5x speed up in timing variation analysis of the I5CA589-s27 benchmark with a controlled average error bound of 9.4%.
{"title":"Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection","authors":"H. Ghasemzadeh, P. Gaillardon, Majid Yazdani, G. Micheli","doi":"10.1145/2770287.2770327","DOIUrl":"https://doi.org/10.1145/2770287.2770327","url":null,"abstract":"With growing concern about process variation in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for design and verification. However, the high dimensionality of parameter space is a serious modeling challenge for emerging VLSI technologies, where the models are increasingly more complex. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. Despite the commonly used methods such as Principal Component Analysis (PCA) and Independent Component Analysis (ICA), this method is capable of dealing with mixed Gaussian and non-Gaussian parameters, and performs a parameter selection in the input space rather than creating a new space. By considering non-linear dependencies among input parameters and outputs, the method results in an effective parameter selection. The application of this method is demonstrated in digital circuit timing analysis to effectively reduce the number of simulations. The experimental results on Double-Gate Silicon NanoWire FET (DG-SiNWFET) technology indicate 2.5x speed up in timing variation analysis of the I5CA589-s27 benchmark with a controlled average error bound of 9.4%.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"100 1","pages":"163-168"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80334131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinghua Yang, Niranjan S. Kulkarni, Shimeng Yu, S. Vrudhula
Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.
{"title":"Integration of threshold logic gates with RRAM devices for energy efficient and robust operation","authors":"Jinghua Yang, Niranjan S. Kulkarni, Shimeng Yu, S. Vrudhula","doi":"10.1145/2770287.2770298","DOIUrl":"https://doi.org/10.1145/2770287.2770298","url":null,"abstract":"Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"60 1","pages":"39-44"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77904550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the current advanced technology nodes, an accurate, yet fast reliability analysis is needed at design time, to enable the comparison between different circuit architectures, and thus a reliability-aware design and synthesis process. To this end we propose a reliability assessment framework that is able to estimate more accurately the circuit reliability and which can be applied to large-scale circuit settings, by: (i) taking into account the circuit topology (and implicitly its reconvergent fanouts), the input vectors, the environmental conditions and fault scenarios, (ii) employing a range of probabilities, i.e., a Probability Density Function (PDF), instead of hitherto single probability value, in order to quantify the circuit reliability, (iii) employing variational inference, to derive the circuit primary output PDFs, given its primary inputs PDFs, and (iv) adapting the traditional variational inference approach to exploit the peculiarities of the probabilistic model afferent to logic circuits, for convergence speed improvements and thus applicability in large scale circuits settings.
{"title":"Probability density function based reliability evaluation of large-scale ICs","authors":"N. C. Laurenciu, S. Cotofana","doi":"10.1145/2770287.2770326","DOIUrl":"https://doi.org/10.1145/2770287.2770326","url":null,"abstract":"For the current advanced technology nodes, an accurate, yet fast reliability analysis is needed at design time, to enable the comparison between different circuit architectures, and thus a reliability-aware design and synthesis process. To this end we propose a reliability assessment framework that is able to estimate more accurately the circuit reliability and which can be applied to large-scale circuit settings, by: (i) taking into account the circuit topology (and implicitly its reconvergent fanouts), the input vectors, the environmental conditions and fault scenarios, (ii) employing a range of probabilities, i.e., a Probability Density Function (PDF), instead of hitherto single probability value, in order to quantify the circuit reliability, (iii) employing variational inference, to derive the circuit primary output PDFs, given its primary inputs PDFs, and (iv) adapting the traditional variational inference approach to exploit the peculiarities of the probabilistic model afferent to logic circuits, for convergence speed improvements and thus applicability in large scale circuits settings.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"108 1","pages":"157-162"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78091152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Magnus Själander, Nina Shariati Nilsson, S. Kaxiras
CMOS scaling is near its end but new emerging devices are being developed to replace CMOS. These devices have different features than CMOS, such as the possibility for multi-value logic, which present new opportunities when designing computer systems. In this work we investigate the use of multi-value devices to design a cache that can tune the amount of resources used to store application data. We leverage work on approximate computing to store data that are not application critical in a compact quaternary format while critical data is stored in a more error resilient binary format.
{"title":"A tunable cache for approximate computing","authors":"Magnus Själander, Nina Shariati Nilsson, S. Kaxiras","doi":"10.1145/2770287.2770309","DOIUrl":"https://doi.org/10.1145/2770287.2770309","url":null,"abstract":"CMOS scaling is near its end but new emerging devices are being developed to replace CMOS. These devices have different features than CMOS, such as the possibility for multi-value logic, which present new opportunities when designing computer systems. In this work we investigate the use of multi-value devices to design a cache that can tune the amount of resources used to store application data. We leverage work on approximate computing to store data that are not application critical in a compact quaternary format while critical data is stored in a more error resilient binary format.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"21 1","pages":"88-89"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85335534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The versatility of nanodevices dynamics may allow original architectures for computation but care should be taken to handle fluctuations arising at this scale. In the network of oscillatory units which we propose, bistability with down-quiescent and up-oscillatory states enable tolerance to noise in storage and retrieval dynamics for patterns or sequences. We illustrate this by simulations of the stochastic differential equations for a network with connectivity corresponding to stored patterns.
{"title":"Robust sequence storage in bistable oscillators","authors":"David Colliaux, P. Bessière, J. Droulez","doi":"10.1145/2770287.2770310","DOIUrl":"https://doi.org/10.1145/2770287.2770310","url":null,"abstract":"The versatility of nanodevices dynamics may allow original architectures for computation but care should be taken to handle fluctuations arising at this scale. In the network of oscillatory units which we propose, bistability with down-quiescent and up-oscillatory states enable tolerance to noise in storage and retrieval dynamics for patterns or sequences. We illustrate this by simulations of the stochastic differential equations for a network with connectivity corresponding to stored patterns.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"1 1","pages":"90-91"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79485976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Emerging nanotechnologies have the potential to completely revolutionize the semiconductor industry by providing “more than Moore” capabilities. Instead of trying to compete in areas where conventional CMOS is still dominant, such as digital processing, emerging technologies can provide a perfect complement to CMOS in areas where conventional solutions are not scaling, such as memory, interconnect, analog and mixed-signal, and RF. This paper focuses on the application of such an emerging nanotechnology, Spin Torque Nano Oscillators (STNOs), for on-chip mixed-signal and RF applications. Bulky and power-hungry CMOS active (e.g. oscillators and amplifiers) and passive (e.g. capacitors and spiral inductors) elements can be replaced by single STNO nanodevice with improved overall metrics: small footprint of the order of 100nm on a side, low power, high-Q, tunability, etc. Additionally, since STNOs fundamentally use similar materials and geometries as Spin Torque Transfer RAM (STT-RAM), they can be readily integrated on chip and can benefit from all advances in that field. This paper proposes a new STNO device structure appropriate for on-chip mixed-signal and RF applications, as well as several hybrid STNO/CMOS circuits that take advantage of the STNO device characteristics to obtain desired behaviors, such as frequency generation, pass and notch filters, etc.
{"title":"Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future","authors":"M. Stan, M. Kabir, S. Wolf, Jiwei Lu","doi":"10.1145/2770287.2770296","DOIUrl":"https://doi.org/10.1145/2770287.2770296","url":null,"abstract":"Emerging nanotechnologies have the potential to completely revolutionize the semiconductor industry by providing “more than Moore” capabilities. Instead of trying to compete in areas where conventional CMOS is still dominant, such as digital processing, emerging technologies can provide a perfect complement to CMOS in areas where conventional solutions are not scaling, such as memory, interconnect, analog and mixed-signal, and RF. This paper focuses on the application of such an emerging nanotechnology, Spin Torque Nano Oscillators (STNOs), for on-chip mixed-signal and RF applications. Bulky and power-hungry CMOS active (e.g. oscillators and amplifiers) and passive (e.g. capacitors and spiral inductors) elements can be replaced by single STNO nanodevice with improved overall metrics: small footprint of the order of 100nm on a side, low power, high-Q, tunability, etc. Additionally, since STNOs fundamentally use similar materials and geometries as Spin Torque Transfer RAM (STT-RAM), they can be readily integrated on chip and can benefit from all advances in that field. This paper proposes a new STNO device structure appropriate for on-chip mixed-signal and RF applications, as well as several hybrid STNO/CMOS circuits that take advantage of the STNO device characteristics to obtain desired behaviors, such as frequency generation, pass and notch filters, etc.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"21 1","pages":"37-38"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82633097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Zografos, P. Raghavan, L. Amarù, B. Sorée, R. Lauwereins, I. Radu, D. Verkest, A. Thean
Spin Wave Devices (SWDs) are promising candidates for scaling electronics beyond the domain of CMOS. In contrast to traditional charge-based technologies, SWDs rely on propagating oscillation of magnetization as information carrier. Thanks to the intrinsic wave computation capability of these devices, the majority gate is implemented with low physical re-sources. Being more expressive than standard NAND/NOR gates, the compact majority gate pushes further the expected benefits of SWDs over CMOS. In this paper, we present a realistic design framework for SWD-based logic circuits, accounting for both limitations and advantages deriving from the new technology. We use a majority logic synthesis tool to fully exploit the SWD functionality. In the experiments, we focus on the estimated area. We consider several arithmetic-intensive benchmarks, and compare their SWD area with three state-of-the-art CMOS nodes. We show that an area reduction up to 11.3x is possible, as compared to a 10nm CMOS technology.
{"title":"System-level assessment and area evaluation of Spin Wave logic circuits","authors":"O. Zografos, P. Raghavan, L. Amarù, B. Sorée, R. Lauwereins, I. Radu, D. Verkest, A. Thean","doi":"10.1145/2770287.2770294","DOIUrl":"https://doi.org/10.1145/2770287.2770294","url":null,"abstract":"Spin Wave Devices (SWDs) are promising candidates for scaling electronics beyond the domain of CMOS. In contrast to traditional charge-based technologies, SWDs rely on propagating oscillation of magnetization as information carrier. Thanks to the intrinsic wave computation capability of these devices, the majority gate is implemented with low physical re-sources. Being more expressive than standard NAND/NOR gates, the compact majority gate pushes further the expected benefits of SWDs over CMOS. In this paper, we present a realistic design framework for SWD-based logic circuits, accounting for both limitations and advantages deriving from the new technology. We use a majority logic synthesis tool to fully exploit the SWD functionality. In the experiments, we focus on the estimated area. We consider several arithmetic-intensive benchmarks, and compare their SWD area with three state-of-the-art CMOS nodes. We show that an area reduction up to 11.3x is possible, as compared to a 10nm CMOS technology.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"6 1","pages":"25-30"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89111482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Khasanvis, Mostafizur Rahman, S. Rajapandian, C. A. Moritz
We present a novel multi-valued computation framework called Wave Interference Functions (WIF), based on emerging non-equilibrium wave phenomenon such as spin waves. WIF offers new features for data representation and computation, which can be game changing for post-CMOS integrated circuits (ICs). Information encoding wave attributes inherently leads to multi-dimensional multi-valued data representation and communication. Multi-valued computation is natively supported with wave interactions, such as wave superposition or interference. We introduce the concept of a multi-valued Interference Function that is more sophisticated than conventional Boolean and Majority functions, leading to compact circuits for logic. We present WIF implementation of multi-valued operators to realize any desired logic/arithmetic function using the Interference Function. We evaluate 2-digit to 16-digit quaternary (radix-4) full adder designs with WIF operators in terms of power, performance and area. Estimates indicate up to 63x higher density, 884x lower power and 3x better performance when compared to equivalent 45nm CMOS adders. WIF features completely change conventional assumptions on circuit design, opening new avenues to implement future nanoscale ICs for general purpose processing and other applications inherently suited to multi-valued computation.
{"title":"Wave-based multi-valued computation framework","authors":"S. Khasanvis, Mostafizur Rahman, S. Rajapandian, C. A. Moritz","doi":"10.1145/2770287.2770330","DOIUrl":"https://doi.org/10.1145/2770287.2770330","url":null,"abstract":"We present a novel multi-valued computation framework called Wave Interference Functions (WIF), based on emerging non-equilibrium wave phenomenon such as spin waves. WIF offers new features for data representation and computation, which can be game changing for post-CMOS integrated circuits (ICs). Information encoding wave attributes inherently leads to multi-dimensional multi-valued data representation and communication. Multi-valued computation is natively supported with wave interactions, such as wave superposition or interference. We introduce the concept of a multi-valued Interference Function that is more sophisticated than conventional Boolean and Majority functions, leading to compact circuits for logic. We present WIF implementation of multi-valued operators to realize any desired logic/arithmetic function using the Interference Function. We evaluate 2-digit to 16-digit quaternary (radix-4) full adder designs with WIF operators in terms of power, performance and area. Estimates indicate up to 63x higher density, 884x lower power and 3x better performance when compared to equivalent 45nm CMOS adders. WIF features completely change conventional assumptions on circuit design, opening new avenues to implement future nanoscale ICs for general purpose processing and other applications inherently suited to multi-valued computation.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"32 1","pages":"171-176"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74566473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Davide Giri, M. Vacca, G. Causapruno, Wenjing Rao, M. Graziano, M. Zamboni
Among emerging technologies Quantum dot Cellular Automata (QCA) plays a fundamental role. Its magnetic version, normally called NanoMagnet Logic (NML), is particularly interesting thanks to the ability to work at room temperature and to mix logic and memory in the same device. Magnetic circuits have also a potential very low power consumption. Unfortunately classic NML circuits are normally driven (clocked) with a current generating a clocked magnetic field, nullifying the possibility to actually obtain low power circuits. We have recently developed a technology-friendly solution, the MagnetoElastic NML (ME-NML), where magnetic circuits are driven through an electric field, and not with a current, drastically reducing the power consumption. In this paper we start to explore the architectural consequences of this new magnetic technology. The analysis is performed using as a benchmark a Galois multiplier, a systolic architecture particularly suited for QCA and NML technologies. The layout is precisely described and the resulting circuit is modeled and simulated using VHDL language. The obtained results are remarkable. The circuit area is reduced by 4 times compared to classic NML approach. This, coupled with the intrinsic lower power consumption due to different clock, leads to a 50 times reduction of power absorption. Moreover the particular structure of magnetoelastic NML allows to define a library of standard cells that can be easily used by designers and automatic layout tools to design circuits, greatly improving future research in this field.
{"title":"A standard cell approach for MagnetoElastic NML circuits","authors":"Davide Giri, M. Vacca, G. Causapruno, Wenjing Rao, M. Graziano, M. Zamboni","doi":"10.1145/2770287.2770304","DOIUrl":"https://doi.org/10.1145/2770287.2770304","url":null,"abstract":"Among emerging technologies Quantum dot Cellular Automata (QCA) plays a fundamental role. Its magnetic version, normally called NanoMagnet Logic (NML), is particularly interesting thanks to the ability to work at room temperature and to mix logic and memory in the same device. Magnetic circuits have also a potential very low power consumption. Unfortunately classic NML circuits are normally driven (clocked) with a current generating a clocked magnetic field, nullifying the possibility to actually obtain low power circuits. We have recently developed a technology-friendly solution, the MagnetoElastic NML (ME-NML), where magnetic circuits are driven through an electric field, and not with a current, drastically reducing the power consumption. In this paper we start to explore the architectural consequences of this new magnetic technology. The analysis is performed using as a benchmark a Galois multiplier, a systolic architecture particularly suited for QCA and NML technologies. The layout is precisely described and the resulting circuit is modeled and simulated using VHDL language. The obtained results are remarkable. The circuit area is reduced by 4 times compared to classic NML approach. This, coupled with the intrinsic lower power consumption due to different clock, leads to a 50 times reduction of power absorption. Moreover the particular structure of magnetoelastic NML allows to define a library of standard cells that can be easily used by designers and automatic layout tools to design circuits, greatly improving future research in this field.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"44 1","pages":"65-70"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75587313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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