Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808148
G. Dayananda, C. Rai, A. Jayarama, Hyun Jae Kim
Amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin film transistors (TFTs) were fabricated on 1737 corning glass are investigated effects of 8-MeV electron irradiation with different irradiation dosage on the different parameters of a-IGZO thin film transistors. The thin film transistors show slight degradation for dosage greater than 1kGy. After radiation, a decrease of saturation electron mobility () was observed. The experimental results show threshold voltage(Vth) and Ion /Ioff ratio were increased after radiation. Initially the sub threshold swing(SS) increased and remained constant after 10kGy electron irradiation. However there is no drastic variation in device parameters, hence these TFTs can be used in spacecraft environments and nuclear plants.
{"title":"Study of radiation resistance property of a — IGZO thin film transistors","authors":"G. Dayananda, C. Rai, A. Jayarama, Hyun Jae Kim","doi":"10.1109/RTEICT.2016.7808148","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808148","url":null,"abstract":"Amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin film transistors (TFTs) were fabricated on 1737 corning glass are investigated effects of 8-MeV electron irradiation with different irradiation dosage on the different parameters of a-IGZO thin film transistors. The thin film transistors show slight degradation for dosage greater than 1kGy. After radiation, a decrease of saturation electron mobility () was observed. The experimental results show threshold voltage(Vth) and Ion /Ioff ratio were increased after radiation. Initially the sub threshold swing(SS) increased and remained constant after 10kGy electron irradiation. However there is no drastic variation in device parameters, hence these TFTs can be used in spacecraft environments and nuclear plants.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"40 1","pages":"1816-1819"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73823751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808194
Jikku Jeemon
This article describes an 8-bit RISC processor design using Verilog Hardware Description Language (HDL) on FPGA board. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains only 34 instructions, which is very simple, easy to learn and compact. The proposed processor has 8-bit ALU, Two 8-bit I/O ports, serial-in/serial-out ports, Eight 8-bit general-purpose registers, 4-bit flag register and priority based three vectored interrupts. Another advantage of the proposed processor is that it can execute programs with up to 262,144 instructions long, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 3E Starter Board FPGA with 0.0517μs instruction cycle.
本文介绍了一种基于Verilog硬件描述语言(HDL)的8位RISC处理器在FPGA板上的设计。该处理器采用哈佛体系结构设计，具有独立的指令和数据存储器。该处理器的显著特点是流水线，用于提高性能，这样在每个时钟周期将执行一条指令。指令集的另一个重要特点是指令集只包含34条指令，非常简单、易学、紧凑。该处理器具有8位ALU、2个8位I/O端口、串行输入/串行输出端口、8个8位通用寄存器、4位标志寄存器和基于优先级的3个矢量中断。所提出的处理器的另一个优点是，它可以执行长达262,144条指令的程序，这样任何实际的程序都可以装入其中。该处理器在Xilinx Spartan 3E Starter Board FPGA上进行了物理验证，指令周期为0.0517μs。
{"title":"Pipelined 8-bit RISC processor design using Verilog HDL on FPGA","authors":"Jikku Jeemon","doi":"10.1109/RTEICT.2016.7808194","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808194","url":null,"abstract":"This article describes an 8-bit RISC processor design using Verilog Hardware Description Language (HDL) on FPGA board. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains only 34 instructions, which is very simple, easy to learn and compact. The proposed processor has 8-bit ALU, Two 8-bit I/O ports, serial-in/serial-out ports, Eight 8-bit general-purpose registers, 4-bit flag register and priority based three vectored interrupts. Another advantage of the proposed processor is that it can execute programs with up to 262,144 instructions long, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 3E Starter Board FPGA with 0.0517μs instruction cycle.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"108 1","pages":"2023-2027"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73925841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7807777
Hiroshama Nain, Urvashi Jadon, V. Mishra
Non-Linear effects in Optical networks are occurred due to the refractive index of the optical transmitting medium depending on the intensity of light. One of the most commonly occurred non-linear effect in optical network is the Self phase modulation (SPM) phenomenon. The impact of self-phase modulation instigates distortions to the optical signal transmission over desired configuration of spectrally systematic wavelength division multiplexing (WDM) optical fiber transmission system. Here we imitated the results for fiber optical network on different lengths of fiber. We investigate the results on the basis of Q-factor, jitter, BER at multiple values of dispersion and bit rate. We had analyzed the variation in optical dispersion from -8ps/ns/km to 8ps/ns/km and had realized the result through eye diagram. We have observed the optical spectrum for input and output from of signal mediation. For multiple values of fiber length, Data rate, emission frequency we have examine the BER and Q-factor. The outcome is analyzed using optical software tool i.e. OPTSIM.
{"title":"Evaluation and analysis of non-linear effect in WDM optical network","authors":"Hiroshama Nain, Urvashi Jadon, V. Mishra","doi":"10.1109/RTEICT.2016.7807777","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807777","url":null,"abstract":"Non-Linear effects in Optical networks are occurred due to the refractive index of the optical transmitting medium depending on the intensity of light. One of the most commonly occurred non-linear effect in optical network is the Self phase modulation (SPM) phenomenon. The impact of self-phase modulation instigates distortions to the optical signal transmission over desired configuration of spectrally systematic wavelength division multiplexing (WDM) optical fiber transmission system. Here we imitated the results for fiber optical network on different lengths of fiber. We investigate the results on the basis of Q-factor, jitter, BER at multiple values of dispersion and bit rate. We had analyzed the variation in optical dispersion from -8ps/ns/km to 8ps/ns/km and had realized the result through eye diagram. We have observed the optical spectrum for input and output from of signal mediation. For multiple values of fiber length, Data rate, emission frequency we have examine the BER and Q-factor. The outcome is analyzed using optical software tool i.e. OPTSIM.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"64 1","pages":"36-39"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85852040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A dual layer stacked swastika shaped antenna with a meta-material based ground structure at frequency 11.65 GHz and for the frequency range of 6-16 GHz is presented in this paper. An air gap is used between two dielectrics whereas an inverted patch configuration is employed to achieve wideband characteristics. The proposed design exhibits maximum gain of 5.63 dB and maximum return loss of 29.08 dB at 11.65 GHz and 7.16 GHz respectively. The simulation has been carried out using HFSS software.
{"title":"Performance analysis of dual layer stacked swastika shaped patch antenna with a meta-material structured ground plane for satellite communication and radar applications","authors":"Devesh Kumar, Vedant Malik, Janhvi Yadav, Shantnu Atree, Sindhu Hak Gupta","doi":"10.1109/RTEICT.2016.7807836","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807836","url":null,"abstract":"A dual layer stacked swastika shaped antenna with a meta-material based ground structure at frequency 11.65 GHz and for the frequency range of 6-16 GHz is presented in this paper. An air gap is used between two dielectrics whereas an inverted patch configuration is employed to achieve wideband characteristics. The proposed design exhibits maximum gain of 5.63 dB and maximum return loss of 29.08 dB at 11.65 GHz and 7.16 GHz respectively. The simulation has been carried out using HFSS software.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"31 1","pages":"327-331"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88514215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7807771
Vanitha Guda, Suresh Kumar Sanampudi
The notion of events plays a crucial role in narrative texts. Events are the situations that happen or occur at a particular place and time. Extraction and representation of event has a significant role in many of the natural language text and applications like text summarization, question answering systems etc. Several methods were developed so far but they addressed the problem in domain aspect point of view. In this paper we demonstrate a rule based system for event extraction which is generic in nature. A generic rules based event extraction algorithm was developed that maps the framed rules to derive the events from natural language text. Experiments were conducted on the MUC data set and the results are found to be encouraging.
{"title":"Rules based event extraction from natural language text","authors":"Vanitha Guda, Suresh Kumar Sanampudi","doi":"10.1109/RTEICT.2016.7807771","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807771","url":null,"abstract":"The notion of events plays a crucial role in narrative texts. Events are the situations that happen or occur at a particular place and time. Extraction and representation of event has a significant role in many of the natural language text and applications like text summarization, question answering systems etc. Several methods were developed so far but they addressed the problem in domain aspect point of view. In this paper we demonstrate a rule based system for event extraction which is generic in nature. A generic rules based event extraction algorithm was developed that maps the framed rules to derive the events from natural language text. Experiments were conducted on the MUC data set and the results are found to be encouraging.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"42 1","pages":"9-13"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87381169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808163
G. Ram, D. S. Rani, R. Balasaikesava, K. B. Sindhuri
The structure of modified tree multipliers with different adders is presented. Multiplication is an important fundamental arithmetic operation in all microprocessor circuits and algorithms. Currently the speed of multipliers is limited by the speed of adders used for partial products addition. In this paper Conventional Array Multiplier and Dadda Multiplier are compared with the Wallace multiplier in terms of delay. Further a proposed sixteen bit Wallace multiplier is implemented by using Carry Select Adder (CSLA) and Binary to Excess -1 Converter (BEC) adder. The delay for Wallace multiplier using CSLA is less when compared to Wallace multiplier with BEC. These multipliers are coded in Verilog HDL, simulated and synthesized by using XILINX software 12.2 on Spartan 3E FPGA device xc3s500-5fg320.
给出了带有不同加法器的改进树乘法器的结构。乘法运算是所有微处理器电路和算法中重要的基本运算。目前，乘法器的运算速度受到部分乘积加法运算速度的限制。本文比较了传统阵列乘法器和达达乘法器与华莱士乘法器的时延。采用进位选择加法器(CSLA)和二进制到超-1转换器(BEC)加法器实现了16位华莱士乘法器。与使用BEC的华莱士乘法器相比，使用CSLA的华莱士乘法器延迟更小。这些乘法器用Verilog HDL编码，在Spartan 3E FPGA器件xc3s500-5fg320上使用XILINX软件12.2进行仿真和合成。
{"title":"Design of delay efficient modified 16 bit Wallace multiplier","authors":"G. Ram, D. S. Rani, R. Balasaikesava, K. B. Sindhuri","doi":"10.1109/RTEICT.2016.7808163","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808163","url":null,"abstract":"The structure of modified tree multipliers with different adders is presented. Multiplication is an important fundamental arithmetic operation in all microprocessor circuits and algorithms. Currently the speed of multipliers is limited by the speed of adders used for partial products addition. In this paper Conventional Array Multiplier and Dadda Multiplier are compared with the Wallace multiplier in terms of delay. Further a proposed sixteen bit Wallace multiplier is implemented by using Carry Select Adder (CSLA) and Binary to Excess -1 Converter (BEC) adder. The delay for Wallace multiplier using CSLA is less when compared to Wallace multiplier with BEC. These multipliers are coded in Verilog HDL, simulated and synthesized by using XILINX software 12.2 on Spartan 3E FPGA device xc3s500-5fg320.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"40 1","pages":"1887-1891"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81487441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808180
Suraj K. Mankani, N. S. Kumar, Prasad R. Dongrekar, Shreekant Sajjanar, Mohana, H. V. Ravish Aradhya
In the recent years, object detection and tracking has become an integral part of various applications such as Surveillance system, Vehicle navigation, and autonomous robot navigation. Especially in the field of surveillance system it has gained greater significance than ever before due to the recent terror activities taking place all over the world. Many efforts have been made to make the system automated in order to decrease the complexity and to increase the ease with which it can be implemented. The paper describes the implementation of Object Detection and Tracking for the surveillance system on DSP board Embest Dev Kit 8500D using Modified Background Subtraction algorithm. The camera used in the system, Microsoft LifeCam HD 3000 camera, operates at a speed of 30fps. The DSP board acts as a standalone system with Linux based Angstrom Operating System (OS) installed in it and it is programmed in C++ language integrated with OpenCV library. Contrary to the conventional Background Subtraction algorithm where a fixed reference frame is subtracted from incoming frame, Frame Differencing technique is used in this paper in which two consecutive frames are subtracted from one another to remove the stationary background. The design is successfully implemented to detect and track the object with a minimum time delay.
近年来，目标检测与跟踪已成为监控系统、车辆导航和自主机器人导航等各种应用中不可或缺的一部分。特别是在监视系统领域，由于最近世界各地发生的恐怖活动，它比以往任何时候都具有更大的意义。为了降低系统的复杂性，增加实现系统的便利性，已经做出了许多努力使系统自动化。本文介绍了在DSP板Embest Dev Kit 8500D上利用改进的背景减法算法实现监控系统的目标检测与跟踪。系统中使用的摄像头是微软LifeCam HD 3000摄像头，运行速度为30fps。DSP板作为一个独立的系统，安装了基于Linux的Angstrom操作系统(OS)，使用c++语言结合OpenCV库进行编程。与传统的背景减法算法从输入帧中减去固定的参考帧不同，本文采用帧差分技术，将两个连续的帧相互减去以去除静止的背景。该设计成功地实现了以最小的时间延迟检测和跟踪目标。
{"title":"Real-time implementation of object detection and tracking on DSP for video surveillance applications","authors":"Suraj K. Mankani, N. S. Kumar, Prasad R. Dongrekar, Shreekant Sajjanar, Mohana, H. V. Ravish Aradhya","doi":"10.1109/RTEICT.2016.7808180","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808180","url":null,"abstract":"In the recent years, object detection and tracking has become an integral part of various applications such as Surveillance system, Vehicle navigation, and autonomous robot navigation. Especially in the field of surveillance system it has gained greater significance than ever before due to the recent terror activities taking place all over the world. Many efforts have been made to make the system automated in order to decrease the complexity and to increase the ease with which it can be implemented. The paper describes the implementation of Object Detection and Tracking for the surveillance system on DSP board Embest Dev Kit 8500D using Modified Background Subtraction algorithm. The camera used in the system, Microsoft LifeCam HD 3000 camera, operates at a speed of 30fps. The DSP board acts as a standalone system with Linux based Angstrom Operating System (OS) installed in it and it is programmed in C++ language integrated with OpenCV library. Contrary to the conventional Background Subtraction algorithm where a fixed reference frame is subtracted from incoming frame, Frame Differencing technique is used in this paper in which two consecutive frames are subtracted from one another to remove the stationary background. The design is successfully implemented to detect and track the object with a minimum time delay.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"31 1","pages":"1965-1969"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75016453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7807946
Nayan Modhave, Y. Karuna, Sourabh Tonde
This paper proposes an algorithm for matrix wiener filter for speech processing in case of hearing aids. Hearing aid (HA) devices currently used are less efficient as environmental noise already added into speech signal corrupts it and heard by listener. Introducing wiener filter in HA device allows reducing noise to particular level. By increasing number of secondary channels can enhance the performance of the device. Matrix wiener filter is a technique which considers matrix combination of speech and noise correlations and has better performance than multichannel wiener filter. A multi input multi output (MIMO) system having multiple target speech signals is used, it utilizes matrix wiener filter for nullifying noise in speech which estimates the speech coming towards listener. Wiener matrix coefficients are calculated from speech and noise correlation matrices. Simulation results prove that matrix wiener filter performs better compared to multichannel and single channel wiener filter.
{"title":"Design of matrix wiener filter for noise reduction and speech enhancement in hearing aids","authors":"Nayan Modhave, Y. Karuna, Sourabh Tonde","doi":"10.1109/RTEICT.2016.7807946","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807946","url":null,"abstract":"This paper proposes an algorithm for matrix wiener filter for speech processing in case of hearing aids. Hearing aid (HA) devices currently used are less efficient as environmental noise already added into speech signal corrupts it and heard by listener. Introducing wiener filter in HA device allows reducing noise to particular level. By increasing number of secondary channels can enhance the performance of the device. Matrix wiener filter is a technique which considers matrix combination of speech and noise correlations and has better performance than multichannel wiener filter. A multi input multi output (MIMO) system having multiple target speech signals is used, it utilizes matrix wiener filter for nullifying noise in speech which estimates the speech coming towards listener. Wiener matrix coefficients are calculated from speech and noise correlation matrices. Simulation results prove that matrix wiener filter performs better compared to multichannel and single channel wiener filter.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"81 1","pages":"843-847"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73579880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7807948
K. Sharmila, Anjali, S. Pattar
Device-to-Device (D2D) communication is one of the most popular topic in the upcoming device communication. D2D provides access to services through direct or indirect connection path with neighboring devices with or/and without ENodeB (eNB) assistance. Some of the problems faced in this case are discovering process of neighbor user equipment (UE) and services, as well as designing suitable and secure protocols for D2D communication. In this paper, we propose a sidelink based D2D communication, wherein a separate unlicensed band apart from uplink and downlink is considered to be allocated for sidelink and is functional without the presence of eNB. In this paper we present a detailed study of operational procedures at Radio Resource Control (RRC) and Media Access Control (MAC) layers for sidelink based D2D communication along with this various messages handled for D2D communication for both scenarios using sidelink has been discussed. Two scenarios of D2D communications have been considered-for both UE's in-coverage and both UE's' out-of-coverage. The client side architecture of D2D communication with respect to RRC and MAC layers is also presented.
{"title":"RRC and MAC call flow procedures for D2D communication through sidelink in LTE-A","authors":"K. Sharmila, Anjali, S. Pattar","doi":"10.1109/RTEICT.2016.7807948","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807948","url":null,"abstract":"Device-to-Device (D2D) communication is one of the most popular topic in the upcoming device communication. D2D provides access to services through direct or indirect connection path with neighboring devices with or/and without ENodeB (eNB) assistance. Some of the problems faced in this case are discovering process of neighbor user equipment (UE) and services, as well as designing suitable and secure protocols for D2D communication. In this paper, we propose a sidelink based D2D communication, wherein a separate unlicensed band apart from uplink and downlink is considered to be allocated for sidelink and is functional without the presence of eNB. In this paper we present a detailed study of operational procedures at Radio Resource Control (RRC) and Media Access Control (MAC) layers for sidelink based D2D communication along with this various messages handled for D2D communication for both scenarios using sidelink has been discussed. Two scenarios of D2D communications have been considered-for both UE's in-coverage and both UE's' out-of-coverage. The client side architecture of D2D communication with respect to RRC and MAC layers is also presented.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"62 1","pages":"851-854"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74070976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808071
S. K. L. V. Sai Prakash, A. P. Kumar
Green communication (energy efficient), with increasing capacity in mobile networks, mainly depends on energy used by relay nodes, placement of relay nodes and total number of relays. The range extension of the network with all the three considerations lead to an energy efficient communication with achievable data rates and less bit error rate (BER). Initial part of the paper explores efficient single node placement in/on a circle between source and sink. Later, it is extended to an optimal placement on a one dimensional plane to provide a better network connectivity. Mathematical analysis for optimal placement of the relay nodes and the number of relays required for energy efficient communication is shown. The same is simulated using GNU Octave and the results are presented for optimal number of hops and optimal placement. From our results obtained from single relay in/on a circle, the relay communication is energy efficient if the relay nodes makes an angle of π. In case of multi-hop relay, communication energy vs number of hops vs user mobility is presented.
{"title":"Relay based green communication in mobile networks: 1-dimension case","authors":"S. K. L. V. Sai Prakash, A. P. Kumar","doi":"10.1109/RTEICT.2016.7808071","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808071","url":null,"abstract":"Green communication (energy efficient), with increasing capacity in mobile networks, mainly depends on energy used by relay nodes, placement of relay nodes and total number of relays. The range extension of the network with all the three considerations lead to an energy efficient communication with achievable data rates and less bit error rate (BER). Initial part of the paper explores efficient single node placement in/on a circle between source and sink. Later, it is extended to an optimal placement on a one dimensional plane to provide a better network connectivity. Mathematical analysis for optimal placement of the relay nodes and the number of relays required for energy efficient communication is shown. The same is simulated using GNU Octave and the results are presented for optimal number of hops and optimal placement. From our results obtained from single relay in/on a circle, the relay communication is energy efficient if the relay nodes makes an angle of π. In case of multi-hop relay, communication energy vs number of hops vs user mobility is presented.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"56 1","pages":"1447-1451"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74671479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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