Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942569
Sweta V. Munkanpalli, S. Sagat, M. Mali
Many research activities have taken place in the field of brain computer interface based on EEG signal. The main aim of this paper is to give a good potential for disabled people where driving is impossible task for them. This can be achieved mainly by four steps i.e signal acquisition, signal preprocessing, feature extraction and classification using MATLAB. For feature extraction DWT method and for classification SVM classifier is used. After the classification the commands are executed on Arduino board (model UNO R3). The experimental result showed that the robot can be controlled successfully.
{"title":"Design and development of EEG controlled mobile robots","authors":"Sweta V. Munkanpalli, S. Sagat, M. Mali","doi":"10.1109/ICAECCT.2016.7942569","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942569","url":null,"abstract":"Many research activities have taken place in the field of brain computer interface based on EEG signal. The main aim of this paper is to give a good potential for disabled people where driving is impossible task for them. This can be achieved mainly by four steps i.e signal acquisition, signal preprocessing, feature extraction and classification using MATLAB. For feature extraction DWT method and for classification SVM classifier is used. After the classification the commands are executed on Arduino board (model UNO R3). The experimental result showed that the robot can be controlled successfully.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"14 1","pages":"133-138"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89087696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942560
N. Shinde, D. S. Bhosale
Real-time 3D imagery has gained special attention in many Champaign such as computer vision, virtual reality. The third dimension plays a decisive role in the analysis of dynamic or static environments. Therefore, developing a reliable real-time depth imaging system is very challenging. The depth information allows a much better analysis of the environment. This proposed system is a 3D scanner system used to obtain 3D using structured light from sequence of 2D images. This paper describes different stages of development of 3D scanner prototype, both from hardware and software point of view. Aspects such as extracting ROI, edge detection, distance transformation, and plotting the element on 3D platform are considered towards an optimal implementation of this 3D scanner. The 3D scanner composed of simple hardware such as stepper motor with rotating platform, motor driver, Arduino, an uvc camera, and proper lighting system. On software part Linux operating system is used along with python as programming language. The libraries such as Open CV, numpy, matplotlib, tkinter are used for development.
{"title":"Development of 3D reconstruction system","authors":"N. Shinde, D. S. Bhosale","doi":"10.1109/ICAECCT.2016.7942560","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942560","url":null,"abstract":"Real-time 3D imagery has gained special attention in many Champaign such as computer vision, virtual reality. The third dimension plays a decisive role in the analysis of dynamic or static environments. Therefore, developing a reliable real-time depth imaging system is very challenging. The depth information allows a much better analysis of the environment. This proposed system is a 3D scanner system used to obtain 3D using structured light from sequence of 2D images. This paper describes different stages of development of 3D scanner prototype, both from hardware and software point of view. Aspects such as extracting ROI, edge detection, distance transformation, and plotting the element on 3D platform are considered towards an optimal implementation of this 3D scanner. The 3D scanner composed of simple hardware such as stepper motor with rotating platform, motor driver, Arduino, an uvc camera, and proper lighting system. On software part Linux operating system is used along with python as programming language. The libraries such as Open CV, numpy, matplotlib, tkinter are used for development.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"28 1","pages":"82-85"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85941743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942572
M. Ravi, Shashidhara Tg, S. S, S. S
The computational resources of a System on Chip (SoC) accompanied by their compact design tailors to the needs of current medical devices where there is a necessity for visualizing and performing diagnosis in real-time. Currently we are developing a Small Organ Imaging Gamma Camera (SOIGC) for imaging small organs with higher spatial and energy resolution. We present here a novel “SoC” based real-time medical image processing tool for evaluation and quantification of Thyroid Uptake Ratio derived from Single Photon Emission Computed Tomography (SPECT).The Thyroid Uptake Ratio is a diagnostic index used extensively to assess Thyroid's hormonal activity obtained by quantifying the intensity of the segmented SPECT images which are conventionally done on expensive propriety tools. In contrast to these, our lower cost SoC tool based on DSP architecture offers a higher speed image segmentation process with co-relating performance. Thus, it also eliminates the need for higher computing resources on the host machine by using a Hardware accelerator called “Pipeline Vision Processor” of an optimized Dual Core Digital Signal Processor. This architecture offers a high performance enhanced infrastructure with large on-chip memory and reduces the overall bandwidth requirement leading to accelerated imaging. We have cross-validated the performance of this tool by evaluating 27 medical case studies with thyroid medical history. As compared to diagnosis by propriety SIEMENS software or segmentation tools based on MATLAB, our hardware accelerated approach has shown a drastic reduction of computational time of about 250% with superior correlation. This SoC tool can be extended and realized for various other Medical Imaging procedures like Kidney's Glomerular Filtration Rate and Myocardial Perfusion studies of Heart.
{"title":"A novel System on Chip design for Thyroid imaging studies","authors":"M. Ravi, Shashidhara Tg, S. S, S. S","doi":"10.1109/ICAECCT.2016.7942572","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942572","url":null,"abstract":"The computational resources of a System on Chip (SoC) accompanied by their compact design tailors to the needs of current medical devices where there is a necessity for visualizing and performing diagnosis in real-time. Currently we are developing a Small Organ Imaging Gamma Camera (SOIGC) for imaging small organs with higher spatial and energy resolution. We present here a novel “SoC” based real-time medical image processing tool for evaluation and quantification of Thyroid Uptake Ratio derived from Single Photon Emission Computed Tomography (SPECT).The Thyroid Uptake Ratio is a diagnostic index used extensively to assess Thyroid's hormonal activity obtained by quantifying the intensity of the segmented SPECT images which are conventionally done on expensive propriety tools. In contrast to these, our lower cost SoC tool based on DSP architecture offers a higher speed image segmentation process with co-relating performance. Thus, it also eliminates the need for higher computing resources on the host machine by using a Hardware accelerator called “Pipeline Vision Processor” of an optimized Dual Core Digital Signal Processor. This architecture offers a high performance enhanced infrastructure with large on-chip memory and reduces the overall bandwidth requirement leading to accelerated imaging. We have cross-validated the performance of this tool by evaluating 27 medical case studies with thyroid medical history. As compared to diagnosis by propriety SIEMENS software or segmentation tools based on MATLAB, our hardware accelerated approach has shown a drastic reduction of computational time of about 250% with superior correlation. This SoC tool can be extended and realized for various other Medical Imaging procedures like Kidney's Glomerular Filtration Rate and Myocardial Perfusion studies of Heart.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"81 1","pages":"150-156"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87350057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942602
M. Desai, S. Patel
Image steganalysis finds its application in the field of digital investigation. Performance of any image steganalysis algorithm depends on sensitivity of features and amount of data hidden in an image. The goal of this paper is to evaluate the performance of DWT feature based steganalysis algorithms against various state-of-art steganography methods and variable message embedding rates. Feature selection and classification are the two main steps of any image steganalysis algorithm. This paper also presents the comparative performance of individual algorithms against different classification methods. The images used for quantitative evaluation are taken from image database BSDS500 which contains images of different types and textures. All the algorithms are implemented in MATLAB and they are evaluated against stego images generated by steganography tools available for data hiding methods like F5, BlindHide, HideSeek, DBS, DFF and LSB.
{"title":"Performance analysis of image steganalysis against message size, message type and classification methods","authors":"M. Desai, S. Patel","doi":"10.1109/ICAECCT.2016.7942602","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942602","url":null,"abstract":"Image steganalysis finds its application in the field of digital investigation. Performance of any image steganalysis algorithm depends on sensitivity of features and amount of data hidden in an image. The goal of this paper is to evaluate the performance of DWT feature based steganalysis algorithms against various state-of-art steganography methods and variable message embedding rates. Feature selection and classification are the two main steps of any image steganalysis algorithm. This paper also presents the comparative performance of individual algorithms against different classification methods. The images used for quantitative evaluation are taken from image database BSDS500 which contains images of different types and textures. All the algorithms are implemented in MATLAB and they are evaluated against stego images generated by steganography tools available for data hiding methods like F5, BlindHide, HideSeek, DBS, DFF and LSB.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"6 1","pages":"295-302"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87584119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942590
S. Jog, Vatsla Bhatnagar, Roopa Burli
Today is the world of dense EMI environment. Therefore, all the electronic equipments are constantly being exposed to EMI. While the installation of any electronic equipment, wiring may act as receiving antenna for RF signals, which may result in impairment of its operation. EMI such as lightning, electromagnetic pulses, transients, RF noise, etc get coupled to a product directly through its AC/DC power lines and input/output lines. Therefore, to protect the devices from breaking down in the presence of such interferences, there is a need for them to undergo Conducted Susceptibility testing. Music infotainment system usually installed in our vehicles may also get affected by RF noise and transients. This paper mainly lays emphasis on Conducted Susceptibility testing of Music Infotainment System conducted at General Industrial Control, Pune, India test laboratory. This model with and without RFI filter was tested for Conducted Susceptibility where transient glitch of ± 100V, 1 µs was generated and RF input of 5V and 1V RMS for a sweep of frequency band 100 KHz to 250MHz and 250 MHz to 410 MHz respectively was connected to the power supply line. Observations for any malfunctioning in the operation of equipment were made.
{"title":"Conducted susceptibility assessment of music infotainment system","authors":"S. Jog, Vatsla Bhatnagar, Roopa Burli","doi":"10.1109/ICAECCT.2016.7942590","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942590","url":null,"abstract":"Today is the world of dense EMI environment. Therefore, all the electronic equipments are constantly being exposed to EMI. While the installation of any electronic equipment, wiring may act as receiving antenna for RF signals, which may result in impairment of its operation. EMI such as lightning, electromagnetic pulses, transients, RF noise, etc get coupled to a product directly through its AC/DC power lines and input/output lines. Therefore, to protect the devices from breaking down in the presence of such interferences, there is a need for them to undergo Conducted Susceptibility testing. Music infotainment system usually installed in our vehicles may also get affected by RF noise and transients. This paper mainly lays emphasis on Conducted Susceptibility testing of Music Infotainment System conducted at General Industrial Control, Pune, India test laboratory. This model with and without RFI filter was tested for Conducted Susceptibility where transient glitch of ± 100V, 1 µs was generated and RF input of 5V and 1V RMS for a sweep of frequency band 100 KHz to 250MHz and 250 MHz to 410 MHz respectively was connected to the power supply line. Observations for any malfunctioning in the operation of equipment were made.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"20 1","pages":"240-243"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88192275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942621
Vidya A. Gaikwad, S. Babar
In advanced world, the E-Auction frameworks give the stage to offer the different sorts of auctioning with less adaptability. In normal scenario the data sharing is extreme requirement over the internet and right survey of shared data is more helpful to people and society. The sharing of information may accomplish issues like validity of information, reasonableness and insurance of data proprietor. To make E-Auction with honest and genuine data sharing, the utilization of ring signature is a guaranteed course of action where the proprietors of data demonstrate the veracity of their information which can be preceded with cloud for drawing in purposes. The significant declaration check in routine PKI (Public key Infrastructure) changes into the issue. The use of forward ring ID signature security executes the endeavors required for attestation of support. The additional third party auditor with E-auction closeout surveys and keeps the risk of dispersed cloud stockpiling affiliations.
{"title":"Forward secure E-Auction with Auditing Integrity","authors":"Vidya A. Gaikwad, S. Babar","doi":"10.1109/ICAECCT.2016.7942621","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942621","url":null,"abstract":"In advanced world, the E-Auction frameworks give the stage to offer the different sorts of auctioning with less adaptability. In normal scenario the data sharing is extreme requirement over the internet and right survey of shared data is more helpful to people and society. The sharing of information may accomplish issues like validity of information, reasonableness and insurance of data proprietor. To make E-Auction with honest and genuine data sharing, the utilization of ring signature is a guaranteed course of action where the proprietors of data demonstrate the veracity of their information which can be preceded with cloud for drawing in purposes. The significant declaration check in routine PKI (Public key Infrastructure) changes into the issue. The use of forward ring ID signature security executes the endeavors required for attestation of support. The additional third party auditor with E-auction closeout surveys and keeps the risk of dispersed cloud stockpiling affiliations.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"27 1","pages":"399-406"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82077973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942604
R. Kothe, D. Bhalke, P. P. Gutal
In this paper, we present a model to detect and distinguish individual musical instrument using different feature schemes. The proposed method considers ten musical instruments. The feature extraction scheme consists of temporal, spectral, cepstral and wavelet features. We developed k-nearest neighbor model and support vector machine model to test the performance of system. Our system achieves the 60.43% of recognition rate using k-nearest neighbor classifier with all features. A two prong approach was taken to the multiclass classification which were SVM-one against rest &SVM-one vs. one. The accuracy of SVM in both cases is 73.73% with all features using radial basis function. Using weight factor method knn shows 73% accuracy while SVM shows 90.3% accuracy using exponential kernel function. Using weight factor method knn shows 73% accuracy while SVM shows 90.3% accuracy using exponential kernel function.
{"title":"Musical instrument recognition using k-nearest neighbour and Support Vector Machine","authors":"R. Kothe, D. Bhalke, P. P. Gutal","doi":"10.1109/ICAECCT.2016.7942604","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942604","url":null,"abstract":"In this paper, we present a model to detect and distinguish individual musical instrument using different feature schemes. The proposed method considers ten musical instruments. The feature extraction scheme consists of temporal, spectral, cepstral and wavelet features. We developed k-nearest neighbor model and support vector machine model to test the performance of system. Our system achieves the 60.43% of recognition rate using k-nearest neighbor classifier with all features. A two prong approach was taken to the multiclass classification which were SVM-one against rest &SVM-one vs. one. The accuracy of SVM in both cases is 73.73% with all features using radial basis function. Using weight factor method knn shows 73% accuracy while SVM shows 90.3% accuracy using exponential kernel function. Using weight factor method knn shows 73% accuracy while SVM shows 90.3% accuracy using exponential kernel function.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"32 1","pages":"308-313"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81877765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942578
Archana Zanzane, Sayali Rawat
As FPGA's are used in cryptography, for the purpose of implementation of complex functions in various applications. Those applications includes nuclear systems, transmission-reception system as well as adaptive computing systems. Reconfigurable devices play very important role in such applications. They are commonly known as Field Programmable Gate Array. In case of mission critical application area reliability of hardware is very much important hence concept of cryptography is widely used. The system should be designed in order to remove the faults which occurs in a system. SRAM-based FPGAs has made it possible to constitute fault tolerance into systems at lower cost. Since cryptographic devices are widely employed for applications which demands to keep personal information secure and safe and collection of sensitive information. These days, such as bank cards, universal-serial-bus (USB) keys, and e-passports, studying the effect of these faults for that RSA implementation safety- and mission-critical applications is of significant importance.
{"title":"SRAM-based FPGA implementations of cryptographic circuits for fault injection and fault tolerant techniques","authors":"Archana Zanzane, Sayali Rawat","doi":"10.1109/ICAECCT.2016.7942578","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942578","url":null,"abstract":"As FPGA's are used in cryptography, for the purpose of implementation of complex functions in various applications. Those applications includes nuclear systems, transmission-reception system as well as adaptive computing systems. Reconfigurable devices play very important role in such applications. They are commonly known as Field Programmable Gate Array. In case of mission critical application area reliability of hardware is very much important hence concept of cryptography is widely used. The system should be designed in order to remove the faults which occurs in a system. SRAM-based FPGAs has made it possible to constitute fault tolerance into systems at lower cost. Since cryptographic devices are widely employed for applications which demands to keep personal information secure and safe and collection of sensitive information. These days, such as bank cards, universal-serial-bus (USB) keys, and e-passports, studying the effect of these faults for that RSA implementation safety- and mission-critical applications is of significant importance.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"26 1","pages":"176-179"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74314541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942612
R. Kaul, U. Khot
In this paper, Low profile microstrip antennas for glucometer application are proposed. As dielectric constant of the material as a superstrate placed above antenna changes, resonant characteristic of antenna varies and shift in the frequency is observed. The proposed microstrip antenna resonators are designed using Advanced Design System 2015.01 for an operating frequency as low as 1 GHz. The operating frequency of antenna should be low as the low frequency microwave signal penetrate deep into tissues and have potential for practical application because of low physical area, low cost and better frequency resolution. Further, a high frequency resolution i.e. for a small change in glucose concentration leads to considerable shift in operating frequency, is achieved. The proposed microstrip antennas are designed and tested with aqueous glucose superstrate. This is advancement towards developing microstrip sensor for non-invasive glucometer application.
本文提出了一种用于血糖仪的低轮廓微带天线。当放置在天线上的材料介电常数发生变化时，天线的谐振特性发生变化，频率发生偏移。采用Advanced Design System 2015.01设计微带天线谐振器，工作频率低至1ghz。由于低频微波信号能深入人体组织，因此天线的工作频率应较低，具有占地面积小、成本低、频率分辨率高等优点，具有实际应用的潜力。此外，实现了高频率分辨率，即葡萄糖浓度的微小变化导致工作频率的相当大的变化。采用葡萄糖水基质对微带天线进行了设计和测试。这是研制用于无创血糖仪的微带传感器的一个重要进展。
{"title":"Design of microstrip antennas for glucometer application","authors":"R. Kaul, U. Khot","doi":"10.1109/ICAECCT.2016.7942612","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942612","url":null,"abstract":"In this paper, Low profile microstrip antennas for glucometer application are proposed. As dielectric constant of the material as a superstrate placed above antenna changes, resonant characteristic of antenna varies and shift in the frequency is observed. The proposed microstrip antenna resonators are designed using Advanced Design System 2015.01 for an operating frequency as low as 1 GHz. The operating frequency of antenna should be low as the low frequency microwave signal penetrate deep into tissues and have potential for practical application because of low physical area, low cost and better frequency resolution. Further, a high frequency resolution i.e. for a small change in glucose concentration leads to considerable shift in operating frequency, is achieved. The proposed microstrip antennas are designed and tested with aqueous glucose superstrate. This is advancement towards developing microstrip sensor for non-invasive glucometer application.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"1 1","pages":"352-357"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87420613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942625
S. Gopikrishna, M. Jha, S. Sreekanth, G. Savithri
This paper presents an empirical approach to accelerate the verification of System On Chip using hardware acceleration and software emulation. This paper emphasizes the importance of simultaneous hardware (HW) and Firmware (FW) development to fix HW/SW interaction bugs early in the design to reduce the product development cycle. This paper discusses various solution methodologies for SoC verification methodology using HW emulation & Co-modeling testbench technologies. The test bench is put into the accelerator directly, resulting in a quick migration to accelerator. The functional verification of the SoC and Firmware development is based on Software Oriented Emulation in hardware acceleration mode of testbench technology. The SoC is synthesized on to the Mentor Graphics Veloce2 Quattro Emulation box and U-Boot Monitor Commands are developed with UART and Hyper terminal utility at baud rate of 9600. U-Boot debug monitor commands were customized to debug various verification scenarios and to enable early software development for the SoC. The verification of SoC using U-Boot commands developed and the emulator crystal utilization are presented. The results show that by adopting the accelerated verification on veloce2 emulator using U-Boot software, speedup of the order of 100× was achieved for functional verification of a Complex Multiprocessor SoC compared to standard HDL simulator.
{"title":"A multiprocessor System On Chip verification on hardware accelerator and Software Emulation","authors":"S. Gopikrishna, M. Jha, S. Sreekanth, G. Savithri","doi":"10.1109/ICAECCT.2016.7942625","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942625","url":null,"abstract":"This paper presents an empirical approach to accelerate the verification of System On Chip using hardware acceleration and software emulation. This paper emphasizes the importance of simultaneous hardware (HW) and Firmware (FW) development to fix HW/SW interaction bugs early in the design to reduce the product development cycle. This paper discusses various solution methodologies for SoC verification methodology using HW emulation & Co-modeling testbench technologies. The test bench is put into the accelerator directly, resulting in a quick migration to accelerator. The functional verification of the SoC and Firmware development is based on Software Oriented Emulation in hardware acceleration mode of testbench technology. The SoC is synthesized on to the Mentor Graphics Veloce2 Quattro Emulation box and U-Boot Monitor Commands are developed with UART and Hyper terminal utility at baud rate of 9600. U-Boot debug monitor commands were customized to debug various verification scenarios and to enable early software development for the SoC. The verification of SoC using U-Boot commands developed and the emulator crystal utilization are presented. The results show that by adopting the accelerated verification on veloce2 emulator using U-Boot software, speedup of the order of 100× was achieved for functional verification of a Complex Multiprocessor SoC compared to standard HDL simulator.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"36 11","pages":"423-428"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91500383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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