Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942634
N. Thune, S. Haridas
In this paper unique approach of new digital communication system, 4D 8 PSK TCM Encoder design and simulation is presented. TCM Encoder with 11/12 code rate and 2.75 spectral efficiency has been implemented, Modulator specifications are same as given in Consultative Committee for Space Data System (CCSDS) used for satellite application[2]. TCM is combination of Encoding and Modulation, which improve noise performance of digital communication by 3 dB without any data rate loss or expansion of bandwidth. As the complexity of system increases coding gain of 6 dB can be achieved. That's why TCM referred as a bandwidth efficient modulation preferred by CCSDC. Specialized software for communication system simulation MATLAB Simulink is used for simulation; preferably communication and signal processing tools boxes are used.
{"title":"4D-8PSK trellis coded modulation for high speed satellite communication","authors":"N. Thune, S. Haridas","doi":"10.1109/ICAECCT.2016.7942634","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942634","url":null,"abstract":"In this paper unique approach of new digital communication system, 4D 8 PSK TCM Encoder design and simulation is presented. TCM Encoder with 11/12 code rate and 2.75 spectral efficiency has been implemented, Modulator specifications are same as given in Consultative Committee for Space Data System (CCSDS) used for satellite application[2]. TCM is combination of Encoding and Modulation, which improve noise performance of digital communication by 3 dB without any data rate loss or expansion of bandwidth. As the complexity of system increases coding gain of 6 dB can be achieved. That's why TCM referred as a bandwidth efficient modulation preferred by CCSDC. Specialized software for communication system simulation MATLAB Simulink is used for simulation; preferably communication and signal processing tools boxes are used.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"290 1","pages":"469-473"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80560392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942632
Nidhi Jha, Chinmay Pisu, Sneha Sakhare, Pramod K. Jagtap, Varsha N. Degaonkar
In this paper, we are presenting a tri-band Planar Inverted F Antenna (PIFA) for mobile application. PIFA basically consist of ground plate, patch, feed and shortening pin connected to ground plate. Antenna is designed to tune at 916MHz, 1800MHz and 6.2GHz frequencies. Designed antenna has been simulated in CST 2012 software and various parameters of antenna are studied and presented. The designed antenna also has been fabricated manually and tested on vector network analyser (VNA) and has met the performance criteria for mobile application.
{"title":"Design of tri band Planar Inverted F Antenna","authors":"Nidhi Jha, Chinmay Pisu, Sneha Sakhare, Pramod K. Jagtap, Varsha N. Degaonkar","doi":"10.1109/ICAECCT.2016.7942632","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942632","url":null,"abstract":"In this paper, we are presenting a tri-band Planar Inverted F Antenna (PIFA) for mobile application. PIFA basically consist of ground plate, patch, feed and shortening pin connected to ground plate. Antenna is designed to tune at 916MHz, 1800MHz and 6.2GHz frequencies. Designed antenna has been simulated in CST 2012 software and various parameters of antenna are studied and presented. The designed antenna also has been fabricated manually and tested on vector network analyser (VNA) and has met the performance criteria for mobile application.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"18 1","pages":"461-463"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75211839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942586
A. Deshmukh, Mohil Gala, S. Agrawal
By cutting U-slot, bandwidth of shorted square microstrip antenna has been increased. Here, detailed analysis which explain the effects of U-slot to achieve wide band response in shorted square patch is presented. U-slot yields tuning of TM3/4,0 mode frequency with respect to shorted patch TM1/4,0 mode, thereby it gives 27% of bandwidth in 2.4 GHz range. Slot also modifies current distribution at second order mode to give broadside radiation pattern over the bandwidth. An insight into the functioning of widely reported U-slot cut shorted square patch antennas in terms of patch resonant modes is provided here. This study will serve as a tutorial to re-design similar antennas at any given frequency.
{"title":"U-slot cut shorted square microstrip antenna","authors":"A. Deshmukh, Mohil Gala, S. Agrawal","doi":"10.1109/ICAECCT.2016.7942586","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942586","url":null,"abstract":"By cutting U-slot, bandwidth of shorted square microstrip antenna has been increased. Here, detailed analysis which explain the effects of U-slot to achieve wide band response in shorted square patch is presented. U-slot yields tuning of TM3/4,0 mode frequency with respect to shorted patch TM1/4,0 mode, thereby it gives 27% of bandwidth in 2.4 GHz range. Slot also modifies current distribution at second order mode to give broadside radiation pattern over the bandwidth. An insight into the functioning of widely reported U-slot cut shorted square patch antennas in terms of patch resonant modes is provided here. This study will serve as a tutorial to re-design similar antennas at any given frequency.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"99 1","pages":"221-225"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74176465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942574
C. Choubey, Gaurav Tiwari, S. K. Paul
In this paper, we proposed a number of new inverse highpass (IHP), inverse bandpass (IBP), and inverse lowpass (ILP) filters using second generation current conveyor (CCII) as building blocks. The proposed two topologies can be configured as one of the above mentioned inversed filter by the selection of appropriate admittance. To test the functionality of the proposed multifunction inverse filter, the circuit was simulated using PSPICE simulator software. In simulation of the circuits, the CCII circuit was designed using macro model of AD844 IC. The simulated results are well agreed with the theoretical results.
{"title":"CCII based multifunction inverse filter","authors":"C. Choubey, Gaurav Tiwari, S. K. Paul","doi":"10.1109/ICAECCT.2016.7942574","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942574","url":null,"abstract":"In this paper, we proposed a number of new inverse highpass (IHP), inverse bandpass (IBP), and inverse lowpass (ILP) filters using second generation current conveyor (CCII) as building blocks. The proposed two topologies can be configured as one of the above mentioned inversed filter by the selection of appropriate admittance. To test the functionality of the proposed multifunction inverse filter, the circuit was simulated using PSPICE simulator software. In simulation of the circuits, the CCII circuit was designed using macro model of AD844 IC. The simulated results are well agreed with the theoretical results.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"3 1","pages":"160-163"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82173521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942562
Ganesh V. Patil, Santosh L. Deshpande
Photo realistic effects in a complex animation scene can be achieved using the process of rendering. Rendering is more time and cost consuming process as it involves pixel based light and camera effects that will be converted into actual photo realistic scenes. To upgrade quality of animated scenes up to the mark, rendering requires high end computational set up. Processing cost of rendering goes on increasing as the quality and efficiency required increases. Required computational set up includes high end computational resources which are not affordable to a small scale animator. So with the present work we here are going to provide a solution to this problem so that small scale animator also can have effective rendering at a low cost and better efficiency. We are going to provide a Blender based low cost distributed, efficient rendering set up.
{"title":"Distributed rendering system for 3D animations with Blender","authors":"Ganesh V. Patil, Santosh L. Deshpande","doi":"10.1109/ICAECCT.2016.7942562","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942562","url":null,"abstract":"Photo realistic effects in a complex animation scene can be achieved using the process of rendering. Rendering is more time and cost consuming process as it involves pixel based light and camera effects that will be converted into actual photo realistic scenes. To upgrade quality of animated scenes up to the mark, rendering requires high end computational set up. Processing cost of rendering goes on increasing as the quality and efficiency required increases. Required computational set up includes high end computational resources which are not affordable to a small scale animator. So with the present work we here are going to provide a solution to this problem so that small scale animator also can have effective rendering at a low cost and better efficiency. We are going to provide a Blender based low cost distributed, efficient rendering set up.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"22 1","pages":"91-98"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84491987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942545
S. Shinde, H. Muthurajan
PCB (Printed Circuit Board) is the backbone of electronics fabrication industry. Tremendous research in PCB fabrication technique has contributed in the reliable and accurate PCB fabrication. There are numerous PCB fabrication techniques available for PCB prototyping. The technique used here to fabricate PCB is UV lithography; the lithography is worldwide accepted technique by semiconductor industry for IC (Integrated Chip) fabrication. Lithography technique uses photosensitive material (Photoresist) coated subject to transfer the required pattern. It is kind of pattern transfer technique with the help of radiation source having wavelength in the range of UV spectrum. The aim of this work is to fabricate low cost PCB fabricating unit for research and educational use. The low cost PCB prototyping equipment is fabricated and tested for its performance. The unit is evaluated, calibrated and automated for its optimum performance to make precise PCBs with better resolution and accuracy. Overviews of Different PCB fabrication techniques for electronics product prototyping are also highlighted.
{"title":"PCB fabrication unit for electronics circuit prototyping","authors":"S. Shinde, H. Muthurajan","doi":"10.1109/ICAECCT.2016.7942545","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942545","url":null,"abstract":"PCB (Printed Circuit Board) is the backbone of electronics fabrication industry. Tremendous research in PCB fabrication technique has contributed in the reliable and accurate PCB fabrication. There are numerous PCB fabrication techniques available for PCB prototyping. The technique used here to fabricate PCB is UV lithography; the lithography is worldwide accepted technique by semiconductor industry for IC (Integrated Chip) fabrication. Lithography technique uses photosensitive material (Photoresist) coated subject to transfer the required pattern. It is kind of pattern transfer technique with the help of radiation source having wavelength in the range of UV spectrum. The aim of this work is to fabricate low cost PCB fabricating unit for research and educational use. The low cost PCB prototyping equipment is fabricated and tested for its performance. The unit is evaluated, calibrated and automated for its optimum performance to make precise PCBs with better resolution and accuracy. Overviews of Different PCB fabrication techniques for electronics product prototyping are also highlighted.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"52 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85128812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942631
Suyash Toro, Sushma Wadar, Y. Chavan, S. Patil, D. Bormane, A. Patil
Development in VLSI technology and its implementation leading to optimization of various systems related with prime parameters such as power, speed and area has been achieved. As the consumer electronics market is growing very rapidly, RISC processors with additional features required to be implemented are also demanding. The RISC processor supports many applications with its features, but the feature like external memory interface which is the requirement for some of the applications is limiting factor and has been given due weightage in this paper. This interface of external memory with the RISC processor is targeted to be performed in stipulated time span with the required control signals. The additional hardware required for interfacing the external memory does not affect the timing required for accessing the data from it. The timing analysis with the hardware targeted technology has been done and discussed. This paper presents the simulation of external memory interfacing of 8-bit PIC microcontroller using Xilinx 10.1.
{"title":"External memory interface for RISC controller on reconfigurable hardware logic","authors":"Suyash Toro, Sushma Wadar, Y. Chavan, S. Patil, D. Bormane, A. Patil","doi":"10.1109/ICAECCT.2016.7942631","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942631","url":null,"abstract":"Development in VLSI technology and its implementation leading to optimization of various systems related with prime parameters such as power, speed and area has been achieved. As the consumer electronics market is growing very rapidly, RISC processors with additional features required to be implemented are also demanding. The RISC processor supports many applications with its features, but the feature like external memory interface which is the requirement for some of the applications is limiting factor and has been given due weightage in this paper. This interface of external memory with the RISC processor is targeted to be performed in stipulated time span with the required control signals. The additional hardware required for interfacing the external memory does not affect the timing required for accessing the data from it. The timing analysis with the hardware targeted technology has been done and discussed. This paper presents the simulation of external memory interfacing of 8-bit PIC microcontroller using Xilinx 10.1.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"446 1","pages":"455-460"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76484750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942624
Naktode Dipali Ravi, D. Bhalke
In this paper musical instrument recognition and retrieval for fifteen musical instruments from different instrument families are discussed. The system is implementing in three stages; first stage is pre-processing, second is feature extraction and third is recognition and retrieval. Musical instruments are retrieved using most important and distinguishable features like temporal and cepstral features. Kohenon self organizing map has been used as classifiers. The average accuracy is achieved for fifteen instruments are recorded 92.98%. The experimental results also show that the better recognition rate is obtained for LPCC as compared to MFCC and temporal for all the musical instruments.
{"title":"Musical Instrument Information retrieval using Neural Network","authors":"Naktode Dipali Ravi, D. Bhalke","doi":"10.1109/ICAECCT.2016.7942624","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942624","url":null,"abstract":"In this paper musical instrument recognition and retrieval for fifteen musical instruments from different instrument families are discussed. The system is implementing in three stages; first stage is pre-processing, second is feature extraction and third is recognition and retrieval. Musical instruments are retrieved using most important and distinguishable features like temporal and cepstral features. Kohenon self organizing map has been used as classifiers. The average accuracy is achieved for fifteen instruments are recorded 92.98%. The experimental results also show that the better recognition rate is obtained for LPCC as compared to MFCC and temporal for all the musical instruments.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"243 1","pages":"418-422"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77139861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942630
Suyash Toro, A. Patil, Y. Chavan, S. Patil, D. Bormane, Sushma Wadar
The work presented in this paper targets on the Division operation i.e. division. Basic operations like addition, subtraction and multiplication are implemented using Vedic mathematics for various dedicated applications such as RSA encryption and decryption algorithm. The proposed work focuses on division operation which is an important operation in areas such as image processing, networking, signal processing, computer graphics, numerical application, scientific applications and in processor implementation. From the architectural point of view, hardware required by division circuits are usually much larger than the multiplier circuits for same data word length and division operation is generally categories as slow division and fast division. Where slow division is restoring and non-restoring methods and fast division is Newton Raphson and Goldschmidt methods. The Vedic division method is mathematically modeled and tested for feasibility and is compared with earlier implementation like restoring and non-restoring methods. The work carried out on division operation based on Vedic mathematics is limited to one of the Vedic sutra. In this paper the four Sutras are considered for implementation.
{"title":"Division operation based on Vedic mathematics","authors":"Suyash Toro, A. Patil, Y. Chavan, S. Patil, D. Bormane, Sushma Wadar","doi":"10.1109/ICAECCT.2016.7942630","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942630","url":null,"abstract":"The work presented in this paper targets on the Division operation i.e. division. Basic operations like addition, subtraction and multiplication are implemented using Vedic mathematics for various dedicated applications such as RSA encryption and decryption algorithm. The proposed work focuses on division operation which is an important operation in areas such as image processing, networking, signal processing, computer graphics, numerical application, scientific applications and in processor implementation. From the architectural point of view, hardware required by division circuits are usually much larger than the multiplier circuits for same data word length and division operation is generally categories as slow division and fast division. Where slow division is restoring and non-restoring methods and fast division is Newton Raphson and Goldschmidt methods. The Vedic division method is mathematically modeled and tested for feasibility and is compared with earlier implementation like restoring and non-restoring methods. The work carried out on division operation based on Vedic mathematics is limited to one of the Vedic sutra. In this paper the four Sutras are considered for implementation.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"1 1","pages":"450-454"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91197020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICAECCT.2016.7942608
Mukta Y. Raut, M. Kulkarni
In recent times, the availability of online reviews is ever increasing. This results in opinion mining being one of the core areas of affective computing. Classification of opinions or sentiments is the core task in opinion mining. To accomplish this task, often Bag-Of-Words(BOW) is used as a feature for training a classifier in statistical machine learning. However, the fundamental limitations in handling the polarity shift problem in turn limits the performance of BOW in some cases. Also the external dictionaries used for generating training sets for opinion classification are not domain specific. This further limits the task of deriving the accurate sentiment or consumer opinion in certain cases. We address these two problems in opinion classification. To handle the problem of polarity shift, we propose a Dual Opinion mining Model. The data expansion technique used in this model creates a review which has opposite opinion as that of the original test review for each training and test review. Based on this we propose a dual training algorithm which uses the pairs of the original and the reversed review to learn an opinion classifier. A dual prediction algorithm is used for classification of test reviews by considering both positive and negative sides of each review. At the end we build a pseudo-opposites dictionary using a corpus based method. By this we tackle the problem of having to depend upon an external opposites dictionary for opposites of reviews. By doing this we also get a domain adaptive dictionary for training a classifier which increases the accuracy of the dual opinion mining model.
{"title":"Polarity shift in opinion mining","authors":"Mukta Y. Raut, M. Kulkarni","doi":"10.1109/ICAECCT.2016.7942608","DOIUrl":"https://doi.org/10.1109/ICAECCT.2016.7942608","url":null,"abstract":"In recent times, the availability of online reviews is ever increasing. This results in opinion mining being one of the core areas of affective computing. Classification of opinions or sentiments is the core task in opinion mining. To accomplish this task, often Bag-Of-Words(BOW) is used as a feature for training a classifier in statistical machine learning. However, the fundamental limitations in handling the polarity shift problem in turn limits the performance of BOW in some cases. Also the external dictionaries used for generating training sets for opinion classification are not domain specific. This further limits the task of deriving the accurate sentiment or consumer opinion in certain cases. We address these two problems in opinion classification. To handle the problem of polarity shift, we propose a Dual Opinion mining Model. The data expansion technique used in this model creates a review which has opposite opinion as that of the original test review for each training and test review. Based on this we propose a dual training algorithm which uses the pairs of the original and the reversed review to learn an opinion classifier. A dual prediction algorithm is used for classification of test reviews by considering both positive and negative sides of each review. At the end we build a pseudo-opposites dictionary using a corpus based method. By this we tackle the problem of having to depend upon an external opposites dictionary for opposites of reviews. By doing this we also get a domain adaptive dictionary for training a classifier which increases the accuracy of the dual opinion mining model.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"5 1","pages":"333-337"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88827450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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