Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00064
S. Dhanuskodi, Daniel E. Holcomb
Highly serialized implementations of the AES block cipher are used in lightweight applications where low area and low power are the primary concerns. Security of these lightweight designs becomes increasingly critical on resource-constrained devices in the Internet of Things era. The AES algorithm does not have any significant known cryptanalytic weaknesses, but keys can often be extracted by attacking implementation weaknesses using side channel information leakage or fault injection. Highly serialized AES implementations compute on individual bytes/words of data in each cycle which leaves them especially sensitive to side channel key extraction because there is less overall power consumption to obscure side channel leakages. In this work, we present an efficient AES microarchitecture that randomizes sub-round operations and reduces susceptibility to power side channel attacks. The architecture we propose is compatible with, and complementary to, all existing circuit-level side channel countermeasures. We design an 8-bit AES architecture in a commercial 16nm FinFET technology and observe an order of magnitude improvement in side channel protection at a cost of 36% more area and 25% more energy per encryption. Testchip measurement shows 0.93pJ/bit energy consumption at 10MHz.
{"title":"Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility","authors":"S. Dhanuskodi, Daniel E. Holcomb","doi":"10.1109/ISVLSI.2019.00064","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00064","url":null,"abstract":"Highly serialized implementations of the AES block cipher are used in lightweight applications where low area and low power are the primary concerns. Security of these lightweight designs becomes increasingly critical on resource-constrained devices in the Internet of Things era. The AES algorithm does not have any significant known cryptanalytic weaknesses, but keys can often be extracted by attacking implementation weaknesses using side channel information leakage or fault injection. Highly serialized AES implementations compute on individual bytes/words of data in each cycle which leaves them especially sensitive to side channel key extraction because there is less overall power consumption to obscure side channel leakages. In this work, we present an efficient AES microarchitecture that randomizes sub-round operations and reduces susceptibility to power side channel attacks. The architecture we propose is compatible with, and complementary to, all existing circuit-level side channel countermeasures. We design an 8-bit AES architecture in a commercial 16nm FinFET technology and observe an order of magnitude improvement in side channel protection at a cost of 36% more area and 25% more energy per encryption. Testchip measurement shows 0.93pJ/bit energy consumption at 10MHz.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"20 1","pages":"314-319"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85935098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00109
Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang
Polar code has gained worldwide recognition due to its capacity-achieving property. The fast simplified successive cancellation flip (Fast-SSC-Flip) algorithm improves the frame error rate (FER) performance of successive cancellation (SC) decoders with extra metric computations. However, the metric includes exponential operations, which is inefficient to implement. In this work, one shift operation and one addition are employed to approximate the exponential operations with negligible performance loss. Besides, the metric computations of more constituent codes (Type-I to Type-V) are derived that the complexity of Fast-SSC-Flip is further reduced. Simulation results show that the FER performance of the improved Fast-SSC-Flip algorithm with list size λ = 8 outperforms that of the Fast-SSC algorithm by 0.7dB. Moreover, based on the proposed algorithm, an efficient hardware architecture is first developed. It uses less look up tables and achieves a maximum throughput of 140.6 Mbps at high SNR on the Altera Stratix IV EP4SGX530KH40C2 FPGA. Compared with the state of art Fast-SSC implementation, the proposed architecture has a higher resource utilization efficiency (throughput per look-up tables). Under the 28 nm CMOS technology, the throughput can reach up to 483.8 Mbps at a clock frequency of 704 MHz.
{"title":"Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes","authors":"Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang","doi":"10.1109/ISVLSI.2019.00109","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00109","url":null,"abstract":"Polar code has gained worldwide recognition due to its capacity-achieving property. The fast simplified successive cancellation flip (Fast-SSC-Flip) algorithm improves the frame error rate (FER) performance of successive cancellation (SC) decoders with extra metric computations. However, the metric includes exponential operations, which is inefficient to implement. In this work, one shift operation and one addition are employed to approximate the exponential operations with negligible performance loss. Besides, the metric computations of more constituent codes (Type-I to Type-V) are derived that the complexity of Fast-SSC-Flip is further reduced. Simulation results show that the FER performance of the improved Fast-SSC-Flip algorithm with list size λ = 8 outperforms that of the Fast-SSC algorithm by 0.7dB. Moreover, based on the proposed algorithm, an efficient hardware architecture is first developed. It uses less look up tables and achieves a maximum throughput of 140.6 Mbps at high SNR on the Altera Stratix IV EP4SGX530KH40C2 FPGA. Compared with the state of art Fast-SSC implementation, the proposed architecture has a higher resource utilization efficiency (throughput per look-up tables). Under the 28 nm CMOS technology, the throughput can reach up to 483.8 Mbps at a clock frequency of 704 MHz.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"88 1","pages":"580-585"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85633660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00037
A. L. Sartor, P. H. E. Becker, Stephan Wong, R. Marculescu, A. C. S. Beck
Adaptive processors can dynamically change their hardware configuration by tuning several knobs that optimize a given metric, according to the current application. However, the complexity of choosing the best setup at runtime increases exponentially as more adaptive resources become available. Therefore, we propose a polymorphic VLIW processor coupled to a machine learning-based decision mechanism that quickly and accurately delivers the best trade-off in terms of energy, performance, and reliability. The proposed system predicts the best processor configuration in 97.37% of the test cases and achieves an efficiency that is close to an oracle (more than 93.30% on all benchmarks).
{"title":"Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability","authors":"A. L. Sartor, P. H. E. Becker, Stephan Wong, R. Marculescu, A. C. S. Beck","doi":"10.1109/ISVLSI.2019.00037","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00037","url":null,"abstract":"Adaptive processors can dynamically change their hardware configuration by tuning several knobs that optimize a given metric, according to the current application. However, the complexity of choosing the best setup at runtime increases exponentially as more adaptive resources become available. Therefore, we propose a polymorphic VLIW processor coupled to a machine learning-based decision mechanism that quickly and accurately delivers the best trade-off in terms of energy, performance, and reliability. The proposed system predicts the best processor configuration in 97.37% of the test cases and achieves an efficiency that is close to an oracle (more than 93.30% on all benchmarks).","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"12 1","pages":"158-163"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83889576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00070
S. Swami, K. Mohanram
Computing systems that integrate advanced non-volatile memories (NVMs) are vulnerable to several security attacks that threaten (i) data confidentiality, (ii) data availability, and (iii) data integrity. This paper proposes Architectures for Smart Security of NVMs (AS-SET), which integrates five low overhead, high performance security solutions—SECRET [1], COVERT [2], ACME [3], ARSE-NAL [4], and STASH [5]—to thwart these attacks on NVM systems. SECRET is a low cost security solution that employs counter mode encryption (CME) for data confidentiality in multi-/triple-level cell (i.e., MLC/TLC) NVMs. COVERT and ACME complement SECRET to improve system availability of CME. ARSENAL integrates CME and Bonsai Merkle Tree (BMT) authentication to thwart data confidentiality and integrity attacks, respectively, in NVMs and simultaneously enables instant data recovery (IDR) on power/system failures. Finally, STASH is the first comprehensive end-to-end security architecture for state-of-the-art smart hybrid memories (SHMs). STASH integrates (i) CME for data confidentiality, (ii) page-level MT authentication for data integrity, (iii) recovery-compatible MT updates to withstand power or system failures, and (iv) page-migration friendly security meta-data management. This paper thus addresses the core security challenges of next-generation NVM systems.
{"title":"ASSET: Architectures for Smart Security of Non-Volatile Memories","authors":"S. Swami, K. Mohanram","doi":"10.1109/ISVLSI.2019.00070","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00070","url":null,"abstract":"Computing systems that integrate advanced non-volatile memories (NVMs) are vulnerable to several security attacks that threaten (i) data confidentiality, (ii) data availability, and (iii) data integrity. This paper proposes Architectures for Smart Security of NVMs (AS-SET), which integrates five low overhead, high performance security solutions—SECRET [1], COVERT [2], ACME [3], ARSE-NAL [4], and STASH [5]—to thwart these attacks on NVM systems. SECRET is a low cost security solution that employs counter mode encryption (CME) for data confidentiality in multi-/triple-level cell (i.e., MLC/TLC) NVMs. COVERT and ACME complement SECRET to improve system availability of CME. ARSENAL integrates CME and Bonsai Merkle Tree (BMT) authentication to thwart data confidentiality and integrity attacks, respectively, in NVMs and simultaneously enables instant data recovery (IDR) on power/system failures. Finally, STASH is the first comprehensive end-to-end security architecture for state-of-the-art smart hybrid memories (SHMs). STASH integrates (i) CME for data confidentiality, (ii) page-level MT authentication for data integrity, (iii) recovery-compatible MT updates to withstand power or system failures, and (iv) page-migration friendly security meta-data management. This paper thus addresses the core security challenges of next-generation NVM systems.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"182 1","pages":"348-353"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77589898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00117
Prasad Vernekar, Nithin Kumar Yernad Balachandra, V. M. Harishchandra
The scaling of technology resulted in shrinking of device sizes, however suffers from threshold variation. These variations impact the performance and stability of static random access memory (SRAM). The proposed work takes the advantage of the conventional Replica-Bit-Line (RBL) technique to design a self-timed SRAM control circuit which keeps track of timing variations and generated control signals. A variable wordline scheme is proposed to ensure successful read and write operation of SRAM at low voltages. The 2 Kb (2048 bits) SRAM designed in 65 nm UMC technology, operates with clock frequency reaching upto 1 GHz at the nominal supply voltage of 1.2 V and at 50 MHz with the supply voltage of 0.58 V. The variations in the Sense Amplifier Enable (SAE) generation are reduced upto 92% compared to the conventional RBL technique.
{"title":"Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability","authors":"Prasad Vernekar, Nithin Kumar Yernad Balachandra, V. M. Harishchandra","doi":"10.1109/ISVLSI.2019.00117","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00117","url":null,"abstract":"The scaling of technology resulted in shrinking of device sizes, however suffers from threshold variation. These variations impact the performance and stability of static random access memory (SRAM). The proposed work takes the advantage of the conventional Replica-Bit-Line (RBL) technique to design a self-timed SRAM control circuit which keeps track of timing variations and generated control signals. A variable wordline scheme is proposed to ensure successful read and write operation of SRAM at low voltages. The 2 Kb (2048 bits) SRAM designed in 65 nm UMC technology, operates with clock frequency reaching upto 1 GHz at the nominal supply voltage of 1.2 V and at 50 MHz with the supply voltage of 0.58 V. The variations in the Sense Amplifier Enable (SAE) generation are reduced upto 92% compared to the conventional RBL technique.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"46 1","pages":"627-631"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78169814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00047
S. Paul, Pritha Banerjee, S. Sur-Kolay
Extreme Ultraviolet Lithography (EUVL) suffers from pattern distortion defects caused by flare, which is irregular reflection from the surface of the mask used. While techniques based on (a) dummification and (b) perturbation of wire segments have reduced flare notably, each has its own merits and demerits. Unlike earlier works where each method for flare reduction is applied independently, in this paper we extensively study the effects on flare and the amount of dummy fills required by simultaneous dummification and wire segment perturbation using an Integer Linear Programming (ILP) based formulation in a multilevel framework at the post-routing stage. Experimental results show an average reduction of maximum flare level by 29% compared to that in the initial routed layout. In addition to that, an average reduction of maximum flare by 19% is observed compared to the method of wire perturbation alone. Moreover, in our method 35% reduction in dummy requirement on average is achieved compared to the application of dummification technique alone for the reduction of flare.
{"title":"Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification","authors":"S. Paul, Pritha Banerjee, S. Sur-Kolay","doi":"10.1109/ISVLSI.2019.00047","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00047","url":null,"abstract":"Extreme Ultraviolet Lithography (EUVL) suffers from pattern distortion defects caused by flare, which is irregular reflection from the surface of the mask used. While techniques based on (a) dummification and (b) perturbation of wire segments have reduced flare notably, each has its own merits and demerits. Unlike earlier works where each method for flare reduction is applied independently, in this paper we extensively study the effects on flare and the amount of dummy fills required by simultaneous dummification and wire segment perturbation using an Integer Linear Programming (ILP) based formulation in a multilevel framework at the post-routing stage. Experimental results show an average reduction of maximum flare level by 29% compared to that in the initial routed layout. In addition to that, an average reduction of maximum flare by 19% is observed compared to the method of wire perturbation alone. Moreover, in our method 35% reduction in dummy requirement on average is achieved compared to the application of dummification technique alone for the reduction of flare.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"8 1","pages":"212-217"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73575290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00069
A. Annagrebah, E. Bechetoille, I. Laktineh, H. Chanal, P. Russo, H. Mathez
is paper reports the development of an adjustable, Time-to-Digital Converter (TDC) based on two vernier Ring Oscillators (RO). The TDC aims to measure timing in Resistive Plate Chamber (RPC) detector for CMS experiment. Considering previous designs, the contribution from power supply noise and intrinsic transistor noise had been minimizing with differential stages and proper transistor sizing. In order to reduce the dead time inherent to Vernier TDC architecture, as many Phase Detector (PD) as possible had been implemented. Such functionality permits to choose whether reducing the dead time or measuring redundantly the start-stop time difference for an improved resolution. The 81-PD Matrix is the originality of the design. Indeed, the information of the start-stop time is present at each inverter output with a predictable offset in term of time. The inverter architecture introduces a constant delay at each stage of the chain with phase inversion. By recording the counter when a phase detection occurs at each inverter output permitted to revert back to the start-stop time. The prototype TDC fabricated in a 130-nm technology consumes 8.5 mW power under 1.2-V supply. The measurement of this chip shown a timing accuracy of 5.48 ps at a timing resolution of 8 ps for the first data allowed by the first phase detection
{"title":"A Multi-phase Time-to-Digital Converter Differential Vernier Ring Oscillato","authors":"A. Annagrebah, E. Bechetoille, I. Laktineh, H. Chanal, P. Russo, H. Mathez","doi":"10.1109/ISVLSI.2019.00069","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00069","url":null,"abstract":"is paper reports the development of an adjustable, Time-to-Digital Converter (TDC) based on two vernier Ring Oscillators (RO). The TDC aims to measure timing in Resistive Plate Chamber (RPC) detector for CMS experiment. Considering previous designs, the contribution from power supply noise and intrinsic transistor noise had been minimizing with differential stages and proper transistor sizing. In order to reduce the dead time inherent to Vernier TDC architecture, as many Phase Detector (PD) as possible had been implemented. Such functionality permits to choose whether reducing the dead time or measuring redundantly the start-stop time difference for an improved resolution. The 81-PD Matrix is the originality of the design. Indeed, the information of the start-stop time is present at each inverter output with a predictable offset in term of time. The inverter architecture introduces a constant delay at each stage of the chain with phase inversion. By recording the counter when a phase detection occurs at each inverter output permitted to revert back to the start-stop time. The prototype TDC fabricated in a 130-nm technology consumes 8.5 mW power under 1.2-V supply. The measurement of this chip shown a timing accuracy of 5.48 ps at a timing resolution of 8 ps for the first data allowed by the first phase detection","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"22 1","pages":"344-347"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85404019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00079
Soheil Salehi, Alireza Zaeemzadeh, Adrian Tatulian, N. Rahnavard, R. Demara
Recent advances to hardware integration and realization of highly-efficient Compressive Sensing (CS) approaches have inspired novel circuit and architectural-level approaches. These embrace the challenge to design more optimal nonuniform CS solutions that consider device-level constraints for IoT applications wherein lifetime energy, device area, and manufacturing costs are highly-constrained, but meanwhile, the sensing environment is rapidly changing. In this manuscript, we develop a novel adaptive hardware-based approach for non-uniform compressive sampling of sparse and time-varying signals. The proposed Adaptive Sampling of Sparse IoT signals via STochastic-oscillators (ASSIST) approach intelligently generates the CS measurement matrix by distributing the sensing energy among coefficients by considering the signal characteristics such as sparsity rate and noise level obtained in the previous time step. In our proposed approach, Magnetic Random Access Memory (MRAM)-based stochastic oscillators are utilized to generate the random bitstreams used in the CS measurement matrix. SPICE and MATLAB circuit-algorithm simulation results indicate that ASSIST efficiently achieves the desired non-uniform recovery of the original signals with varying sparsity rates and noise levels.
{"title":"MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications","authors":"Soheil Salehi, Alireza Zaeemzadeh, Adrian Tatulian, N. Rahnavard, R. Demara","doi":"10.1109/ISVLSI.2019.00079","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00079","url":null,"abstract":"Recent advances to hardware integration and realization of highly-efficient Compressive Sensing (CS) approaches have inspired novel circuit and architectural-level approaches. These embrace the challenge to design more optimal nonuniform CS solutions that consider device-level constraints for IoT applications wherein lifetime energy, device area, and manufacturing costs are highly-constrained, but meanwhile, the sensing environment is rapidly changing. In this manuscript, we develop a novel adaptive hardware-based approach for non-uniform compressive sampling of sparse and time-varying signals. The proposed Adaptive Sampling of Sparse IoT signals via STochastic-oscillators (ASSIST) approach intelligently generates the CS measurement matrix by distributing the sensing energy among coefficients by considering the signal characteristics such as sparsity rate and noise level obtained in the previous time step. In our proposed approach, Magnetic Random Access Memory (MRAM)-based stochastic oscillators are utilized to generate the random bitstreams used in the CS measurement matrix. SPICE and MATLAB circuit-algorithm simulation results indicate that ASSIST efficiently achieves the desired non-uniform recovery of the original signals with varying sparsity rates and noise levels.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"28 1","pages":"403-408"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89941504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00051
Prashansa Mukim, Aditya Dalakoti, D. McCarthy, Brandon Pon, Carrie Segal, Merritt Miller, J. Buckwalter, F. Brewer
This paper describes the architecture and design of pulse rotary traveling wave voltage controlled oscillators that preserve wave shape, and thus wave harmonics using non-linear amplification. These oscillators can provide multiple low dutycycle clock phases and architectural modifications can allow for the same clock phase to be present at multiple physical locations. A design fabricated in GFUS 130nm (8RF) technology operates at 5.32 GHz with a 10 MHz offset phase noise of -128.15 dBc/Hz at 45.4 mW while generating 12 driven phase outputs with 15.66 ps phase resolution and less than 500 fs cycle-to-cycle jitter. It can be coarse or fine tuned within a frequency range of 4.35 GHz to 5.4 GHz with KV CO of 1.7 GHz/V and 470 MHz/V respectively. The start-up mechanism of the oscillator minimizes transmission line reflections and allows maintenance of the traveling wave shape, yielding an average 3 dB figure of merit improvement over existing designs.
{"title":"Distributed Pulse Rotary Traveling Wave VCO: Architecture and Design","authors":"Prashansa Mukim, Aditya Dalakoti, D. McCarthy, Brandon Pon, Carrie Segal, Merritt Miller, J. Buckwalter, F. Brewer","doi":"10.1109/ISVLSI.2019.00051","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00051","url":null,"abstract":"This paper describes the architecture and design of pulse rotary traveling wave voltage controlled oscillators that preserve wave shape, and thus wave harmonics using non-linear amplification. These oscillators can provide multiple low dutycycle clock phases and architectural modifications can allow for the same clock phase to be present at multiple physical locations. A design fabricated in GFUS 130nm (8RF) technology operates at 5.32 GHz with a 10 MHz offset phase noise of -128.15 dBc/Hz at 45.4 mW while generating 12 driven phase outputs with 15.66 ps phase resolution and less than 500 fs cycle-to-cycle jitter. It can be coarse or fine tuned within a frequency range of 4.35 GHz to 5.4 GHz with KV CO of 1.7 GHz/V and 470 MHz/V respectively. The start-up mechanism of the oscillator minimizes transmission line reflections and allows maintenance of the traveling wave shape, yielding an average 3 dB figure of merit improvement over existing designs.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"18 1","pages":"235-240"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89546675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00043
Adarsha Balaji, Anup Das
Spiking neural networks (SNN) are efficient computation models to infer spacio-temporal pattern recognition applications on neuromorphic hardware. Neuromorphic hardware are typically designed using interconnected crossbars, with each crossbar containing a structure of fully connected neurons. In order to ensure application performance such as accuracy and system performance such as throughput and resource utilization, SNNs need to be efficiently mapped on neuromorphic hardware. To address this, we propose a design flow to partition and map SNN-based applications on neuromorphic hardware, with an aim to enhance application and system performance. The design flow operates in two steps : (1) a two-step clustering technique to partition trained SNNs into clusters of neurons and synapses, with an aim to minimize inter-cluster spike communication, (2) mapping and scheduling the clusters on to crossbars-based architectures, modeled using Synchronous Data-flow Graphs (SDFGs). The SDFG model incorporates hardware constraints such as I/O bandwidth of crossbars and synaptic memory while analyzing the throughput of the modeled system. Our design-flow integrates CARLsim, a GPU-accelerated application-level SNN simulator with SDF3, a tool to map SDFG on hardware. We evaluate the design-flow using synthetic and realistic SNN-based applications. We show that, for throughput constrained applications, we achieve a 21.74% and 15.03% reduction in memory usage and utilization of the time-multiplexed interconnect, compared to a state of the art approach.
{"title":"A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic Hardware","authors":"Adarsha Balaji, Anup Das","doi":"10.1109/ISVLSI.2019.00043","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00043","url":null,"abstract":"Spiking neural networks (SNN) are efficient computation models to infer spacio-temporal pattern recognition applications on neuromorphic hardware. Neuromorphic hardware are typically designed using interconnected crossbars, with each crossbar containing a structure of fully connected neurons. In order to ensure application performance such as accuracy and system performance such as throughput and resource utilization, SNNs need to be efficiently mapped on neuromorphic hardware. To address this, we propose a design flow to partition and map SNN-based applications on neuromorphic hardware, with an aim to enhance application and system performance. The design flow operates in two steps : (1) a two-step clustering technique to partition trained SNNs into clusters of neurons and synapses, with an aim to minimize inter-cluster spike communication, (2) mapping and scheduling the clusters on to crossbars-based architectures, modeled using Synchronous Data-flow Graphs (SDFGs). The SDFG model incorporates hardware constraints such as I/O bandwidth of crossbars and synaptic memory while analyzing the throughput of the modeled system. Our design-flow integrates CARLsim, a GPU-accelerated application-level SNN simulator with SDF3, a tool to map SDFG on hardware. We evaluate the design-flow using synthetic and realistic SNN-based applications. We show that, for throughput constrained applications, we achieve a 21.74% and 15.03% reduction in memory usage and utilization of the time-multiplexed interconnect, compared to a state of the art approach.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"193-196"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75049569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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