Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00015
Chi Fung Brian Fong, Jiandong Mu, Wei Zhang
Convolutional neural networks (CNNs) are rapidly expanding and being applied to a vast range of applications. Despite its popularity, deploying CNNs on a portable system is challenging due to enormous data volume, intensive computation, and frequent memory access. Hence, many approaches have been proposed to reduce the CNN model complexity, such as model pruning and quantization. However, it also brings new challenges. For example, existing designs usually adopted channel dimension tiling which requires regular channel number. After pruning, the channel number may become highly irregular which will incur heavy zero padding and large resource waste. As for quantization, simple aggressive bit reduction usually results in large accuracy drop. In order to address these challenges, in this work, firstly we propose to use row-based tiling in the kernel dimension to adapt to different kernel sizes and channel numbers and significantly reduce the zero padding. Moreover, we developed the configurable processing units (PUs) design which can be dynamically grouped or split to support the tiling flexibility and enable efficient hardware resource sharing. As for quantization, we considered the recently proposed Incremental Network Quantization (INQ) algorithm which uses low bit representation of weights in power of 2 format, and hence is able to represent the weights with minimum computing complexity since expensive multiplication can be transferred into cheap shift operation. We further propose an approximate shifter based processing element (PE) design as the fundamental building block of the PUs to facilitate the convolution computation. At last, a case study of RTL-level implementation of INQ quantized AlexNet is realized on a standalone FPGA, Stratix V. Compared with the state-of-art designs, our accelerator achieves 1.87x higher performance, which demonstrates the efficiency of the proposed design methods.
{"title":"A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA","authors":"Chi Fung Brian Fong, Jiandong Mu, Wei Zhang","doi":"10.1109/ISVLSI.2019.00015","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00015","url":null,"abstract":"Convolutional neural networks (CNNs) are rapidly expanding and being applied to a vast range of applications. Despite its popularity, deploying CNNs on a portable system is challenging due to enormous data volume, intensive computation, and frequent memory access. Hence, many approaches have been proposed to reduce the CNN model complexity, such as model pruning and quantization. However, it also brings new challenges. For example, existing designs usually adopted channel dimension tiling which requires regular channel number. After pruning, the channel number may become highly irregular which will incur heavy zero padding and large resource waste. As for quantization, simple aggressive bit reduction usually results in large accuracy drop. In order to address these challenges, in this work, firstly we propose to use row-based tiling in the kernel dimension to adapt to different kernel sizes and channel numbers and significantly reduce the zero padding. Moreover, we developed the configurable processing units (PUs) design which can be dynamically grouped or split to support the tiling flexibility and enable efficient hardware resource sharing. As for quantization, we considered the recently proposed Incremental Network Quantization (INQ) algorithm which uses low bit representation of weights in power of 2 format, and hence is able to represent the weights with minimum computing complexity since expensive multiplication can be transferred into cheap shift operation. We further propose an approximate shifter based processing element (PE) design as the fundamental building block of the PUs to facilitate the convolution computation. At last, a case study of RTL-level implementation of INQ quantized AlexNet is realized on a standalone FPGA, Stratix V. Compared with the state-of-art designs, our accelerator achieves 1.87x higher performance, which demonstrates the efficiency of the proposed design methods.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"23 1","pages":"31-36"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73041658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00102
Amin Rezaei, J. Gu, H. Zhou
The high cost of IC design has made chip protection one of the first priorities of the semiconductor industry. In addition, with the growing number of untrusted foundries, the possibility of inside foundry attack is escalating. However, by taking advantage of polymorphic gates, the layouts of the circuits with different functionalities look exactly identical, making it impossible even for an inside foundry attacker to distinguish the defined functionality of an IC by looking at its layout. Moreover, since memristor is compatible with CMOS structure, it is possible to efficiently design hybrid memristor-CMOS circuits. In this paper, we propose a hardware obfuscation method based on polymorphic hybrid memristor-CMOS technology. Overhead of the polymorphic designs and the time complexity of possible attacks are discussed.
{"title":"Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries","authors":"Amin Rezaei, J. Gu, H. Zhou","doi":"10.1109/ISVLSI.2019.00102","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00102","url":null,"abstract":"The high cost of IC design has made chip protection one of the first priorities of the semiconductor industry. In addition, with the growing number of untrusted foundries, the possibility of inside foundry attack is escalating. However, by taking advantage of polymorphic gates, the layouts of the circuits with different functionalities look exactly identical, making it impossible even for an inside foundry attacker to distinguish the defined functionality of an IC by looking at its layout. Moreover, since memristor is compatible with CMOS structure, it is possible to efficiently design hybrid memristor-CMOS circuits. In this paper, we propose a hardware obfuscation method based on polymorphic hybrid memristor-CMOS technology. Overhead of the polymorphic designs and the time complexity of possible attacks are discussed.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"23 1","pages":"535-540"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75333020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00013
Arish S, Sharad Sinha, S. K G
Implementation of convolutional neural networks (CNNs) on resource constrained devices like FPGA (example: Zynq) etc. is important for intelligence in edge computing. This paper presents and discusses different hardware optimization methods that were employed to design a CNN model that is amenable to such devices, in general. Adaptive processing, exploitation of parallelism etc. are employed to show the superior performance of proposed methods over state of the art.
{"title":"Optimization of Convolutional Neural Networks on Resource Constrained Devices","authors":"Arish S, Sharad Sinha, S. K G","doi":"10.1109/ISVLSI.2019.00013","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00013","url":null,"abstract":"Implementation of convolutional neural networks (CNNs) on resource constrained devices like FPGA (example: Zynq) etc. is important for intelligence in edge computing. This paper presents and discusses different hardware optimization methods that were employed to design a CNN model that is amenable to such devices, in general. Adaptive processing, exploitation of parallelism etc. are employed to show the superior performance of proposed methods over state of the art.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"26 1","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78945133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00118
Yier Jin
As computing devices become more commonplace in every day life, we have seen an increase of possible attacks on commercial devices and critical infrastructure. As a result, both academia and industry have proposed solutions to mitigate or outright eliminate the ever expanding set of viable targets. Initially, this resulted in an influx of software-based defenses against these emerging threats. Unfortunately, it was found that software solutions could be bypassed with more advanced attacks and often resulted in high performance overhead. As such, hardware-assisted security defenses have been developed to provide improved security while keeping performance overhead to manageable levels, especially for IoT devices. In this paper, we will provide a survey of prominent hardware-assisted security defenses. We will enumerate the attacks these defenses aim to protect, as well as their effectiveness. We will also discuss the implications in both performance and system design. A comparison between approaches that target the same set of issues, and possible directions for future research will be presented.
{"title":"Towards Hardware-Assisted Security for IoT Systems","authors":"Yier Jin","doi":"10.1109/ISVLSI.2019.00118","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00118","url":null,"abstract":"As computing devices become more commonplace in every day life, we have seen an increase of possible attacks on commercial devices and critical infrastructure. As a result, both academia and industry have proposed solutions to mitigate or outright eliminate the ever expanding set of viable targets. Initially, this resulted in an influx of software-based defenses against these emerging threats. Unfortunately, it was found that software solutions could be bypassed with more advanced attacks and often resulted in high performance overhead. As such, hardware-assisted security defenses have been developed to provide improved security while keeping performance overhead to manageable levels, especially for IoT devices. In this paper, we will provide a survey of prominent hardware-assisted security defenses. We will enumerate the attacks these defenses aim to protect, as well as their effectiveness. We will also discuss the implications in both performance and system design. A comparison between approaches that target the same set of issues, and possible directions for future research will be presented.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"196 1","pages":"632-637"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76958171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00108
Shuo Li, Xiaolin Xu, W. Burleson
Measuring timing signals of sub-picosecond has become an urgent need in today's high-speed electronics design. However, conventional timing measurement devices are either built with analog circuits that are hard to integrate with digital systems or differential delay-lines whose resolution is significantly impacted by the process variations of a circuit or environmental conditions. In this work, we present a novel all-digital timing measurement circuit: PVTMC, which for the first time, constructively leverages process variations to measure timing signals of sub-picosecond duration. We show that PVTMC achieves high resolution and robust performance against environmental fluctuations. A simple random search-based method is proposed to speed up the measurements and improve its accuracy. We also demonstrate that PVTMC is compatible with most prevalent CMOS technology nodes, as well as FPGA implementations due to the existence of process variations.
{"title":"PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations","authors":"Shuo Li, Xiaolin Xu, W. Burleson","doi":"10.1109/ISVLSI.2019.00108","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00108","url":null,"abstract":"Measuring timing signals of sub-picosecond has become an urgent need in today's high-speed electronics design. However, conventional timing measurement devices are either built with analog circuits that are hard to integrate with digital systems or differential delay-lines whose resolution is significantly impacted by the process variations of a circuit or environmental conditions. In this work, we present a novel all-digital timing measurement circuit: PVTMC, which for the first time, constructively leverages process variations to measure timing signals of sub-picosecond duration. We show that PVTMC achieves high resolution and robust performance against environmental fluctuations. A simple random search-based method is proposed to speed up the measurements and improve its accuracy. We also demonstrate that PVTMC is compatible with most prevalent CMOS technology nodes, as well as FPGA implementations due to the existence of process variations.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"10 1","pages":"574-579"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73943800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00106
D. Stathis, Yu Yang, S. Tewari, A. Hemani, Kolin Paul, M. Grabherr, Rafi Ahmad
In this paper we explore the design space of a self-organizing map (SOM) used for rapid and accurate identification of bacterial genomes. This is an important health care problem because even in Europe, 70% of prescriptions for antibiotics is wrong. The SOM is trained on Next Generation Sequencing (NGS) data and is able to identify the exact strain of bacteria. This is in contrast to conventional methods that require genome assembly to identify the bacterial strain. SOM has been implemented as an synchoros VLSI design and shown to have 3-4 orders better computational efficiency compared to GPUs. To further lower the energy consumption, we exploit the robustness of SOM by successively lowering the resolution to gain further improvements in efficiency and lower the implementation cost without substantially sacrificing the accuracy. We do an in depth analysis of the reduction in resolution vs. loss in accuracy as the basis for designing a system with the lowest cost and acceptable accuracy using NGS data from samples containing multiple bacteria from the labs of one of the co-authors. The objective of this method is to design a bacterial recognition system for battery operated clinical use where the area, power and performance are of critical importance. We demonstrate that with 39% loss in accuracy in 12 bits and 1% in 16 bit representation can yield significant savings in energy and area.
{"title":"Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps","authors":"D. Stathis, Yu Yang, S. Tewari, A. Hemani, Kolin Paul, M. Grabherr, Rafi Ahmad","doi":"10.1109/ISVLSI.2019.00106","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00106","url":null,"abstract":"In this paper we explore the design space of a self-organizing map (SOM) used for rapid and accurate identification of bacterial genomes. This is an important health care problem because even in Europe, 70% of prescriptions for antibiotics is wrong. The SOM is trained on Next Generation Sequencing (NGS) data and is able to identify the exact strain of bacteria. This is in contrast to conventional methods that require genome assembly to identify the bacterial strain. SOM has been implemented as an synchoros VLSI design and shown to have 3-4 orders better computational efficiency compared to GPUs. To further lower the energy consumption, we exploit the robustness of SOM by successively lowering the resolution to gain further improvements in efficiency and lower the implementation cost without substantially sacrificing the accuracy. We do an in depth analysis of the reduction in resolution vs. loss in accuracy as the basis for designing a system with the lowest cost and acceptable accuracy using NGS data from samples containing multiple bacteria from the labs of one of the co-authors. The objective of this method is to design a bacterial recognition system for battery operated clinical use where the area, power and performance are of critical importance. We demonstrate that with 39% loss in accuracy in 12 bits and 1% in 16 bit representation can yield significant savings in energy and area.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"23 1","pages":"560-567"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74400303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00050
Xiangyu Chen, Yasuhiro Takahashi
This work presents the design and performance of a transimpedance amplifier (TIA) implemented in a 180nm CMOS technology. The introduced TIA uses a floating active inductor (FAI) based on gyrator-C structure, which is why it can increase the bandwidth while occupying a smaller chip area. And we have explained the schematic and characteristics of the gyrator-C structure and FAI. In addition, the proposed TIA also uses the combination of capacitive degeneration, broadband matching network, and the regulated cascode (RGC) input stage, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with butterworth response, to enhance the bandwidth and the gain. The TIA is implemented in 0.18 m Rohm CMOS technology and a 1.8-V supply. The transimpedance amplifier achieves a transimpedance gain of 41dBΩ and -3 dB frequency of 10 GHz with 0.1pF total input capacitance. Layout size of the proposed TIA is 180 μm × 118 μm.
{"title":"Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor","authors":"Xiangyu Chen, Yasuhiro Takahashi","doi":"10.1109/ISVLSI.2019.00050","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00050","url":null,"abstract":"This work presents the design and performance of a transimpedance amplifier (TIA) implemented in a 180nm CMOS technology. The introduced TIA uses a floating active inductor (FAI) based on gyrator-C structure, which is why it can increase the bandwidth while occupying a smaller chip area. And we have explained the schematic and characteristics of the gyrator-C structure and FAI. In addition, the proposed TIA also uses the combination of capacitive degeneration, broadband matching network, and the regulated cascode (RGC) input stage, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with butterworth response, to enhance the bandwidth and the gain. The TIA is implemented in 0.18 m Rohm CMOS technology and a 1.8-V supply. The transimpedance amplifier achieves a transimpedance gain of 41dBΩ and -3 dB frequency of 10 GHz with 0.1pF total input capacitance. Layout size of the proposed TIA is 180 μm × 118 μm.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"230-234"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86905165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00074
Yunxiang Zhang, Xiaokun Yang, Lei Wu, J. Andrian
This paper presents a case study of approximate design with Field-Programmable Gate Array (FPGA), combining an application of a color to grayscale converter and an open image/video processing platform with Verilog hardware description language (HDL). First of all, by integrating two approximations of adders and two approximations of multipliers, together with the exact design, nine different approximations of the design on color to grayscale converter are offered. Second, the image processing platform is presented to demonstrate the proposed work on Nexys-4 FPGA, enabling to capture color images through a low-cost OV7670 camera and display the grayscale results of images on a VGA-interfaced monitor. Experimental results show the difference between different approximations of the design, providing a range of design options corresponding to different quality constrains.
{"title":"A Case Study On Approximate FPGA Design With an Open-Source Image Processing Platform","authors":"Yunxiang Zhang, Xiaokun Yang, Lei Wu, J. Andrian","doi":"10.1109/ISVLSI.2019.00074","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00074","url":null,"abstract":"This paper presents a case study of approximate design with Field-Programmable Gate Array (FPGA), combining an application of a color to grayscale converter and an open image/video processing platform with Verilog hardware description language (HDL). First of all, by integrating two approximations of adders and two approximations of multipliers, together with the exact design, nine different approximations of the design on color to grayscale converter are offered. Second, the image processing platform is presented to demonstrate the proposed work on Nexys-4 FPGA, enabling to capture color images through a low-cost OV7670 camera and display the grayscale results of images on a VGA-interfaced monitor. Experimental results show the difference between different approximations of the design, providing a range of design options corresponding to different quality constrains.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"10 1","pages":"372-377"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88591287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00062
Shichao Yu, Weiqiang Liu, Máire O’Neill
Over the past 10 years, various Hardware Trojan (HT) detection techniques have been proposed by the research community. However, the development of HT benchmark suites for testing and evaluating HT detection techniques lags behind. The number of HT-infected circuits available in current public HT benchmarks is somewhat limited and the circuits lack diversity in structure. Therefore, this paper proposes a new method to generate HTs using a highly configurable generation platform based on transition probability. The generation platform is highly configurable in terms of the HT trigger condition, trigger type, payload type and in the number and variety of HT-infected circuits that can be generated. In this research the transition probability of netlists is employed to identify rarely activated internal nodes to target for HT insertion rather than functional simulation as utilised in previous research. The authors believe transition probability provides a more realistic reflection of the netlist activity for use in determining the appropriate position for HT insertion. Finally, the generated HT-infected circuits are tested by a machine learning (ML)-based HT detection technique, which is known as Controllability and Observability for HT Detection (COTD). The resulting false positive and false negative rates illustrate the feasibility of the benchmark suite.
{"title":"An Improved Automatic Hardware Trojan Generation Platform","authors":"Shichao Yu, Weiqiang Liu, Máire O’Neill","doi":"10.1109/ISVLSI.2019.00062","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00062","url":null,"abstract":"Over the past 10 years, various Hardware Trojan (HT) detection techniques have been proposed by the research community. However, the development of HT benchmark suites for testing and evaluating HT detection techniques lags behind. The number of HT-infected circuits available in current public HT benchmarks is somewhat limited and the circuits lack diversity in structure. Therefore, this paper proposes a new method to generate HTs using a highly configurable generation platform based on transition probability. The generation platform is highly configurable in terms of the HT trigger condition, trigger type, payload type and in the number and variety of HT-infected circuits that can be generated. In this research the transition probability of netlists is employed to identify rarely activated internal nodes to target for HT insertion rather than functional simulation as utilised in previous research. The authors believe transition probability provides a more realistic reflection of the netlist activity for use in determining the appropriate position for HT insertion. Finally, the generated HT-infected circuits are tested by a machine learning (ML)-based HT detection technique, which is known as Controllability and Observability for HT Detection (COTD). The resulting false positive and false negative rates illustrate the feasibility of the benchmark suite.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"2000 1","pages":"302-307"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88288545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00120
S. Shahsavani, Massoud Pedram
This paper presents a novel method for evaluating the robustness of single flux quantum (SFQ) logic cells in a superconducting electronic circuit. The proposed method improves the state-of-the-art by accounting for the global sources of variation, clustering cell parameters into hyper-parameters, and considering the co-dependency of these hyper-parameters when calculating a feasible parameter region in which cell functions correctly, given any combination of the parameter values. The average parametric yield inside the reported feasible parameter region is more than 98%. Additionally, a machine learning based method is presented to estimate the parametric yield both inside and outside the feasible parameter region. The average accuracy of the developed yield model is 96% for five SFQ cells.
{"title":"A Hyper-Parameter Based Margin Calculation Algorithm for Single Flux Quantum Logic Cells","authors":"S. Shahsavani, Massoud Pedram","doi":"10.1109/ISVLSI.2019.00120","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00120","url":null,"abstract":"This paper presents a novel method for evaluating the robustness of single flux quantum (SFQ) logic cells in a superconducting electronic circuit. The proposed method improves the state-of-the-art by accounting for the global sources of variation, clustering cell parameters into hyper-parameters, and considering the co-dependency of these hyper-parameters when calculating a feasible parameter region in which cell functions correctly, given any combination of the parameter values. The average parametric yield inside the reported feasible parameter region is more than 98%. Additionally, a machine learning based method is presented to estimate the parametric yield both inside and outside the feasible parameter region. The average accuracy of the developed yield model is 96% for five SFQ cells.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"38 1","pages":"645-650"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78037517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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