Bayesian inference is an effective approach to capture the model uncertainty as well as tackle the over-fitting problem in deep neural networks. Recently Bayesian neural networks (BNNs) are becoming more and more popular and have succeeded in many recognition tasks. However, the BNNs inference procedure requires numerous memory access operations due to the resulted sampling networks. In this paper, a near memory architecture is proposed for accelerating BNN inference by introducing additional memory units near the processing units. The near memory architecture could cache the frequently accessed data to reduce the data movement efficiently. Minimizing the expensive data movements between memory units and computation units contributes to cutting down the latency and energy consumption. Comparing with the traditional approach, the simulation results show that the proposed architecture reduces the energy consumption by 9% and achieves a 1:6 speedup at the cost of 4% area overhead.
{"title":"Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration","authors":"Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, W. Kang, Youguang Zhang, Weisheng Zhao","doi":"10.1109/ISVLSI.2019.00045","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00045","url":null,"abstract":"Bayesian inference is an effective approach to capture the model uncertainty as well as tackle the over-fitting problem in deep neural networks. Recently Bayesian neural networks (BNNs) are becoming more and more popular and have succeeded in many recognition tasks. However, the BNNs inference procedure requires numerous memory access operations due to the resulted sampling networks. In this paper, a near memory architecture is proposed for accelerating BNN inference by introducing additional memory units near the processing units. The near memory architecture could cache the frequently accessed data to reduce the data movement efficiently. Minimizing the expensive data movements between memory units and computation units contributes to cutting down the latency and energy consumption. Comparing with the traditional approach, the simulation results show that the proposed architecture reduces the energy consumption by 9% and achieves a 1:6 speedup at the cost of 4% area overhead.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"115 1","pages":"203-206"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80822378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00056
A. Gordon-Ross, S. Abdel-Hafeez, Mohamad Hammam Alsafrjalani
We present an efficient synchronous first-in first-out (FIFO) buffer for enhanced memory management units and inter-core data communication in manycore systems. Our design significantly reduces hardware overhead and eliminates latency delays by using both the rising and falling clock edges during read and write, which makes our design suitable for increased processing element (PE) utilization by increasing the memory bandwidth in complex network and system on-chip solutions. Compared to prior work, our design can operate 5X faster at the same supply voltage, or up to 44X faster with a 2.5X increase in supply voltage. Our design's total power consumption is 7.8 mW with a total transistor count of 34,470.
{"title":"A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems","authors":"A. Gordon-Ross, S. Abdel-Hafeez, Mohamad Hammam Alsafrjalani","doi":"10.1109/ISVLSI.2019.00056","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00056","url":null,"abstract":"We present an efficient synchronous first-in first-out (FIFO) buffer for enhanced memory management units and inter-core data communication in manycore systems. Our design significantly reduces hardware overhead and eliminates latency delays by using both the rising and falling clock edges during read and write, which makes our design suitable for increased processing element (PE) utilization by increasing the memory bandwidth in complex network and system on-chip solutions. Compared to prior work, our design can operate 5X faster at the same supply voltage, or up to 44X faster with a 2.5X increase in supply voltage. Our design's total power consumption is 7.8 mW with a total transistor count of 34,470.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"19 1","pages":"265-270"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72715188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00116
Süleyman Savas, Y. Atwa, T. Nordström, Z. Ul-Abdin
This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards. The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance. Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor's floating point unit or be used as a stand-alone accelerator.
{"title":"Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit","authors":"Süleyman Savas, Y. Atwa, T. Nordström, Z. Ul-Abdin","doi":"10.1109/ISVLSI.2019.00116","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00116","url":null,"abstract":"This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards. The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance. Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor's floating point unit or be used as a stand-alone accelerator.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"64 1","pages":"621-626"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74504121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00040
R. Sunil, K. SiddharthR., Nithin Y. B. Kumar, M. H. Vasantha
This paper proposes an asynchronous analog to digital converter (ADC) for wireless surveillance video camera applications. The proposed architecture is based on a nonuniform sampling, whose sampling instants depend on the input voltage amplitude. The proposed design has the power performance advantage, by using a power down comparator, for an input voltage close to the extreme values. Thus, the proposed architecture is suitable for the applications in which the input signal rarely assumes voltage values closer to the mid-range amplitude voltage. The design is simulated, at the transistor level, in a 180-nm CMOS technology. The results show that about 96.7% of the power can be saved in the best case (input voltage in the vicinity of extreme values) when compared to a conventional flash ADC.
{"title":"An Asynchronous Analog to Digital Converter for Video Camera Applications","authors":"R. Sunil, K. SiddharthR., Nithin Y. B. Kumar, M. H. Vasantha","doi":"10.1109/ISVLSI.2019.00040","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00040","url":null,"abstract":"This paper proposes an asynchronous analog to digital converter (ADC) for wireless surveillance video camera applications. The proposed architecture is based on a nonuniform sampling, whose sampling instants depend on the input voltage amplitude. The proposed design has the power performance advantage, by using a power down comparator, for an input voltage close to the extreme values. Thus, the proposed architecture is suitable for the applications in which the input signal rarely assumes voltage values closer to the mid-range amplitude voltage. The design is simulated, at the transistor level, in a 180-nm CMOS technology. The results show that about 96.7% of the power can be saved in the best case (input voltage in the vicinity of extreme values) when compared to a conventional flash ADC.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"358 1","pages":"175-180"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74147311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00084
Saman Froehlich, S. Shirinzadeh, R. Drechsler
Resistive Random Access Memory (ReRAM) is an emerging non-volatile technology with high scalability and zero standby power which allows to perform logic primitives. ReRAM crossbar arrays combined with a CMOS ubstrate provide a wide range of benefits in logic synthesis. In this paper, we propose to exploit ReRAM in sequential circuits as it provides both required features as a computational and memory element. We propose a fully automated synthesis approach based on graph representations (i.e., BDDs and AIGs) for synthesis of sequential circuits on hybrid CMOS-ReRAM architectures. We propose an algorithm to efficiently divide the target function into two independent computational parts. This allows to merge part of the computation within a ReRAM unit and utilize its computational capabilities besides its function as a sequential element in order to minimize the CMOS overhead. Experimental results show that ReRAM allows for a significant reduction in CMOS size of up to 40.9% for BDDs with an average of 8.7% for BDDs and up to 10.1% with an average of 3.2% for AIGs.
{"title":"Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits","authors":"Saman Froehlich, S. Shirinzadeh, R. Drechsler","doi":"10.1109/ISVLSI.2019.00084","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00084","url":null,"abstract":"Resistive Random Access Memory (ReRAM) is an emerging non-volatile technology with high scalability and zero standby power which allows to perform logic primitives. ReRAM crossbar arrays combined with a CMOS ubstrate provide a wide range of benefits in logic synthesis. In this paper, we propose to exploit ReRAM in sequential circuits as it provides both required features as a computational and memory element. We propose a fully automated synthesis approach based on graph representations (i.e., BDDs and AIGs) for synthesis of sequential circuits on hybrid CMOS-ReRAM architectures. We propose an algorithm to efficiently divide the target function into two independent computational parts. This allows to merge part of the computation within a ReRAM unit and utilize its computational capabilities besides its function as a sequential element in order to minimize the CMOS overhead. Experimental results show that ReRAM allows for a significant reduction in CMOS size of up to 40.9% for BDDs with an average of 8.7% for BDDs and up to 10.1% with an average of 3.2% for AIGs.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"431-436"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81075587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00065
Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, A. Ganguly
Wireless Networks-on-Chips (NoCs) have emerged as a panacea to the non-scalable multi-hop data transmission paths in traditional wired NoC architectures. Using low-power transceivers in NoC switches, novel Wireless NoC (WiNoC) architectures have been shown to achieve higher energy efficiency with improved peak bandwidth and reduced on-chip data transfer latency. However, using wireless interconnects for data transfer within a chip makes the on-chip communications vulnerable to various security threats from either external attackers or internal hardware Trojans (HTs). In this work, we propose a mechanism to make the wireless communication in a WiNoC secure against persistent jamming based Denial-of-Service attacks from both external and internal attackers. Persistent jamming attacks on the on-chip wireless medium will cause interference in data transfer over the duration of the attack resulting in errors in contiguous bits, known as burst errors. Therefore, we use a burst error correction code to monitor the rate of burst errors received over the wireless medium and deploy a Machine Learning (ML) classifier to detect the persistent jamming attack and distinguish it from random burst errors. In the event of jamming attack, alternate routing strategies are proposed to avoid the DoS attack over the wireless medium, so that a secure data transfer can be sustained even in the presence of jamming. We evaluate the proposed technique on a secure WiNoC in the presence of DoS attacks. It has been observed that with the proposed defense mechanisms, WiNoC can outperform a wired NoC even in presence of attacks in terms of performance and security. On an average, 99.87% attack detection was achieved with the chosen ML Classifiers. A bandwidth degradation of <3% is experienced in the event of internal attack, while the wireless interconnects are disabled in the presence of an external attacker.
{"title":"Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks","authors":"Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, A. Ganguly","doi":"10.1109/ISVLSI.2019.00065","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00065","url":null,"abstract":"Wireless Networks-on-Chips (NoCs) have emerged as a panacea to the non-scalable multi-hop data transmission paths in traditional wired NoC architectures. Using low-power transceivers in NoC switches, novel Wireless NoC (WiNoC) architectures have been shown to achieve higher energy efficiency with improved peak bandwidth and reduced on-chip data transfer latency. However, using wireless interconnects for data transfer within a chip makes the on-chip communications vulnerable to various security threats from either external attackers or internal hardware Trojans (HTs). In this work, we propose a mechanism to make the wireless communication in a WiNoC secure against persistent jamming based Denial-of-Service attacks from both external and internal attackers. Persistent jamming attacks on the on-chip wireless medium will cause interference in data transfer over the duration of the attack resulting in errors in contiguous bits, known as burst errors. Therefore, we use a burst error correction code to monitor the rate of burst errors received over the wireless medium and deploy a Machine Learning (ML) classifier to detect the persistent jamming attack and distinguish it from random burst errors. In the event of jamming attack, alternate routing strategies are proposed to avoid the DoS attack over the wireless medium, so that a secure data transfer can be sustained even in the presence of jamming. We evaluate the proposed technique on a secure WiNoC in the presence of DoS attacks. It has been observed that with the proposed defense mechanisms, WiNoC can outperform a wired NoC even in presence of attacks in terms of performance and security. On an average, 99.87% attack detection was achieved with the chosen ML Classifiers. A bandwidth degradation of <3% is experienced in the event of internal attack, while the wireless interconnects are disabled in the presence of an external attacker.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"33 1","pages":"320-325"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80432429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00038
O. Elgawi, A. Mutawa, Afaq Ahmad
We propose an energy-efficient embedded binarized Support Vector Machine (eBSVM) architecture and present its implementation on low-power FPGA accelerator. With binarized input activations and output weights, the dot product operation (float-point multiplications and additions) can be replaced by bitwise XNOR and popcount operations, respectively. The proposed accelerator computes the two binarized vectors using hamming weights, resulting in reduced execution time and energy consumption. Evaluation results show that eBSVM demonstrates performance and performance-per-Watt on MNIST and CIFAR-10 datasets compared to its fixed point (FP) counterpart implemented in CPU and GPU with small accuracy degradation.
{"title":"Energy-Efficient Embedded Inference of SVMs on FPGA","authors":"O. Elgawi, A. Mutawa, Afaq Ahmad","doi":"10.1109/ISVLSI.2019.00038","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00038","url":null,"abstract":"We propose an energy-efficient embedded binarized Support Vector Machine (eBSVM) architecture and present its implementation on low-power FPGA accelerator. With binarized input activations and output weights, the dot product operation (float-point multiplications and additions) can be replaced by bitwise XNOR and popcount operations, respectively. The proposed accelerator computes the two binarized vectors using hamming weights, resulting in reduced execution time and energy consumption. Evaluation results show that eBSVM demonstrates performance and performance-per-Watt on MNIST and CIFAR-10 datasets compared to its fixed point (FP) counterpart implemented in CPU and GPU with small accuracy degradation.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"64 12","pages":"164-168"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91465891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00058
Brett Mathis, J. Stine
This paper demonstrates the design of a fully IEEE 754-compliant floating-point adder and subtractor. This design focuses on creating a high-speed, low-power design while still adhering completely to the IEEE 754 standard. This design's novelty comes in the form of it's 64-bit prefix adder structure, and the parallelization of it's subcomponents. The adder/subtractor has full support for 32-bit and 64-bit operands, as well as the ability to convert integer operands to the IEEE 754 standard. Synthesis results presented use a cmos32soi 32nm CMOS technology and ARM standard-cells.
{"title":"A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter","authors":"Brett Mathis, J. Stine","doi":"10.1109/ISVLSI.2019.00058","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00058","url":null,"abstract":"This paper demonstrates the design of a fully IEEE 754-compliant floating-point adder and subtractor. This design focuses on creating a high-speed, low-power design while still adhering completely to the IEEE 754 standard. This design's novelty comes in the form of it's 64-bit prefix adder structure, and the parallelization of it's subcomponents. The adder/subtractor has full support for 32-bit and 64-bit operands, as well as the ability to convert integer operands to the IEEE 754 standard. Synthesis results presented use a cmos32soi 32nm CMOS technology and ARM standard-cells.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"41 1","pages":"278-283"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85011373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00014
Xinyi Zhang, Weiwen Jiang, Yiyu Shi, J. Hu
Neural Architecture Search (NAS), that automatically identifies the best network architecture, is a promising technique to respond to the ever-growing demand for application-specific Artificial Intelligence (AI). On the other hand, a large number of research efforts have been put on implementing and optimizing AI applications on the hardware. Out of all leading computation platforms, Field Programmable Gate Arrays (FPGAs) stand out due to its flexibility and versatility over ASICs and its efficiency over CPUs and GPUs. To identify the best neural architecture and hardware implementation pair, a number of research works are emerging to involve the awareness of hardware efficiency in the NAS process, which is called "hardware-aware NAS". Unlike the conventional NAS with a mono-criteria of accuracy, hardware-aware NAS is a multi-objective optimization problem, which aims to identify the best network and hardware pair to maximize accuracy with guaranteed hardware efficiency. Most recently, the co-design of neural architecture and hardware has been put forward to further push forward the Pareto frontier between accuracy and efficiency trade-off. This paper will review and discuss the current progress in the neural architecture search and the implementation on hardware.
{"title":"When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design","authors":"Xinyi Zhang, Weiwen Jiang, Yiyu Shi, J. Hu","doi":"10.1109/ISVLSI.2019.00014","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00014","url":null,"abstract":"Neural Architecture Search (NAS), that automatically identifies the best network architecture, is a promising technique to respond to the ever-growing demand for application-specific Artificial Intelligence (AI). On the other hand, a large number of research efforts have been put on implementing and optimizing AI applications on the hardware. Out of all leading computation platforms, Field Programmable Gate Arrays (FPGAs) stand out due to its flexibility and versatility over ASICs and its efficiency over CPUs and GPUs. To identify the best neural architecture and hardware implementation pair, a number of research works are emerging to involve the awareness of hardware efficiency in the NAS process, which is called \"hardware-aware NAS\". Unlike the conventional NAS with a mono-criteria of accuracy, hardware-aware NAS is a multi-objective optimization problem, which aims to identify the best network and hardware pair to maximize accuracy with guaranteed hardware efficiency. Most recently, the co-design of neural architecture and hardware has been put forward to further push forward the Pareto frontier between accuracy and efficiency trade-off. This paper will review and discuss the current progress in the neural architecture search and the implementation on hardware.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"20 1","pages":"25-30"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89423416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISVLSI.2019.00070
S. Swami, K. Mohanram
Computing systems that integrate advanced non-volatile memories (NVMs) are vulnerable to several security attacks that threaten (i) data confidentiality, (ii) data availability, and (iii) data integrity. This paper proposes Architectures for Smart Security of NVMs (AS-SET), which integrates five low overhead, high performance security solutions—SECRET [1], COVERT [2], ACME [3], ARSE-NAL [4], and STASH [5]—to thwart these attacks on NVM systems. SECRET is a low cost security solution that employs counter mode encryption (CME) for data confidentiality in multi-/triple-level cell (i.e., MLC/TLC) NVMs. COVERT and ACME complement SECRET to improve system availability of CME. ARSENAL integrates CME and Bonsai Merkle Tree (BMT) authentication to thwart data confidentiality and integrity attacks, respectively, in NVMs and simultaneously enables instant data recovery (IDR) on power/system failures. Finally, STASH is the first comprehensive end-to-end security architecture for state-of-the-art smart hybrid memories (SHMs). STASH integrates (i) CME for data confidentiality, (ii) page-level MT authentication for data integrity, (iii) recovery-compatible MT updates to withstand power or system failures, and (iv) page-migration friendly security meta-data management. This paper thus addresses the core security challenges of next-generation NVM systems.
{"title":"ASSET: Architectures for Smart Security of Non-Volatile Memories","authors":"S. Swami, K. Mohanram","doi":"10.1109/ISVLSI.2019.00070","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00070","url":null,"abstract":"Computing systems that integrate advanced non-volatile memories (NVMs) are vulnerable to several security attacks that threaten (i) data confidentiality, (ii) data availability, and (iii) data integrity. This paper proposes Architectures for Smart Security of NVMs (AS-SET), which integrates five low overhead, high performance security solutions—SECRET [1], COVERT [2], ACME [3], ARSE-NAL [4], and STASH [5]—to thwart these attacks on NVM systems. SECRET is a low cost security solution that employs counter mode encryption (CME) for data confidentiality in multi-/triple-level cell (i.e., MLC/TLC) NVMs. COVERT and ACME complement SECRET to improve system availability of CME. ARSENAL integrates CME and Bonsai Merkle Tree (BMT) authentication to thwart data confidentiality and integrity attacks, respectively, in NVMs and simultaneously enables instant data recovery (IDR) on power/system failures. Finally, STASH is the first comprehensive end-to-end security architecture for state-of-the-art smart hybrid memories (SHMs). STASH integrates (i) CME for data confidentiality, (ii) page-level MT authentication for data integrity, (iii) recovery-compatible MT updates to withstand power or system failures, and (iv) page-migration friendly security meta-data management. This paper thus addresses the core security challenges of next-generation NVM systems.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"182 1","pages":"348-353"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77589898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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