Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510501
D. Johns, D. Essig
This tutorial paper discusses typical architectures and future challenges in designing integrated circuits for data transmission over twisted-pair wire channels. To highlight the various architectural approaches, two main applications are addressed-HDSL and fast-Ethernet. Following a discussion of twisted-pair cable modelling, common building blocks and possible trade-offs are described. Finally, future challenges facing integrated circuit designers are presented.
{"title":"Integrated circuits for data transmission over twisted-pair channels","authors":"D. Johns, D. Essig","doi":"10.1109/CICC.1996.510501","DOIUrl":"https://doi.org/10.1109/CICC.1996.510501","url":null,"abstract":"This tutorial paper discusses typical architectures and future challenges in designing integrated circuits for data transmission over twisted-pair wire channels. To highlight the various architectural approaches, two main applications are addressed-HDSL and fast-Ethernet. Following a discussion of twisted-pair cable modelling, common building blocks and possible trade-offs are described. Finally, future challenges facing integrated circuit designers are presented.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"11 1","pages":"5-12"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85959145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510531
D. How
This paper describes the architecture of an entirely self-clocked FPGA. Such an FPGA would avoid clock distribution problems, facilitate circuit composition and increase the amount of hardware concurrency, as well as reliably operate at its maximum speed without timing analysis. These unique advantages would be of great use in many functional simulation and logic emulation applications targeting larger designs requiring many FPGAs.
{"title":"A self clocked FPGA for general purpose logic emulation","authors":"D. How","doi":"10.1109/CICC.1996.510531","DOIUrl":"https://doi.org/10.1109/CICC.1996.510531","url":null,"abstract":"This paper describes the architecture of an entirely self-clocked FPGA. Such an FPGA would avoid clock distribution problems, facilitate circuit composition and increase the amount of hardware concurrency, as well as reliably operate at its maximum speed without timing analysis. These unique advantages would be of great use in many functional simulation and logic emulation applications targeting larger designs requiring many FPGAs.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"68 1","pages":"148-151"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83472110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510586
S. Au, B. Leung
The design of a low power, low voltage, 12-bit 8 kHz bandwidth /spl Sigma//spl Delta/ modulator that achieves 0.34 mW power consumption at 1.95 V supply is described. The modulator employs a novel architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multi-stage /spl Sigma//spl Delta/ modulators, this architecture is very tolerant to the modest DC gain of low voltage opamps. The architecture, together with special circuit techniques, permits a low voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2 /spl mu/m CMOS technology.
{"title":"A 1.95 V, 0.34 mW 12-bit sigma-delta modulator stabilized by local feedback loops","authors":"S. Au, B. Leung","doi":"10.1109/CICC.1996.510586","DOIUrl":"https://doi.org/10.1109/CICC.1996.510586","url":null,"abstract":"The design of a low power, low voltage, 12-bit 8 kHz bandwidth /spl Sigma//spl Delta/ modulator that achieves 0.34 mW power consumption at 1.95 V supply is described. The modulator employs a novel architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multi-stage /spl Sigma//spl Delta/ modulators, this architecture is very tolerant to the modest DC gain of low voltage opamps. The architecture, together with special circuit techniques, permits a low voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2 /spl mu/m CMOS technology.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"31 1","pages":"411-414"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83739955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510512
K. Tomobe, T. Takahashi, M. Kawashima, Y. Sonobe, T. Kiyuna, S. Yamamoto
A 1860 kG CMOS gate array with a high speed I/O circuit using 0.35 /spl mu/m CMOS process technology, has been developed. 300 MHz synchronous data transmission through a 30 cm line has been achieved with a flip-flop circuit which can directly receive and store a low voltage swing signal. This circuit technique reduces the latency time of data transmission between 2 LSIs by as much as 1.7 ns compared with conventional circuits.
采用0.35 /spl mu/m CMOS工艺技术，研制了一种具有高速I/O电路的1860 kG CMOS门阵列。利用可直接接收和存储低电压摆幅信号的触发器电路，实现了300mhz数据在30cm线上的同步传输。与传统电路相比，该电路技术将2个lsi之间的数据传输延迟时间减少了1.7 ns。
{"title":"A 1860 kG CMOS gate array with GTL input flip-flop circuits","authors":"K. Tomobe, T. Takahashi, M. Kawashima, Y. Sonobe, T. Kiyuna, S. Yamamoto","doi":"10.1109/CICC.1996.510512","DOIUrl":"https://doi.org/10.1109/CICC.1996.510512","url":null,"abstract":"A 1860 kG CMOS gate array with a high speed I/O circuit using 0.35 /spl mu/m CMOS process technology, has been developed. 300 MHz synchronous data transmission through a 30 cm line has been achieved with a flip-flop circuit which can directly receive and store a low voltage swing signal. This circuit technique reduces the latency time of data transmission between 2 LSIs by as much as 1.7 ns compared with conventional circuits.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"106 1","pages":"61-64"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88200331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510523
S. Shigematsu, S. Mutoh, Y. Matsuya
A new power management technique is proposed for low-power, high-speed LSIs. This technique reduces the power consumption and enhances the performance of an LSI by using an embedded small processor to control the sleep modes and the processing of the LSI. Using this technique for a low-power DSP, the total power is reduced to about 10% of one without this technique, while maintaining the speed performance in 1-V LSIs.
{"title":"Power management technique for 1-V LSIs using embedded processor","authors":"S. Shigematsu, S. Mutoh, Y. Matsuya","doi":"10.1109/CICC.1996.510523","DOIUrl":"https://doi.org/10.1109/CICC.1996.510523","url":null,"abstract":"A new power management technique is proposed for low-power, high-speed LSIs. This technique reduces the power consumption and enhances the performance of an LSI by using an embedded small processor to control the sleep modes and the processing of the LSI. Using this technique for a low-power DSP, the total power is reduced to about 10% of one without this technique, while maintaining the speed performance in 1-V LSIs.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"31 1","pages":"111-114"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72896424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510599
A. Chavan, D.W. Stringfellow, S. R. Mallarapu, R. Ardeishar
This paper describes a mixed-signal IC that employs a test architecture consisting of multiple selectable sub-scan chains (SSCs), which the authors have termed "pseudo full scan". This implementation reduces test pattern length and improves fault grading. An additional scan chain of boundary shift register latches (BSRLs) is used to sensitize the analog section of the IC to permit closed-loop testing. A mixed-signal IC using this architecture can be tested with a less expensive digital IC tester. Modeling for standard automatic test pattern generation (ATPG) tools is also presented.
{"title":"A CMOS mixed-signal integrated circuit having a reduced vector set and closed-loop analog test architecture","authors":"A. Chavan, D.W. Stringfellow, S. R. Mallarapu, R. Ardeishar","doi":"10.1109/CICC.1996.510599","DOIUrl":"https://doi.org/10.1109/CICC.1996.510599","url":null,"abstract":"This paper describes a mixed-signal IC that employs a test architecture consisting of multiple selectable sub-scan chains (SSCs), which the authors have termed \"pseudo full scan\". This implementation reduces test pattern length and improves fault grading. An additional scan chain of boundary shift register latches (BSRLs) is used to sensitize the analog section of the IC to permit closed-loop testing. A mixed-signal IC using this architecture can be tested with a less expensive digital IC tester. Modeling for standard automatic test pattern generation (ATPG) tools is also presented.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"5 1","pages":"471-474"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82164806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510548
L. Yuan, Chin-Chi Teng, S. Kang
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power based on the assumption that the power distribution can be characterized by a preassumed function. Large errors can occur when the assumption is not met. To overcome this problem, we propose a nonparametric technique in which no distribution function needs to be assumed. A distribution-independent upper and lower bound of the average power are derived from the Kolmogorov-Smirnov theorem. A stopping criterion is designed based on the bounds for a desired percentage error with a specified confidence level. Since it does not resort to the assumption of any particular distribution function, the technique can be applied to all the circuits irrespective of their power distributions.
{"title":"Nonparametric estimation of average power dissipation in CMOS VLSI circuits","authors":"L. Yuan, Chin-Chi Teng, S. Kang","doi":"10.1109/CICC.1996.510548","DOIUrl":"https://doi.org/10.1109/CICC.1996.510548","url":null,"abstract":"In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power based on the assumption that the power distribution can be characterized by a preassumed function. Large errors can occur when the assumption is not met. To overcome this problem, we propose a nonparametric technique in which no distribution function needs to be assumed. A distribution-independent upper and lower bound of the average power are derived from the Kolmogorov-Smirnov theorem. A stopping criterion is designed based on the bounds for a desired percentage error with a specified confidence level. Since it does not resort to the assumption of any particular distribution function, the technique can be applied to all the circuits irrespective of their power distributions.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"40 1","pages":"225-228"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82953595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510508
A. Tsukamoto, W. Kamisaka, H. Senda, N. Niisoe, H. Aoki, T. Otagaki, Y. Shigeta, M. Asaumi, Y. Miyata, Y. Sano, T. Kuriyama, S. Terakawa
A new pixel technology has been developed for a 1/4-inch 430 k (PAL) pixel IT-CCD (Inter-line Transfer Charge Coupled Device). The new pixel has a thin light shield made of tungsten silicide film and an inner-layer optical micro-lens pre-defined by BPSG flow. This process technology can reduce the pixel size to 22.6 /spl mu/m/sup 2/ with improved sensitivity and reduced smear value. The sensitivity is increased by 30% and the smear value is reduced by 6dB compared to a conventional pixel technology. These characteristics are comparable to a conventional 1/3-inch 560 k pixel IT-CCD with the pixel size of 33.6 /spl mu/m/sup 2/.
{"title":"High sensitivity pixel technology for a 1/4-inch PAL 430 k pixel IT-CCD","authors":"A. Tsukamoto, W. Kamisaka, H. Senda, N. Niisoe, H. Aoki, T. Otagaki, Y. Shigeta, M. Asaumi, Y. Miyata, Y. Sano, T. Kuriyama, S. Terakawa","doi":"10.1109/CICC.1996.510508","DOIUrl":"https://doi.org/10.1109/CICC.1996.510508","url":null,"abstract":"A new pixel technology has been developed for a 1/4-inch 430 k (PAL) pixel IT-CCD (Inter-line Transfer Charge Coupled Device). The new pixel has a thin light shield made of tungsten silicide film and an inner-layer optical micro-lens pre-defined by BPSG flow. This process technology can reduce the pixel size to 22.6 /spl mu/m/sup 2/ with improved sensitivity and reduced smear value. The sensitivity is increased by 30% and the smear value is reduced by 6dB compared to a conventional pixel technology. These characteristics are comparable to a conventional 1/3-inch 560 k pixel IT-CCD with the pixel size of 33.6 /spl mu/m/sup 2/.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"167 1","pages":"39-42"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82641810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510583
S. Krishnamoorthy, A. Khouja
Designers of low power chips are finding it increasingly useful to obtain estimates of average power consumption early in the design phase. They need a fast power estimation capability which gives reasonably accurate power estimates. In this paper, we present some ideas to obtain an efficient implementation of probabilistic power analysis for combinational circuits. These ideas are based on the observation that in order to obtain a fast implementation, it is very important to control the sizes of the Reduced Ordered Binary Decision Diagrams (ROBDDs) that are created during analysis. However, controlling sizes of ROBDDs could impact the accuracy of the result. We explore the consequences of making the trade-off between performance of the implementation and accuracy. Our experimental results illustrate that our implementation can provide estimates that are within 5% of a commonly used probabilistic method and runs 10 times faster, on average. Our method also scales very well for large circuits.
{"title":"Efficient power analysis of combinational circuits","authors":"S. Krishnamoorthy, A. Khouja","doi":"10.1109/CICC.1996.510583","DOIUrl":"https://doi.org/10.1109/CICC.1996.510583","url":null,"abstract":"Designers of low power chips are finding it increasingly useful to obtain estimates of average power consumption early in the design phase. They need a fast power estimation capability which gives reasonably accurate power estimates. In this paper, we present some ideas to obtain an efficient implementation of probabilistic power analysis for combinational circuits. These ideas are based on the observation that in order to obtain a fast implementation, it is very important to control the sizes of the Reduced Ordered Binary Decision Diagrams (ROBDDs) that are created during analysis. However, controlling sizes of ROBDDs could impact the accuracy of the result. We explore the consequences of making the trade-off between performance of the implementation and accuracy. Our experimental results illustrate that our implementation can provide estimates that are within 5% of a commonly used probabilistic method and runs 10 times faster, on average. Our method also scales very well for large circuits.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"62 1","pages":"393-396"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87700375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510584
C. Gebotys
Although memory has been shown to be a crucial component of the total system energy dissipation, few low energy memory design techniques exist. This paper presents for the first time a network flow approach to minimizing the energy dissipation of memory components during systems synthesis. The number of external and internal memory accesses and the number of extra computations (or data regeneration) for each task is optimized to minimize the total estimated system energy dissipation. This is unlike previous research which has only discussed adhoc suggestions for this problem. Results for a large complex real industrial application, audio compression, donated by Motorola, show that estimated energy savings of 2 to 10 times per task contributed 2.7 times energy savings for the embedded system. This research is important for industry since energy dissipation consideration at the early stages of design is crucial for mapping high performance applications into cost-efficient and reliable systems.
{"title":"Low energy memory component design for cost-sensitive high performance embedded systems","authors":"C. Gebotys","doi":"10.1109/CICC.1996.510584","DOIUrl":"https://doi.org/10.1109/CICC.1996.510584","url":null,"abstract":"Although memory has been shown to be a crucial component of the total system energy dissipation, few low energy memory design techniques exist. This paper presents for the first time a network flow approach to minimizing the energy dissipation of memory components during systems synthesis. The number of external and internal memory accesses and the number of extra computations (or data regeneration) for each task is optimized to minimize the total estimated system energy dissipation. This is unlike previous research which has only discussed adhoc suggestions for this problem. Results for a large complex real industrial application, audio compression, donated by Motorola, show that estimated energy savings of 2 to 10 times per task contributed 2.7 times energy savings for the embedded system. This research is important for industry since energy dissipation consideration at the early stages of design is crucial for mapping high performance applications into cost-efficient and reliable systems.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"76 1","pages":"397-400"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84941410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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